Hot Chips 32 /2020 / Official-recording Q&A
Useful compute needs the whole machine.
Recovered Q&A probed whether heterogeneous machines could be fed, programmed, isolated and measured as useful systems. Memory economics, software behavior and degraded operation qualified peak compute rather than following from it.
Updated 2 October 2026 · Analyst interpretation of historical disclosures
Where audience questions concentrated
126 eligible audience asks across 12/12 caption-recovered recordings. Leading themes: execution and dataflow: 18 (14.3%); memory bandwidth and capacity: 16 (12.7%); scale-up and scale-out fabrics: 16 (12.7%). S5, FPGAs and Reconfigurable Architectures, contributes the most eligible asks. Conservative attribution leaves many CPU prompts outside the audience matrix; zero CPU-theme cells do not establish absent CPU interest.
Darker cells mean more recovered asks on one raw-count scale. Both axes rank by marginal counts. Missing-caption sessions are hatched; available recordings with no eligible ask are true reviewed zeros. Q&A time is not normalized.
Counts, coverage and session key
Caption response status in the audience subset: answered 58; deferred 10; deflected 8; partial 49; unclear 1. Unclear denotes missing or unintelligible caption evidence, rather than proof that no answer was spoken.
Reviewed timestamped automatic English captions, without independent audio verification. 206 audit rows; 80 excluded from the audience heatmap. Recorded origins: 127 audience, 20 moderator, 59 unknown. Unintelligible and out-of-scope asks are also excluded. One independently answerable technical ask has one primary theme; separate requested facts can count separately within an exchange.
Two tutorial exports are partial: the unreviewed tails are missing coverage; T1 also omits approximately the first 15 minutes in the official recording. Caption omissions can hide questions and answers even in recovered recordings. Answer status describes what the vendor said, rather than independently verified truth. Attention is not market importance, adoption or investment merit. No Slack content was accessed.
- K1 No Transistor Left Behind — official recording ↗
- K2 AI Research at Scale — Opportunities on the Road Ahead — official recording ↗
- S1 Server Processors — official recording ↗
- S2 Mobile Processors — official recording ↗
- S3 Edge Computing and Sensing — official recording ↗
- S4 GPUs and Gaming Architectures — official recording ↗
- S5 FPGAs and Reconfigurable Architectures — official recording ↗
- S6 Networking and Distributed Systems — official recording ↗
- S7 ML Training — official recording ↗
- S8 ML Inference — official recording ↗
- T1 Machine Learning Scale Out — official recording ↗
- T2 Quantum Computing — official recording ↗
Download exact session/theme counts (CSV) · Two-page Executive Brief
Patterns in the reviewed Q&A
Memory choice follows workload and economics.
Pensando justified HBM-to-DDR migration through capacity flexibility, buffering and cost. Tenstorrent distinguished inference LPDDR4 from training GDDR6. Xbox balanced GPU bandwidth with CPU latency. No single memory hierarchy won every workload. S6 59:20 ↗
Useful scale includes failed links.
Tofino telemetry distinguished local timing from WAN synchronization. Fungible emphasized connectivity; TPU Pod recovery details remained incomplete. Cerebras described redundant cores and routes. Nominal line rate did not establish degraded-mode behavior. T1 106:31 ↗
Placement and compilation remain deployment work.
Versal relocation depended on repeated fabric patterns. Tenstorrent claimed dynamic-graph support; Cerebras described typical compilation in minutes. These answers did not establish general operator coverage, difficult-model compile tails or effortless placement changes. S5 61:58 ↗
Security and lifetime need operating evidence.
Ice Lake encryption overhead came from unspecified preproduction experiments; Tiger Lake withheld latency figures. Lightmatter discussed manufacturing precedents without quantitative array lifetime evidence. Targets and precedent left qualification gaps. S1 45:43 ↗
Benchmarks need full pipeline boundaries.
DeepMind treated MLPerf as useful but insufficient for evolving research. Lightmatter separated simulator results and analog timing from measured digital performance. Conversion, transfers, host work and workload diversity remained essential comparison terms. K2 56:27 ↗
Implications and concrete vendor asks
Analyst inference: these present-day acceptance tests follow from historical uncertainties. Historical statements and roadmap promises do not establish later delivery.
| Decision and timing | Vendor ask and decision test |
|---|---|
| Memory configuration Before sizing | Sweep working sets, concurrency and batch. Compare capacity pressure, effective bandwidth, p99 latency, power and delivered system cost. |
| Scale and availability Before cluster commitment | Run fixed-work scaling and adversarial traffic at the target topology. Inject link/node failures; measure recovery, lost work and completion tails. |
| Compiler/runtime readiness During proof of concept | Use independent models with dynamic control flow. Measure unsupported operations, relocation recompilation, compile-time distributions and debugging effort. |
| Isolation and durability Before qualification sign-off | Test encrypted operation and cross-tenant reassignment. Request photonic drift, lifetime, yield and recalibration distributions under the deployed operating envelope. |
| Performance comparison Before purchasing | Reproduce same-batch, same-quality results on delivered silicon, including conversion, host work and transfers. Expand the corpus beyond a fixed benchmark suite. |
Sources and scope
Official Hot Chips 32 recordings, caption exports recovered2 October 2026. Source anchors link to the recorded exchanges. Patterns may use reviewed moderator or unattributed technical exchanges; plotted counts use the audience-only filter. The evidence ledger retains attribution, answer gaps and exclusion reasons.