{ "vendor": "Qualcomm", "cutoff": "2026-09-28", "sections": [ { "id": "01", "title": [ "Scope and executive synthesis", "研究范围与执行摘要" ], "blocks": [ { "id": "01.scope", "type": "prose", "text": [ "Families and weights: deep on Centriq/Oryon/Dragonfly CPUs and Cloud AI/Dragonfly accelerators; full on datacenter connectivity; proportional on client, edge and RAN derivatives.\nStart: 2015, including the first server effort and the mobile technology baseline.\nCutoff: 28 September 2026; current disclosures include Investor Day and AI Infra Summit 2026.\nFocus: CPU lineage, inference dataflow, memory capacity/bandwidth, fabric and rack integration.\nExclusions: exhaustive handset/modem SKUs; no merchant datacenter training GPU or separately specified Qualcomm AI NIC is established by the reviewed portfolio.", "产品权重：深入研究 Centriq／Oryon／Dragonfly CPU 和 Cloud AI／Dragonfly 加速器；完整覆盖数据中心高速连接；适度覆盖客户端、边缘和 RAN 衍生产品。\n起点：2015 年，涵盖首轮服务器尝试与移动技术基线。\n截止：2026 年 9 月 28 日，最新披露包括 Investor Day 和 AI Infra Summit 2026。\n重点：CPU 谱系、推理数据流、内存容量与带宽、互联及机架集成。\n不含：所有手机／调制解调器 SKU 的穷尽清单；已审阅产品版图未确立商用数据中心训练 GPU，或具有独立完整规格的 Qualcomm AI NIC。" ], "sources": [ "C01", "P08", "E07" ] }, { "id": "01.thesis", "type": "prose", "text": [ "Qualcomm’s infrastructure history is not a continuous server-CPU succession. Centriq was a real commercial Arm server processor, but the next major CPU story comes through Nuvia-derived Oryon client products and the future Dragonfly C1000. In parallel, Cloud AI 100 establishes a dedicated inference architecture, Ultra expands model capacity through a multi-SoC card, and AI200/AI250/AI300 move the product boundary to the rack. Connectivity assets from Alphawave and software from Modular complete parts of that broader platform.", "Qualcomm 的基础设施史不是连续的服务器 CPU 换代。Centriq 是真正商用的 Arm 服务器处理器，但下一段重要 CPU 路线来自 Nuvia 衍生的 Oryon 客户端产品和未来的 Dragonfly C1000。与此同时，Cloud AI 100 建立专用推理架构，Ultra 通过多 SoC 卡提高模型容量，AI200／AI250／AI300 则将产品边界扩展到机架。来自 Alphawave 的连接技术和 Modular 的软件补齐了这一更广泛平台的部分能力。" ], "sources": [ "E02", "P01", "E05", "P08", "E08", "E14" ] }, { "id": "01.finding", "type": "prose", "text": [ "The dominant architectural bet is inference efficiency rather than reproducing a general-purpose training GPU. Large local capacity can reduce model partitioning, and near-memory execution can reduce the cost of moving weights during decode. These benefits are conditional on dataflow, model placement and software. AI250’s effective HBC bandwidth must therefore remain separate from conventional external-memory bandwidth. The platform’s long-term CPU and accelerator roadmap extends beyond the cutoff: C1000 production is planned for the second half of 2028, not a shipping 2026 server.", "其主要架构选择是提高推理效率，而不是复制通用训练 GPU。较大的本地容量可以减少模型切分，近内存执行可以降低解码时搬运权重的成本。但收益取决于数据流、模型放置与软件，因此 AI250 的 HBC 有效带宽必须与常规外部内存带宽区分。平台的长期 CPU 与加速器路线延伸至研究截止日期之后：C1000 计划于 2028 年下半年投产，并非 2026 年已商用服务器。" ], "sources": [ "P05", "P08", "E10" ] } ] }, { "id": "02", "title": [ "Units, product boundaries and roadmap status", "数值口径、产品边界与路线图状态" ], "blocks": [ { "id": "02.units", "type": "prose", "text": [ "A die, card, server and rack are different accounting scopes. Cloud AI 100 Ultra contains four SoCs; its 128 GB memory and 576 MB SRAM are card totals. AI200’s 43 TB is a rounded rack capacity, whereas 768 GB is per card. Rack power is not card TBP. Bandwidth is decimal GB/s or TB/s, and link direction is stated explicitly. PCIe headline bandwidth is a raw interface budget before protocol overhead. Ethernet Gb/s must be divided by eight before comparison with memory GB/s.", "裸片、板卡、服务器和机架属于不同统计范围。Cloud AI 100 Ultra 包含四颗 SoC，其 128 GB 内存和 576 MB SRAM 均为整卡总量。AI200 的 43 TB 是四舍五入后的机架容量，768 GB 则属于每卡。机架功耗不等于板卡 TBP。带宽采用十进制 GB/s 或 TB/s，并明确链路方向；PCIe 标称带宽是未扣除协议开销的接口预算；以太网 Gb/s 与内存 GB/s 比较前必须先除以八。" ], "sources": [ "P01", "P04" ] }, { "id": "02.compute", "type": "prose", "text": [ "The standard accelerator table preserves dense BF16, FP8, FP6/FP4 and FP64 columns. Where the reviewed evidence supplies FP16 or INT8 instead, those values are reported separately rather than relabelled. n/d means not established; n/a means not applicable. A product announcement, customer sampling, a demonstration and general availability are different milestones. In particular, AI200’s 2025 launch forecast of 2026 availability is followed by a 2026 investor roadmap labelled sampling FY26; the reviewed September demo does not alone establish broad GA.", "统一加速器表保留稠密 BF16、FP8、FP6／FP4 和 FP64 字段。如果资料提供的是 FP16 或 INT8，则单独列示，不能换标签填入。n/d 表示未确定，n/a 表示不适用。产品发布、客户送样、演示和正式商用属于不同里程碑。特别是，AI200 在 2025 年发布时预测于 2026 年商用，而 2026 年投资者路线图标为 FY26 送样；已审阅的 9 月演示本身不能证明广泛 GA。" ], "sources": [ "E06", "P08", "E07" ] } ] }, { "id": "03", "title": [ "CPU generation atlas", "CPU 代际总览" ], "blocks": [ { "id": "cpu", "type": "table", "table": "cpu" }, { "id": "03.cpuwarning", "type": "prose", "text": [ "Client entries explain the core-development lineage; their memory, power and I/O are not server specifications. C1000 is not a socketed Snapdragon X2 Elite. Nor does the acquisition of Ventana make C1000 a RISC-V processor: Qualcomm explicitly identifies Oryon server cores for C1000, while Ventana adds a separate RISC-V capability. No second commercial Centriq generation is established here.", "客户端条目用于解释核心开发谱系，其内存、功耗和 I/O 不是服务器规格。C1000 不是插槽版 Snapdragon X2 Elite。收购 Ventana 也不意味着 C1000 是 RISC-V 处理器：Qualcomm 明确将 C1000 与 Oryon 服务器核心关联，而 Ventana 补充另一条 RISC-V 能力。本报告没有确认第二代商用 Centriq。" ], "sources": [ "P07", "E13" ] } ] }, { "id": "04", "title": [ "Centriq and Falkor: the first server architecture", "Centriq 与 Falkor：首轮服务器架构" ], "blocks": [ { "id": "04.falkor", "type": "prose", "text": [ "Centriq 2400 began sampling in 2016 and commercially shipped in November 2017. Falkor is a custom, single-threaded, AArch64-only core. Hot Chips describes an issue path accepting three instructions plus a direct branch and dispatch of up to eight internal operations. A two-core duplex shares L2 and a QSB interface. The segmented bidirectional coherent ring uses shortest-path routing; its reported aggregate bandwidth above 250 GB/s is an internal-fabric figure, not six-channel DDR payload bandwidth.", "Centriq 2400 于 2016 年开始送样，2017 年 11 月商业出货。Falkor 是自定义、单线程、仅支持 AArch64 的核心。Hot Chips 描述的发射路径可接受三条指令加一条直接分支，内部最多分派八个操作。双核 duplex 共享 L2 和 QSB 接口。分段双向一致性环采用最短路径路由；所报超过 250 GB/s 的聚合带宽属于内部互联，不能当作六通道 DDR 有效带宽。" ], "sources": [ "C01", "E01", "E02" ] }, { "id": "04.centriqcache", "type": "prose", "text": [ "The duplex L2 uses 128-byte cache lines, ECC and an inclusive relationship to L1 data caches. The disclosed minimum L2 hit latency is fifteen cycles. Distributed L3 includes allocation controls for quality of service, an important feature when many independent tenants share a socket. Six DDR4 channels and 32 PCIe 3 lanes define a balanced scale-out server of its time, but offer a much smaller external accelerator budget than later AI hosts. At 48 cores, approximately 128 GB/s of channel bandwidth means about 2.67 GB/s per core before contention and protocol effects.", "duplex 的 L2 使用 128 字节缓存行和 ECC，并对 L1 数据缓存保持包含关系，披露的最小 L2 命中延迟为十五周期。分布式 L3 带有服务质量分配控制，适合许多独立租户共享插槽。六通道 DDR4 和 32 条 PCIe 3 通道构成当时较均衡的横向扩展服务器，但外部加速器连接预算明显小于后来的 AI 主机。48 核均分约 128 GB/s 通道带宽，在尚未计入竞争和协议影响前，每核约 2.67 GB/s。" ], "sources": [ "C01", "E02" ] }, { "id": "04.centriqimplementation", "type": "prose", "text": [ "The launch disclosure identifies Samsung 10 nm, 18 billion transistors and a 398 mm2 monolithic die. This is implementation evidence even though a matching full Centriq ISSCC paper was not established in the reviewed sources. OCP 2017 supplies the system connection: Qualcomm and Microsoft demonstrated a Centriq-based Open Compute motherboard. That collaboration is evidence of platform development, not proof of Azure public-instance GA. The later break in the server roadmap means that commercial continuity cannot be inferred from the technical quality of Falkor.", "发布资料明确三星 10 nm、180 亿晶体管和 398 mm2 单裸片。尽管已审阅资料未确认对应的完整 Centriq ISSCC 论文，这仍构成实现证据。OCP 2017 补充系统层联系：Qualcomm 与 Microsoft 展示了基于 Centriq 的 Open Compute 主板。这证明平台开发合作，不能证明 Azure 公共实例已正式商用。后续服务器路线中断，也说明不能从 Falkor 的技术质量推断商业连续性。" ], "sources": [ "E02", "E12" ] } ] }, { "id": "05", "title": [ "Oryon: client silicon rebuilds the CPU lineage", "Oryon：通过客户端芯片重建 CPU 谱系" ], "blocks": [ { "id": "05.oryon", "type": "prose", "text": [ "The 2021 Nuvia acquisition leads to the Oryon CPU introduced in Snapdragon X Elite and commercial PCs in 2024. Hot Chips 2024 and its IEEE Micro follow-up provide the architectural anchor. Three four-core clusters combine substantial near-core cache with a wide out-of-order machine. The design emphasizes instruction supply, branch recovery and outstanding memory operations rather than width alone. The core’s client implementation demonstrates engineering capability; it does not demonstrate server RAS, multi-socket coherence or datacenter memory capacity.", "2021 年收购 Nuvia 后，Oryon CPU 出现在 Snapdragon X Elite 中，并于 2024 年进入商业 PC。Hot Chips 2024 及后续 IEEE Micro 文章构成架构依据。三个四核簇将较大的近核缓存与宽乱序执行结合；重点不仅是执行宽度，还包括指令供给、分支恢复和未完成访存操作。客户端实现证明了核心工程能力，但不代表已证明服务器 RAS、多插槽一致性或数据中心内存容量。" ], "sources": [ "C05", "C08", "C02", "E15" ] }, { "id": "05.oryon-details", "type": "prose", "text": [ "Qualcomm’s Hot Chips 2024 slides give the first Oryon core a 192 KB instruction cache, a 96 KB data cache, eight-instruction decode and eight-micro-op retirement. Six integer and four 128-bit vector execution pipes feed a wide out-of-order machine. The load/store system supports up to four operations per cycle, with a 192-entry load queue and 56-entry store queue. Four cores share a 12 MB L2 at CPU frequency; three clusters connect through a fabric with 6 MB system-level cache to a 135 GB/s LPDDR5X interface. These layers explain why the advertised 42 MB cache total is neither a per-core cache nor a unified last-level cache.", "Qualcomm 的 Hot Chips 2024 幻灯片给出第一代 Oryon 的具体组织：192 KB 指令缓存、96 KB 数据缓存、每周期解码八条指令及提交八个微操作。六条整数与四条 128 位向量执行流水线支撑宽乱序机器。访存系统每周期最多处理四个操作，配有 192 项加载队列和 56 项存储队列。四核共享以 CPU 频率运行的 12 MB L2；三个簇通过互联连接 6 MB 系统级缓存及 135 GB/s LPDDR5X 接口。因此，宣传中的 42 MB 总缓存既不是每核缓存，也不是统一的末级缓存。" ], "sources": [ "C08" ] }, { "id": "05.oryon2", "type": "prose", "text": [ "Oryon then crosses into mobile and the third-generation core returns to Snapdragon X2 Elite. The X2E-96-100 reference combines twelve Prime cores with six Performance cores, 53 MB total CPU cache and 228 GB/s LPDDR5X bandwidth. Its 80 TOPS Hexagon NPU is a separate engine, not CPU vector throughput. The mixed core organization and OEM power envelope are client choices. For the server report, the important continuity is custom core design, cache and power-management expertise, and a common software ISA; memory channels and host links must be re-established for C1000.", "Oryon 随后进入移动产品，第三代核心又用于 Snapdragon X2 Elite。X2E-96-100 参考型号组合十二个 Prime 核心与六个 Performance 核心，具有 53 MB CPU 总缓存和 228 GB/s LPDDR5X 带宽。其 80 TOPS Hexagon NPU 是独立引擎，不是 CPU 向量吞吐。混合核心组织和 OEM 功耗范围属于客户端选择。对于服务器研究，重要的连续性是定制核心设计、缓存和电源管理经验，以及共同软件 ISA；C1000 的内存通道与主机接口仍须独立核验。" ], "sources": [ "P12" ] }, { "id": "05.circuit", "type": "prose", "text": [ "ISSCC/JSSC-related circuit work explains another part of Qualcomm’s efficiency heritage. Keith Bowman’s adaptive-clock research senses supply droop and adjusts clock behavior to avoid paying a permanent worst-case timing margin. The documented Snapdragon 820 connection makes that a legitimate example of research reaching a product. It does not establish that Centriq, Oryon or C1000 uses an identical circuit. The ISSCC 2025 edge-generative-AI tutorial is useful system context, not a transistor-level disclosure of a Dragonfly accelerator.", "与 ISSCC／JSSC 相关的电路研究解释了 Qualcomm 能效积累的另一部分。Keith Bowman 的自适应时钟研究感知电源压降并调整时钟行为，避免持续付出最坏情况时序裕量。资料明确将其与 Snapdragon 820 联系，因而是研究进入产品的有效例子，但不能据此确认 Centriq、Oryon 或 C1000 使用完全相同电路。ISSCC 2025 的边缘生成式 AI 教程提供系统背景，并不是 Dragonfly 加速器的晶体管级披露。" ], "sources": [ "C04", "C03" ] } ] }, { "id": "06", "title": [ "Dragonfly C1000 and the RISC-V branch", "Dragonfly C1000 与 RISC-V 分支" ], "blocks": [ { "id": "06.c1000", "type": "prose", "text": [ "Investor Day 2026 announces a chiplet-based C1000 with more than 250 custom Oryon server cores, a core-frequency target above 5 GHz, PCIe 7/CXL connectivity and an LPDDR memory subsystem. Optional HBC attachment is part of the disclosed direction. The architectural shift from Centriq is substantial: a larger package-level design and a CPU positioned around agent orchestration, general cloud services and accelerator head-node work. The Meta agreement places first-generation production in the second half of 2028 and anticipates subsequent generations.", "Investor Day 2026 公布基于芯粒的 C1000：超过 250 个自定义 Oryon 服务器核心，核心频率目标超过 5 GHz，支持 PCIe 7／CXL，并采用 LPDDR 内存子系统。可选 HBC 连接也属于已披露方向。与 Centriq 相比，变化十分显著：更大的封装级设计，以及面向智能体编排、通用云服务和加速器主节点的 CPU 定位。Meta 合作将首代投产时间设在 2028 年下半年，并计划后续代际。" ], "sources": [ "P08", "P07", "E10" ] }, { "id": "06.c1000limits", "type": "prose", "text": [ "The headline I/O claim of more than 2 TB/s is not normalized here to a lane count or one-way payload figure, because the disclosed direction and aggregation basis are insufficient. Cache sizes, memory-channel count, process partitioning, socket coherence and SKU TDP remain material disclosure gaps. LPDDR can reduce memory energy, but capacity, serviceability, packaging and board topology must be evaluated together. An announced frequency and a core-count ceiling are not evidence that every core sustains that clock at the eventual package power limit.", "超过 2 TB/s 的 I/O 宣传值在此不换算为通道数或单向有效载荷带宽，因为披露的方向与聚合口径不足。缓存大小、内存通道数、工艺分工、插槽一致性和 SKU TDP 仍是实质性披露缺口。LPDDR 可以降低内存能耗，但必须结合容量、可维护性、封装和板级拓扑评价。公布的频率和核心上限，并不能证明最终封装功耗约束下所有核心都能持续运行在该频率。" ], "sources": [ "P08" ] }, { "id": "06.ventana", "type": "prose", "text": [ "Qualcomm acquired Ventana in December 2025, adding RISC-V CPU expertise alongside Oryon. Ventana’s earlier Veyron compute-chiplet work is relevant as an acquired design capability, but the reviewed Qualcomm disclosure does not define a shipping successor SKU or transfer its specifications to C1000. The two instruction-set paths should therefore remain separate in a portfolio map. Their potential common ground is physical design, chiplet integration, verification and server software engineering, rather than binary compatibility.", "Qualcomm 于 2025 年 12 月收购 Ventana，在 Oryon 之外增加 RISC-V CPU 专长。Ventana 此前的 Veyron 计算芯粒工作作为被收购设计能力具有相关性，但已审阅 Qualcomm 公告没有定义已商用后继 SKU，也不能将其规格转移给 C1000。因此，产品版图应将两条指令集路线分开。可能共享的是物理设计、芯粒集成、验证和服务器软件工程，而不是二进制兼容性。" ], "sources": [ "E13" ] } ] }, { "id": "07", "title": [ "Accelerator generation atlas", "加速器代际总览" ], "blocks": [ { "id": "accelerators", "type": "table", "table": "accelerators" }, { "id": "publishedcompute", "type": "table", "table": "publishedcompute" } ] }, { "id": "08", "title": [ "Cloud AI 100: programmable inference dataflow", "Cloud AI 100：可编程推理数据流" ], "blocks": [ { "id": "08.aic", "type": "prose", "text": [ "The 2019 announcement is followed by selected-customer shipments in 2020 and commercial system activity in 2021. Hot Chips 2021 presents the inference architecture. Each AI core separates tensor, vector and scalar work. Tensor units handle the dense linear algebra; vector units process elementwise and other non-matrix operations; a multithreaded VLIW scalar processor coordinates execution. This is not a GPU warp machine. The compiler must expose parallelism, schedule movement and keep specialized engines occupied across a model graph.", "2019 年发布之后，产品于 2020 年向特定客户出货，并在 2021 年进入商业系统活动。Hot Chips 2021 展示其推理架构。每个 AI 核心将张量、向量和标量工作分开：张量单元处理稠密线性代数，向量单元处理逐元素及其他非矩阵操作，多线程 VLIW 标量处理器协调执行。它不是 GPU 的 warp 执行机器；编译器需要显露并行性、调度数据移动，并在模型图中保持专用引擎忙碌。" ], "sources": [ "E03", "E04", "C06", "P01" ] }, { "id": "08.aicmemory", "type": "prose", "text": [ "The SDK describes 8 MB vector tightly coupled memory and 1 MB shared L2 within each nominal AI core, producing 144 MB of on-chip storage across sixteen cores. Separate compute, memory and configuration networks serve different traffic classes. External LPDDR4X provides capacity; local SRAM provides reuse and predictable scheduling. DMA and tiling are therefore first-class architectural mechanisms. A model that reuses weights or activations locally can amortize external traffic, while a large decode workload repeatedly reading weights can become memory-bound despite substantial tensor capacity.", "SDK 描述每个标称 AI 核心具有 8 MB 向量紧耦合内存和 1 MB 共享 L2，十六个核心合计 144 MB 片上存储。计算、内存和配置网络分别服务不同流量类型。外部 LPDDR4X 提供容量，本地 SRAM 提供复用和可预测调度，因此 DMA 与分块是核心架构机制。能够在本地复用权重或激活的模型可以摊薄外部流量，而反复读取权重的大模型解码即使拥有可观张量算力，也可能受内存限制。" ], "sources": [ "P01", "P02" ] }, { "id": "08.sku", "type": "prose", "text": [ "Standard, Pro and the early DM.2 variants address different power and deployment envelopes. The SoC’s architectural peak, an initial launch target and a shipping card’s rated clock point are not interchangeable. For this reason the report uses the explicit Standard/Pro SKU table for card-level comparisons. Host PCIe 4 x8 provides about 15.75 GB/s per direction before protocol overhead, far below the card’s 137 GB/s memory figure. Keeping model state resident on the card is consequently much more attractive than repeatedly streaming it across the host link.", "Standard、Pro 与早期 DM.2 变体面向不同功耗和部署范围。SoC 架构峰值、首发目标与商用板卡的额定时钟工作点不能互换，因此本报告用明确的 Standard／Pro SKU 表进行整卡比较。主机 PCIe 4 x8 在未扣除协议开销前单方向约为 15.75 GB/s，明显低于整卡 137 GB/s 内存带宽。因此，让模型状态驻留在卡上，比反复通过主机链路传输更有利。" ], "sources": [ "P01", "P02" ] } ] }, { "id": "09", "title": [ "Cloud AI 100 Ultra: capacity by replication", "Cloud AI 100 Ultra：通过复制增加容量" ], "blocks": [ { "id": "09.ultra", "type": "prose", "text": [ "Ultra combines four Cloud AI 100 SoCs and a PCIe switch on a 150 W card. Each SoC has its own local memory; the card totals 128 GB LPDDR4X, 576 MB SRAM and 548 GB/s of summed memory bandwidth. The host interface expands to PCIe 4 x16, while each SoC attaches to the switch over x8. Four chips on one board do not create one uniform-latency shared SRAM or one unconstrained 548 GB/s path for every operation. Model partitioning and communication scheduling remain necessary.", "Ultra 在一张 150 W 板卡上组合四颗 Cloud AI 100 SoC 和一个 PCIe 交换机。每颗 SoC 具有本地内存，整卡合计 128 GB LPDDR4X、576 MB SRAM 和 548 GB/s 内存带宽总和。主机接口扩展为 PCIe 4 x16，每颗 SoC 通过 x8 连接交换机。将四颗芯片放在一块板上，并不会形成统一延迟的共享 SRAM，也不会让每个操作都能无约束地使用 548 GB/s；仍需要模型切分和通信调度。" ], "sources": [ "P01", "P03" ] }, { "id": "09.ultrallm", "type": "prose", "text": [ "The 2023 product is explicitly positioned around generative inference. Its capacity allows some large quantized models to remain on one card, reducing the number of boards and host/network crossings. That is a model-placement advantage, not evidence of higher training throughput. Weight precision, KV-cache size, context length and batch size determine whether a model fits. Independent 2025 NRP measurements confirm that the platform can be used for real LLM serving, but their energy ratios depend on the selected models, comparison configurations and utilization; they are not portable chip-level efficiency constants.", "2023 年产品明确面向生成式推理。其容量使部分大型量化模型可以驻留单卡，减少板卡数量以及跨主机／网络传输。这是模型放置优势，不是更高训练吞吐的证据。权重精度、KV 缓存、上下文长度和批量决定模型能否容纳。2025 年 NRP 的独立测量确认平台可用于实际 LLM 服务，但其能效比取决于模型、对照配置和利用率，不能作为通用芯片级效率常数。" ], "sources": [ "E05", "R01" ] } ] }, { "id": "10", "title": [ "AI200: the inference rack becomes the product", "AI200：推理机架成为产品" ], "blocks": [ { "id": "10.ai200", "type": "prose", "text": [ "AI200 moves from a low-power PCIe-card story to a rack-scale inference platform. The published configuration contains 56 cards, 768 GB LPDDR per card, approximately 43 TB per rack and 0.414 PB/s aggregate memory bandwidth. It specifies PCIe 6 scale-up and Ethernet/RoCE scale-out in an ORv3 rack, with a 140 kW liquid-cooled configuration. Dividing rack memory bandwidth by 56 gives approximately 7.39 TB/s per card as an arithmetic average. It does not disclose a single die’s memory interface or prove equal bandwidth for every placement.", "AI200 从低功耗 PCIe 卡扩展为机架级推理平台。公开配置包含 56 张卡、每卡 768 GB LPDDR、每机架约 43 TB，以及 0.414 PB/s 聚合内存带宽。ORv3 机架采用 PCIe 6 纵向扩展和以太网／RoCE 横向扩展，液冷配置功耗为 140 kW。将机架内存带宽除以 56，可得每卡算术平均约 7.39 TB/s，但这没有披露单裸片内存接口，也不保证每种数据放置都能获得相等带宽。" ], "sources": [ "P04" ] }, { "id": "10.ai200system", "type": "prose", "text": [ "A September 2026 demonstration places Kimi-K2.5 on a single AI200 card. That is relevant evidence for model-capacity and software progress, but the demo does not establish sustained throughput, response-time distribution, model precision or broad customer availability. Architecturally, the large capacity can reduce weight sharding, while PCIe scale-up and RoCE still have to move activations, expert-routing traffic and collectives. Model residency and communication efficiency solve different constraints.", "2026 年 9 月的演示将 Kimi-K2.5 放在单张 AI200 卡上，体现模型容量和软件进展，但不能据此确定持续吞吐、响应时间分布、模型精度或广泛客户可用性。较大容量可以减少权重分片，但 PCIe 纵向连接和 RoCE 仍需搬运激活、专家路由流量及集合通信数据。模型驻留和通信效率解决的是不同约束。" ], "sources": [ "E07", "P04" ] } ] }, { "id": "11", "title": [ "AI250 and AI300: near-memory execution", "AI250 与 AI300：近内存执行" ], "blocks": [ { "id": "11.hbc", "type": "prose", "text": [ "AI250 introduces High Bandwidth Compute Gen 1, with a published 133 TB/s effective memory bandwidth per card and 7.4 PB/s per rack. Qualcomm describes this as eighteen times AI200’s effective bandwidth. The key mechanism is moving computation closer to memory, so a useful computation need not pay the same external data movement as a conventional processor reading every operand over a memory bus. Effective bandwidth is a workload/architecture equivalence metric; treating it as an ordinary HBM pin-rate specification would produce a misleading roofline comparison.", "AI250 引入第一代 High Bandwidth Compute（HBC），公布每卡 133 TB/s、每机架 7.4 PB/s 的有效内存带宽，Qualcomm 将其描述为 AI200 有效带宽的十八倍。关键机制是将计算靠近内存，使有效运算不必像常规处理器那样，经外部内存总线读取每个操作数。有效带宽是一种工作负载／架构等效指标，若把它当作普通 HBM 引脚速率，就会得到误导性的 Roofline 比较。" ], "sources": [ "P05", "P08" ] }, { "id": "11.hbcworkload", "type": "prose", "text": [ "The natural target is memory-sensitive decode and long-context serving. Prefill may remain more compute-intensive, so disaggregating the phases can improve resource matching but adds transfer and scheduling costs. HBC’s practical value depends on which operators execute near memory, the precision they support, locality across memory partitions, and how intermediate results reach the rest of the machine. The public investor material outlines the approach but does not disclose enough circuit, stack or inter-die detail to reconstruct a complete implementation.", "自然目标是对内存敏感的解码和长上下文服务。预填充可能仍偏计算密集，因此分离两阶段可以改善资源匹配，但也增加传输与调度成本。HBC 的实际价值取决于哪些算子能在近内存执行、支持何种精度、跨内存分区的局部性，以及中间结果如何到达其他执行单元。公开投资者资料说明了方向，但电路、堆叠和裸片间细节不足以还原完整实现。" ], "sources": [ "P08", "P05" ] }, { "id": "11.ai300", "type": "prose", "text": [ "AI300 extends the roadmap to HBC Gen 2, with UALink/ESUN scale-up, copper and optical scale-out, and a single-hop all-to-all rack objective. The investor roadmap quotes a fifty-four-times AI200 effective-bandwidth target. This is a future architecture claim, not measured shipping throughput. C1000 is shown as the future CPU partner. Per-card link rates, radix, packet semantics, memory capacity and complete power limits remain undisclosed in the reviewed material, so the report does not manufacture a rack bisection figure.", "AI300 将路线扩展至第二代 HBC，计划使用 UALink／ESUN 纵向扩展、铜缆和光横向扩展，并以单跳全互连机架为目标。投资者路线图给出的有效带宽目标为 AI200 的五十四倍。这是未来架构目标，不是商用测量吞吐；C1000 被列为未来配套 CPU。已审阅资料尚未披露每卡链路速率、交换基数、报文语义、内存容量和完整功耗，因此本报告不虚构机架二分带宽。" ], "sources": [ "P06", "P08" ] } ] }, { "id": "12", "title": [ "Connectivity: from Alphawave assets to Dragonfly DSPs", "高速连接：从 Alphawave 到 Dragonfly DSP" ], "blocks": [ { "id": "12.alphawave", "type": "prose", "text": [ "The Alphawave transaction closed on 18 December 2025, earlier than the original 2026 expectation. It adds high-speed wired connectivity and custom-silicon capabilities, which matter because a rack platform needs more than compute engines. The 2026 portfolio spans electrical SerDes, die-to-die interfaces, optical DSPs, active electrical cable retimers and custom silicon. A protocol controller, a PHY, a retimer, an optical module and a complete NIC occupy different layers; they must not be collapsed into a single AI-networking product count.", "Alphawave 交易于 2025 年 12 月 18 日完成，早于最初预期的 2026 年。收购增加高速有线连接和定制芯片能力，对需要完整系统的机架平台十分重要。2026 年版图涵盖电 SerDes、裸片间接口、光 DSP、有源电缆重定时器和定制芯片。协议控制器、PHY、重定时器、光模块和完整 NIC 位于不同层次，不能合并为同一种 AI 网络产品。" ], "sources": [ "E08", "P08", "P09" ] }, { "id": "12.dsps", "type": "prose", "text": [ "Dragonfly O100/O200 are PAM4 optical DSP families; CO400 is a coherent-lite 16QAM optical DSP. CU100/CU200 address PAM4 active electrical cables. CU100 is described as a 4 nm retimer. The 100G/200G/400G labels identify signaling/product classes, not a fully specified NIC port count. Investor Day distinguishes volume-production 800G connectivity, 1.6T scaling in the 2026-2027 period and later 3.2T development. A 448G SerDes roadmap is likewise a technology direction, not evidence of a shipping 448G-per-lane rack.", "Dragonfly O100／O200 属于 PAM4 光 DSP 家族，CO400 是 coherent-lite 16QAM 光 DSP，CU100／CU200 面向 PAM4 有源电缆。CU100 被描述为 4 nm 重定时器。100G／200G／400G 标签表示信号或产品等级，并不是完整 NIC 端口数规格。Investor Day 区分已量产的 800G 连接、2026—2027 年扩展的 1.6T，以及后续开发中的 3.2T。448G SerDes 路线同样是技术方向，不能证明已有每通道 448G 的商用机架。" ], "sources": [ "P09", "P10", "P08" ] }, { "id": "network", "type": "table", "table": "network" } ] }, { "id": "13", "title": [ "Interconnect and system topology", "互联与系统拓扑" ], "blocks": [ { "id": "interconnect", "type": "table", "table": "interconnect" }, { "id": "systems", "type": "table", "table": "systems" }, { "id": "13.networkboundary", "type": "prose", "text": [ "The rack references include NICs and switches, but the reviewed product pages do not specify a complete Qualcomm-branded AI NIC with transport, congestion-control and offload details. It is therefore more accurate to show RoCE as the system transport and the DSPs as connectivity components. Retiming a signal does not implement RDMA, congestion control or collective acceleration. Similarly, UALink participation and controller IP do not by themselves establish a merchant scale-up switch SKU.", "机架参考方案包含 NIC 与交换机，但已审阅产品页没有定义具有完整传输、拥塞控制和卸载细节的 Qualcomm 品牌 AI NIC。因此，应将 RoCE 标为系统传输，将 DSP 标为连接组件。信号重定时并不实现 RDMA、拥塞控制或集合通信加速；同样，参与 UALink 或拥有控制器 IP，也不能单独证明存在商用纵向扩展交换机 SKU。" ], "sources": [ "P04", "P05", "P08", "P09" ] } ] }, { "id": "14", "title": [ "Adreno, Hexagon, Dragonwing and RAN", "Adreno、Hexagon、Dragonwing 与 RAN" ], "blocks": [ { "id": "14.edge", "type": "prose", "text": [ "Qualcomm’s GPU line is Adreno, integrated into Snapdragon and related SoCs. Its role includes graphics and flexible local compute; it is not the architecture identity of Cloud AI 100. Hexagon combines DSP/vector/tensor capabilities for edge AI, with newer products emphasizing dedicated NPU execution. Snapdragon X and mobile Oryon products show CPU, GPU and NPU sharing a constrained memory and thermal envelope. Peak values across these engines cannot simply be added as one usable model throughput because operators, formats and data movement differ.", "Qualcomm 的 GPU 产品线是集成在 Snapdragon 等 SoC 中的 Adreno，承担图形和灵活的本地计算；它不是 Cloud AI 100 的架构名称。Hexagon 将 DSP、向量和张量能力用于边缘 AI，新产品更强调专用 NPU 执行。Snapdragon X 和移动 Oryon 产品体现 CPU、GPU、NPU 共享受限内存与散热范围。由于算子、格式和数据移动不同，不能简单将不同引擎峰值相加为模型可用吞吐。" ], "sources": [ "P12", "P14", "R04" ] }, { "id": "14.dragonwing", "type": "prose", "text": [ "Dragonwing is the industrial/embedded and infrastructure brand; Dragonfly is the datacenter portfolio. The Cloud AI 100 Ultra can also serve on-premises inference appliances, connecting the edge and datacenter stories without turning every embedded product into a server accelerator. X100 is especially easy to misread: Dragonwing X100 is a 5G RAN inline accelerator for Layer 1 baseband processing, whereas Cloud AI 100 is an AI inference family. MWC disclosures belong to telecom infrastructure, not evidence of an AI training fabric.", "Dragonwing 是工业／嵌入式和相关基础设施品牌，Dragonfly 是数据中心产品组合。Cloud AI 100 Ultra 也可用于本地推理设备，将边缘与数据中心路线连接起来，但不意味着所有嵌入式产品都是服务器加速器。X100 尤其容易混淆：Dragonwing X100 是处理 Layer 1 基带的 5G RAN 内联加速器，Cloud AI 100 才是 AI 推理家族。MWC 披露属于电信基础设施，不能作为 AI 训练互联的证据。" ], "sources": [ "P11", "E11", "P03" ] } ] }, { "id": "15", "title": [ "Software and academic evidence", "软件与学术证据" ], "blocks": [ { "id": "15.software", "type": "prose", "text": [ "Cloud AI SDK separates model compilation from runtime execution and exposes hardware-aware model preparation. The future Dragonfly stack adds the AI Inference Suite, infrastructure management, AIC ahead-of-time compilation, QCCL, NPU-direct and orchestration integration. Modular’s acquisition completed in July 2026, adding a software platform whose existing cross-hardware capability is distinct from future Dragonfly optimization. An acquisition announcement or a stack diagram does not establish that every operator and numerical format is production-ready on every accelerator generation.", "Cloud AI SDK 将模型编译与运行时执行分开，提供面向硬件的模型准备流程。未来 Dragonfly 软件栈增加 AI Inference Suite、基础设施管理、AIC 提前编译、QCCL、NPU-direct 和编排集成。Modular 收购于 2026 年 7 月完成；其已有跨硬件软件能力与未来 Dragonfly 优化应分别理解。收购公告或软件栈图不能证明每个算子和数值格式都已在每代加速器上生产就绪。" ], "sources": [ "P13", "P08", "E14" ] }, { "id": "15.academic", "type": "prose", "text": [ "ASPLOS 2025’s Fast On-device LLM Inference with NPUs is a useful implementation-facing study: it partitions variable-length prompts, handles quantization outliers across engines and schedules blocks according to CPU/GPU/NPU affinity. It studies how to use available hardware, not an undisclosed Dragonfly microarchitecture. ISCA 2023 shared-microexponent work and the OCP microscaling paper explain low-precision representation choices, but neither alone proves native support in Cloud AI 100 silicon. Academic sponsorship, a program-committee affiliation or a paper using a Snapdragon phone is not a product disclosure.", "ASPLOS 2025 的 Fast On-device LLM Inference with NPUs 是有价值的实现导向研究：它划分变长提示，将量化异常值分配给不同引擎，并按 CPU／GPU／NPU 适配性调度模型块。它研究如何使用现有硬件，而不是披露未公开的 Dragonfly 微架构。ISCA 2023 的共享微指数研究和 OCP 微缩放论文解释低精度表示选择，但二者本身都不能证明 Cloud AI 100 芯片原生支持相关格式。研究资助、程序委员会任职，或使用 Snapdragon 手机的论文，都不等于产品披露。" ], "sources": [ "R04", "R02", "R03" ] }, { "id": "software", "type": "table", "table": "software" } ] }, { "id": "16", "title": [ "Quantitative balance and deployment trade-offs", "定量配比与部署取舍" ], "blocks": [ { "id": "ratios", "type": "table", "table": "ratios" }, { "id": "16.ratiosmeaning", "type": "prose", "text": [ "These ratios expose the portfolio’s trade-offs. Ultra quadruples card memory capacity relative to Pro while doubling rated card power, but only doubles the host-link width; residency becomes more important. AI200 increases the unit of integration and cooling burden. AI250 attacks decode movement with a different memory-compute organization. Dense BF16/FP8 bytes-per-FLOP, HBM ratios, scale-out bandwidth per card and measured rack tokens/W remain n/d where the required normalized inputs are absent. Substituting marketing multipliers would hide the architectural question rather than answer it.", "这些比例揭示产品取舍：相对 Pro，Ultra 将整卡内存容量增至四倍，额定功耗翻倍，但主机链路宽度仅翻倍，因此数据驻留更加重要。AI200 扩大集成单位和散热负担；AI250 则用不同内存计算组织解决解码数据搬移。缺少归一化输入时，稠密 BF16／FP8 的字节／FLOP、HBM 比例、每卡横向带宽与实测机架 tokens/W 均保留 n/d。用宣传倍数替代这些指标，只会掩盖架构问题。" ], "sources": [ "P01", "P03", "P04", "P05" ] } ] }, { "id": "17", "title": [ "Conference-to-product index", "会议与产品对应索引" ], "blocks": [ { "id": "conference", "type": "table", "table": "conference" }, { "id": "17.gaps", "type": "prose", "text": [ "MICRO and HPCA were checked as architecture-research venues, but the reviewed record does not establish a primary Centriq, Cloud AI or Dragonfly product-architecture paper there. DAC and VLSI can illuminate implementation methods; OFC and Hot Interconnects are relevant to the acquired connectivity stack; Computex and company events establish product milestones. AWS re:Invent, Microsoft Ignite, Google Cloud Next and GTC require a specific partner deployment to count as evidence. The report does not turn generic ecosystem participation into a product presentation or claim exhaustive conference attendance.", "研究检查了 MICRO 和 HPCA，但已审阅记录没有确认这些会议上直接披露 Centriq、Cloud AI 或 Dragonfly 产品架构的一手论文。DAC 和 VLSI 可补充实现方法；OFC 与 Hot Interconnects 适合研究被收购的连接技术；Computex 和公司活动用于确定产品里程碑。AWS re:Invent、Microsoft Ignite、Google Cloud Next 和 GTC 必须有具体合作部署，才能作为证据。本报告不将一般生态参与写成产品演讲，也不宣称穷尽会议出席记录。" ], "sources": [ "C01", "C02", "C06", "P08", "R04" ] } ] }, { "id": "18", "title": [ "Codename and product crosswalk", "代号与产品对照" ], "blocks": [ { "id": "crosswalk", "type": "table", "table": "crosswalk" } ] }, { "id": "19", "title": [ "Integrated stack across four eras", "四个时代的整体产品栈" ], "blocks": [ { "id": "19.intro", "type": "prose", "text": [ "Connections show architectural composition. A roadmap block remains a roadmap in the system view; placing two future products in one figure does not establish a shipping platform.", "连线表示架构组成。路线图产品在系统图中仍是路线图，将两个未来产品画在一起并不表示已有商用平台。" ], "sources": [ "P08", "E10" ] }, { "id": "centriqera", "type": "figure", "figure": "centriqera" }, { "id": "aicera", "type": "figure", "figure": "aicera" }, { "id": "ultraera", "type": "figure", "figure": "ultraera" }, { "id": "dragonflyera", "type": "figure", "figure": "dragonflyera" }, { "id": "hierarchy", "type": "table", "table": "hierarchy" } ] }, { "id": "20", "title": [ "Engineering conclusions", "工程结论" ], "blocks": [ { "id": "20.conclusion", "type": "prose", "text": [ "Qualcomm’s strongest continuity is in energy-conscious programmable compute and data movement, not an uninterrupted server product cadence. Centriq contributes a real server baseline; Oryon rebuilds custom CPU capability; Cloud AI 100 provides a distinct inference engine; Ultra demonstrates capacity scaling through board-level replication. Dragonfly’s next step is harder: coordinating CPU, near-memory acceleration, high-speed connectivity, software and cooling at rack scale. Its success should be assessed with model fit, latency-constrained token throughput, communication overhead and measured system power, while keeping future production targets separate from present capabilities.", "Qualcomm 最强的连续性在于注重能耗的可编程计算和数据移动，而不是从未中断的服务器产品节奏。Centriq 提供真实服务器基线，Oryon 重建定制 CPU 能力，Cloud AI 100 提供独立推理引擎，Ultra 展示通过板级复制扩展容量。Dragonfly 的下一步更难：在机架级协调 CPU、近内存加速、高速连接、软件和散热。应以模型容纳能力、受延迟约束的 token 吞吐、通信开销和实测系统功耗评价，并将未来投产目标与当前能力分开。" ], "sources": [ "C01", "P01", "P08", "E10", "E14" ] } ] } ], "tables": { "cpu": { "id": "cpu", "title": [ "CPU and related client references", "CPU 与相关客户端参考产品" ], "headers": [ [ "Generation / reference SKU", "代际／参考 SKU" ], [ "Codename", "代号" ], [ "GA", "正式商用" ], [ "Status", "状态" ], [ "Core µarch", "核心微架构" ], [ "Cores / threads", "核心／线程" ], [ "Process per die", "各裸片工艺" ], [ "Dies / packaging", "裸片／封装" ], [ "L2 per core", "每核 L2" ], [ "L3 / domain", "L3／共享域" ], [ "Memory: channels; rate; GB/s", "内存：通道；速率；GB/s" ], [ "Sockets / links", "插槽／互联" ], [ "PCIe / CXL", "PCIe／CXL" ], [ "TDP", "TDP" ], [ "Vector / matrix ISA", "向量／矩阵 ISA" ] ], "rows": [ { "id": "centriq", "values": [ [ "Centriq 2460", "Centriq 2460" ], [ "Falkor", "Falkor" ], [ "2017-11", "2017-11" ], [ "Historical shipping", "历史已商用" ], [ "Custom Armv8", "Custom Armv8" ], [ "48 / 48", "48 / 48" ], [ "Samsung 10 nm", "Samsung 10 nm" ], [ "Monolithic; 398 mm2; 18B transistors", "单裸片；398 mm2；180 亿晶体管" ], [ "Shared by 2-core duplex; capacity n/d", "双核心 duplex 共享；容量 n/d" ], [ "60 MB", "60 MB" ], [ "DDR4; 6; 2667 MT/s; ~128 GB/s", "DDR4；6 通道；2667 MT/s；约 128 GB/s" ], [ "1S; QSB internal", "1S; QSB internal" ], [ "32 PCIe 3; CXL n/a", "32 PCIe 3; CXL n/a" ], [ "120 W", "120 W" ], [ "NEON; AArch64", "NEON; AArch64" ] ], "sources": [ "C01", "E02", "E01" ] }, { "id": "xelite", "values": [ [ "Snapdragon X Elite", "Snapdragon X Elite" ], [ "Oryon", "Oryon" ], [ "2024", "2024" ], [ "Historical shipping", "历史已商用" ], [ "Oryon 1", "Oryon 1" ], [ "12 / 12", "12 / 12" ], [ "4 nm", "4 nm" ], [ "Client SoC; 3 CPU clusters", "客户端 SoC；3 个 CPU 簇" ], [ "12 MB / 4-core cluster", "12 MB／4 核簇" ], [ "System-cache accounting differs", "系统缓存口径不同" ], [ "LPDDR5X; 135 GB/s", "LPDDR5X; 135 GB/s" ], [ "Client SoC; n/a", "客户端 SoC；n/a" ], [ "PCIe; CXL n/a", "PCIe; CXL n/a" ], [ "OEM configurable; n/d", "OEM 配置；n/d" ], [ "Arm64; NEON", "Arm64; NEON" ] ], "sources": [ "C07", "C08", "C02" ] }, { "id": "x2", "values": [ [ "Snapdragon X2 Elite Extreme", "Snapdragon X2 Elite Extreme" ], [ "X2E-96-100", "X2E-96-100" ], [ "2026 systems", "2026 systems" ], [ "Shipping / available", "已商用／可获取" ], [ "Oryon 3", "Oryon 3" ], [ "18 / 18", "18 / 18" ], [ "3 nm", "3 nm" ], [ "Client SoC; Prime + Performance", "客户端 SoC；Prime＋Performance" ], [ "n/d", "n/d" ], [ "53 MB total CPU cache; not all L3", "CPU 总缓存 53 MB；并非全为 L3" ], [ "LPDDR5X; 192-bit; 228 GB/s", "LPDDR5X; 192-bit; 228 GB/s" ], [ "Client SoC; n/a", "客户端 SoC；n/a" ], [ "PCIe; CXL n/a", "PCIe; CXL n/a" ], [ "OEM configurable; n/d", "OEM 配置；n/d" ], [ "Arm64; details n/d", "Arm64; details n/d" ] ], "sources": [ "P12", "E16" ] }, { "id": "c1000", "values": [ [ "Dragonfly C1000", "Dragonfly C1000" ], [ "n/d", "n/d" ], [ "2028 H2 target", "2028 H2 target" ], [ "Roadmap", "路线图" ], [ "Oryon server", "Oryon server" ], [ "250+ / n/d", "250+ / n/d" ], [ "n/d", "n/d" ], [ "Chiplet architecture", "芯粒架构" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "LPDDR; channel count/rate n/d", "LPDDR；通道数／速率 n/d" ], [ "n/d", "n/d" ], [ "PCIe 7; CXL; lanes n/d", "PCIe 7; CXL; lanes n/d" ], [ "n/d", "n/d" ], [ "Server ISA details n/d", "服务器 ISA 细节 n/d" ] ], "sources": [ "P07", "P08", "E10" ] } ], "panels": [ [ 0, 1, 2, 3, 4, 5 ], [ 0, 6, 7, 8, 9 ], [ 0, 10, 11, 12, 13, 14 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "accelerators": { "id": "accelerators", "title": [ "Inference accelerators in the common comparison schema", "统一比较字段中的推理加速器" ], "headers": [ [ "Product", "产品" ], [ "Architecture", "架构" ], [ "GA / milestone", "商用／里程碑" ], [ "Status", "状态" ], [ "Process", "工艺" ], [ "Dies / packaging", "裸片／封装" ], [ "Compute units", "计算单元" ], [ "Dense BF16", "稠密 BF16" ], [ "Dense FP8", "稠密 FP8" ], [ "Dense FP6 / FP4", "稠密 FP6／FP4" ], [ "FP64 vector / matrix", "FP64 向量／矩阵" ], [ "Memory: type; stacks; GB; TB/s", "内存：类型；堆栈；GB；TB/s" ], [ "LLC / SRAM", "末级缓存／SRAM" ], [ "Scale-up: links; GB/s per direction; domain", "纵向扩展：链路；单向 GB/s；域" ], [ "Host link", "主机连接" ], [ "Power / cooling", "功耗／散热" ], [ "Form factor", "形态" ] ], "rows": [ { "id": "standard", "values": [ [ "Cloud AI 100 Standard", "Cloud AI 100 Standard" ], [ "AIC", "AIC" ], [ "2021 systems", "2021 systems" ], [ "Historical shipping", "历史已商用" ], [ "7 nm", "7 nm" ], [ "1 SoC per card", "每卡 1 SoC" ], [ "SKU-enabled count n/d", "SKU 启用单元数 n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/a", "n/a" ], [ "LPDDR4X; n/a; 16; 0.137", "LPDDR4X；n/a；16；0.137" ], [ "126 MB SRAM", "126 MB SRAM" ], [ "PCIe; no dedicated scale-up link", "PCIe；无独立纵向链路" ], [ "PCIe 4 x8", "PCIe 4 x8" ], [ "75 W", "75 W" ], [ "HHHL PCIe", "半高半长 PCIe" ] ], "sources": [ "P01", "P02", "E04" ] }, { "id": "pro", "values": [ [ "Cloud AI 100 Pro", "Cloud AI 100 Pro" ], [ "AIC", "AIC" ], [ "2021 systems", "2021 systems" ], [ "Historical shipping", "历史已商用" ], [ "7 nm", "7 nm" ], [ "1 SoC per card", "每卡 1 SoC" ], [ "16 AIC nominal", "16 AIC nominal" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/a", "n/a" ], [ "LPDDR4X; n/a; 32; 0.137", "LPDDR4X; n/a; 32; 0.137" ], [ "144 MB SRAM", "144 MB SRAM" ], [ "PCIe; topology-dependent", "PCIe；依拓扑" ], [ "PCIe 4 x8", "PCIe 4 x8" ], [ "75 W", "75 W" ], [ "HHHL PCIe", "半高半长 PCIe" ] ], "sources": [ "P01", "P02", "E04" ] }, { "id": "ultra", "values": [ [ "Cloud AI 100 Ultra", "Cloud AI 100 Ultra" ], [ "4 x AIC SoC", "4 x AIC SoC" ], [ "2023-2024", "2023-2024" ], [ "Shipping / available", "已商用／可获取" ], [ "7 nm", "7 nm" ], [ "4 SoCs + PCIe switch", "4 SoC＋PCIe 交换机" ], [ "4 x 16 AIC nominal", "标称 4×16 AIC" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/a", "n/a" ], [ "LPDDR4X; n/a; 128; 0.548", "LPDDR4X; n/a; 128; 0.548" ], [ "576 MB SRAM", "576 MB SRAM" ], [ "On-card PCIe switching", "板载 PCIe 交换" ], [ "PCIe 4 x16", "PCIe 4 x16" ], [ "150 W", "150 W" ], [ "FH 3/4 length PCIe", "全高、3/4 长 PCIe" ] ], "sources": [ "P01", "P03", "E05" ] }, { "id": "ai200", "values": [ [ "Dragonfly AI200", "Dragonfly AI200" ], [ "Inference ASIC", "Inference ASIC" ], [ "GA n/d", "GA n/d" ], [ "Sampling / demonstrated", "送样／已演示" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "LPDDR5X; n/a; 768/card; ~7.39 derived", "LPDDR5X；n/a；每卡 768；推导约 7.39" ], [ "n/d", "n/d" ], [ "PCIe 6; link count/BW n/d", "PCIe 6；链路数／带宽 n/d" ], [ "PCIe; details n/d", "PCIe; details n/d" ], [ "Card n/d; rack 140 kW", "整卡 n/d；机架 140 kW" ], [ "Card / ORv3 rack", "板卡／ORv3 机架" ] ], "sources": [ "P04", "P08", "E07" ] }, { "id": "ai250", "values": [ [ "Dragonfly AI250", "Dragonfly AI250" ], [ "HBC Gen 1", "HBC Gen 1" ], [ "2027 target", "2027 target" ], [ "Roadmap", "路线图" ], [ "n/d", "n/d" ], [ "Near-memory architecture; die count n/d", "近内存架构；裸片数 n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "HBC; n/a; 768/card; 133 effective", "HBC；n/a；每卡 768；有效带宽 133" ], [ "n/d", "n/d" ], [ "PCIe 6; link count/BW n/d", "PCIe 6；链路数／带宽 n/d" ], [ "n/d", "n/d" ], [ "Card n/d; air/DLC rack", "整卡 n/d；风冷／DLC 机架" ], [ "Card / ORv3 rack", "板卡／ORv3 机架" ] ], "sources": [ "P05", "P08", "E06" ] }, { "id": "ai300", "values": [ [ "Dragonfly AI300", "Dragonfly AI300" ], [ "HBC Gen 2", "HBC Gen 2" ], [ "FY28 roadmap", "FY28 roadmap" ], [ "Roadmap", "路线图" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "HBC; capacity n/d; 54x AI200 effective BW target", "HBC；容量 n/d；有效带宽目标为 AI200 的 54 倍" ], [ "n/d", "n/d" ], [ "UALink / ESUN roadmap; all-to-all", "UALink／ESUN 路线图；全互连" ], [ "n/d", "n/d" ], [ "n/d; liquid-cooled rack", "n/d；液冷机架" ], [ "Rack platform", "机架平台" ] ], "sources": [ "P06", "P08" ] } ], "panels": [ [ 0, 1, 2, 3, 4, 5 ], [ 0, 6, 7, 8, 9, 10 ], [ 0, 11, 12, 13 ], [ 0, 14, 15, 16 ] ], "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed" }, "publishedcompute": { "id": "publishedcompute", "title": [ "Published legacy-card compute figures", "传统板卡公开算力口径" ], "headers": [ [ "Card", "板卡" ], [ "FP16 TFLOP/s", "FP16 TFLOP/s" ], [ "INT8 TOPS", "INT8 TOPS" ], [ "Rated power", "额定功耗" ], [ "Source basis", "来源口径" ] ], "rows": [ { "id": "s", "values": [ [ "Standard", "Standard" ], [ "110", "110" ], [ "325", "325" ], [ "75 W", "75 W" ], [ "SDK 1.12 SKU table", "SDK 1.12 SKU 表" ] ], "sources": [ "P01" ] }, { "id": "p", "values": [ [ "Pro", "Pro" ], [ "125", "125" ], [ "375", "375" ], [ "75 W", "75 W" ], [ "SDK 1.12 SKU table", "SDK 1.12 SKU 表" ] ], "sources": [ "P01" ] }, { "id": "u", "values": [ [ "Ultra", "Ultra" ], [ "288 product / 290 SDK", "288 product / 290 SDK" ], [ "870", "870" ], [ "150 W", "150 W" ], [ "Small document revision/rounding difference retained", "保留文档修订／舍入小差异" ] ], "sources": [ "P01", "P03" ] } ], "panels": [ [ 0, 1, 2, 3, 4 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "network": { "id": "network", "title": [ "Network and connectivity product classes", "网络与连接产品类别" ], "headers": [ [ "Product", "产品" ], [ "GA / milestone", "商用／里程碑" ], [ "Status", "状态" ], [ "Class", "类别" ], [ "Ports × speed", "端口×速率" ], [ "SerDes", "SerDes" ], [ "Host interface", "主机接口" ], [ "Programmable engine", "可编程引擎" ], [ "Embedded CPU", "嵌入式 CPU" ], [ "On-card memory", "板载内存" ], [ "Transport / RDMA", "传输／RDMA" ], [ "Congestion control", "拥塞控制" ], [ "Key offloads", "主要卸载" ], [ "Power", "功耗" ] ], "rows": [ { "id": "o100", "values": [ [ "Dragonfly O100", "Dragonfly O100" ], [ "2026 portfolio", "2026 portfolio" ], [ "Announced; GA n/d", "已公布；GA n/d" ], [ "Optical DSP", "光 DSP" ], [ "n/a", "n/a" ], [ "100G PAM4 class", "100G PAM4 级" ], [ "n/a", "n/a" ], [ "Signal processing; packet pipeline n/a", "信号处理；报文流水线 n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "Optical link DSP", "光链路 DSP" ], [ "n/d", "n/d" ] ], "sources": [ "P09" ] }, { "id": "o200", "values": [ [ "Dragonfly O200", "Dragonfly O200" ], [ "2026 portfolio", "2026 portfolio" ], [ "Announced; GA n/d", "已公布；GA n/d" ], [ "Optical DSP", "光 DSP" ], [ "n/a", "n/a" ], [ "200G PAM4 class", "200G PAM4 级" ], [ "n/a", "n/a" ], [ "DSP", "DSP" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "Optical link DSP", "光链路 DSP" ], [ "n/d", "n/d" ] ], "sources": [ "P09" ] }, { "id": "co400", "values": [ [ "Dragonfly CO400", "Dragonfly CO400" ], [ "2026 portfolio", "2026 portfolio" ], [ "Announced; GA n/d", "已公布；GA n/d" ], [ "Coherent-lite DSP", "轻相干 DSP" ], [ "n/a", "n/a" ], [ "400G 16QAM", "400G 16QAM" ], [ "n/a", "n/a" ], [ "DSP", "DSP" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "Longer-reach optics", "更长距离光连接" ], [ "n/d", "n/d" ] ], "sources": [ "P09" ] }, { "id": "cu100", "values": [ [ "Dragonfly CU100", "Dragonfly CU100" ], [ "2026 portfolio", "2026 portfolio" ], [ "Announced; GA n/d", "已公布；GA n/d" ], [ "AEC DSP; 4 nm", "AEC DSP；4 nm" ], [ "n/a", "n/a" ], [ "100G PAM4", "100G PAM4" ], [ "n/a", "n/a" ], [ "DSP", "DSP" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "Electrical retiming", "电信号重定时" ], [ "n/d", "n/d" ] ], "sources": [ "P10", "P09" ] }, { "id": "cu200", "values": [ [ "Dragonfly CU200", "Dragonfly CU200" ], [ "2026 portfolio", "2026 portfolio" ], [ "Announced; GA n/d", "已公布；GA n/d" ], [ "AEC DSP", "AEC DSP" ], [ "n/a", "n/a" ], [ "200G PAM4", "200G PAM4" ], [ "n/a", "n/a" ], [ "DSP", "DSP" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "Electrical retiming", "电信号重定时" ], [ "n/d", "n/d" ] ], "sources": [ "P09" ] }, { "id": "x100", "values": [ [ "Dragonwing X100", "Dragonwing X100" ], [ "2021 disclosure", "2021 disclosure" ], [ "Shipping / available", "已商用／可获取" ], [ "5G RAN inline accelerator", "5G RAN 内联加速器" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "PCIe", "PCIe" ], [ "5G L1 software", "5G L1 软件" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "O-RAN fronthaul; AI RDMA n/a", "O-RAN 前传；AI RDMA n/a" ], [ "n/a", "n/a" ], [ "Baseband L1 processing", "基带 L1 处理" ], [ "n/d", "n/d" ] ], "sources": [ "P11", "E11" ] } ], "panels": [ [ 0, 1, 2, 3, 4, 5 ], [ 0, 6, 7, 8, 9 ], [ 0, 10, 11, 12, 13 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "interconnect": { "id": "interconnect", "title": [ "Normalized interconnect boundaries", "归一化互联边界" ], "headers": [ [ "Interconnect", "互联" ], [ "Year / generation", "年份／代际" ], [ "Lane rate", "通道速率" ], [ "Lanes / link", "每链路通道" ], [ "GB/s per link per direction", "每链路单向 GB/s" ], [ "Links / device", "每设备链路" ], [ "Topology", "拓扑" ], [ "Domain limit", "域规模" ], [ "Coherence / semantics", "一致性／语义" ] ], "rows": [ { "id": "qsb", "values": [ [ "QSB", "QSB" ], [ "2017", "2017" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/d; >250 GB/s aggregate internal", "n/d；内部聚合 >250 GB/s" ], [ "n/a", "n/a" ], [ "Segmented coherent ring", "分段一致性环" ], [ "48 cores", "48 cores" ], [ "CPU/cache/I/O coherence", "CPU／缓存／I/O 一致性" ] ], "sources": [ "C01" ] }, { "id": "ai100", "values": [ [ "Cloud AI 100 host", "Cloud AI 100 host" ], [ "2021", "2021" ], [ "16 GT/s", "16 GT/s" ], [ "8", "8" ], [ "~15.75", "~15.75" ], [ "1", "1" ], [ "PCIe", "PCIe" ], [ "1 card", "1 card" ], [ "DMA / host I/O", "DMA／主机 I/O" ] ], "sources": [ "P01" ] }, { "id": "ultra", "values": [ [ "Ultra host / local", "Ultra host / local" ], [ "2023", "2023" ], [ "16 GT/s", "16 GT/s" ], [ "16 host; 8/SoC", "16 host; 8/SoC" ], [ "~31.5 host; ~15.75/SoC", "~31.5 host; ~15.75/SoC" ], [ "4 SoC links", "4 SoC links" ], [ "On-card PCIe switch", "板载 PCIe 交换机" ], [ "4 SoCs", "4 SoCs" ], [ "Partitioned local memory; PCIe movement", "分区本地内存；PCIe 搬移" ] ], "sources": [ "P01" ] }, { "id": "ai200", "values": [ [ "AI200 / AI250 scale-up", "AI200 / AI250 scale-up" ], [ "2026-2027", "2026-2027" ], [ "64 GT/s", "64 GT/s" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "PCIe 6", "PCIe 6" ], [ "Rack solution; topology n/d", "机架方案；拓扑 n/d" ], [ "Coherence not established", "未确认缓存一致性" ] ], "sources": [ "P04", "P05" ] }, { "id": "ai300", "values": [ [ "AI300 UALink / ESUN", "AI300 UALink / ESUN" ], [ "FY28", "FY28" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "Single-hop all-to-all target", "单跳全互连目标" ], [ "n/d", "n/d" ], [ "Protocol details n/d", "协议细节 n/d" ] ], "sources": [ "P06", "P08" ] } ], "panels": [ [ 0, 1, 2, 3, 4 ], [ 0, 5, 6, 7, 8 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "systems": { "id": "systems", "title": [ "System reference envelopes", "系统参考范围" ], "headers": [ [ "Platform", "平台" ], [ "Year / milestone", "年份／里程碑" ], [ "CPU / accelerator count", "CPU／加速器数量" ], [ "Scale-up domain", "纵向扩展域" ], [ "Scale-out per accelerator", "每加速器横向带宽" ], [ "Rack power", "机架功耗" ], [ "Cooling", "散热" ] ], "rows": [ { "id": "centriq", "values": [ [ "Centriq OCP motherboard", "Centriq OCP 主板" ], [ "2017", "2017" ], [ "Centriq 2400", "Centriq 2400" ], [ "1 socket", "1 socket" ], [ "n/a", "n/a" ], [ "n/d", "n/d" ], [ "Server-dependent", "依服务器" ] ], "sources": [ "E12" ] }, { "id": "ultra", "values": [ [ "Ultra inference server", "Ultra 推理服务器" ], [ "2023-2025", "2023-2025" ], [ "Host CPU + PCIe cards", "主机 CPU＋PCIe 卡" ], [ "4 SoCs per card; system-dependent", "每卡 4 SoC；依系统" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "Air, platform-dependent", "风冷；依平台" ] ], "sources": [ "P01", "R01" ] }, { "id": "ai200", "values": [ [ "AI200 ORv3", "AI200 ORv3" ], [ "2026", "2026" ], [ "56 cards", "56 cards" ], [ "PCIe 6 rack integration", "PCIe 6 机架集成" ], [ "RoCE; per-card rate n/d", "RoCE；每卡速率 n/d" ], [ "140 kW", "140 kW" ], [ "DLC reference; air option disclosed", "DLC 参考；另披露风冷选项" ] ], "sources": [ "P04" ] }, { "id": "ai250", "values": [ [ "AI250 ORv3", "AI250 ORv3" ], [ "2027 target", "2027 target" ], [ "43 TB rack; card count n/d here", "43 TB 机架；此处卡数 n/d" ], [ "PCIe 6", "PCIe 6" ], [ "RoCE; rate n/d", "RoCE；速率 n/d" ], [ "n/d", "n/d" ], [ "Air / DLC", "风冷／DLC" ] ], "sources": [ "P05" ] }, { "id": "ai300", "values": [ [ "AI300 + C1000", "AI300 + C1000" ], [ "2028 roadmap", "2028 roadmap" ], [ "Future CPU + HBC accelerators", "未来 CPU＋HBC 加速器" ], [ "All-to-all target", "全互连目标" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "Liquid", "液冷" ] ], "sources": [ "P06", "P08", "E10" ] } ], "panels": [ [ 0, 1, 2, 3 ], [ 0, 4, 5, 6 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "software": { "id": "software", "title": [ "Software timeline and enablement boundary", "软件时间线与启用边界" ], "headers": [ [ "Release / component", "版本／组件" ], [ "Date", "日期" ], [ "Hardware enabled", "启用硬件" ], [ "Key features", "主要功能" ] ], "rows": [ { "id": "sdk", "values": [ [ "Cloud AI SDK", "Cloud AI SDK" ], [ "2021-2026", "2021-2026" ], [ "Cloud AI 100 / Ultra", "Cloud AI 100 / Ultra" ], [ "Compile, deploy, profile; model support is release-specific", "编译、部署、性能分析；模型支持依版本" ] ], "sources": [ "P01", "P13" ] }, { "id": "qnn", "values": [ [ "AI Engine Direct / QNN", "AI Engine Direct / QNN" ], [ "2022-2026", "2022-2026" ], [ "Snapdragon / Hexagon / Adreno", "Snapdragon / Hexagon / Adreno" ], [ "On-device heterogeneous execution", "端侧异构执行" ] ], "sources": [ "P14", "R04" ] }, { "id": "suite", "values": [ [ "AI Inference Suite / AIMS", "AI Inference Suite / AIMS" ], [ "2026 disclosure", "2026 disclosure" ], [ "Dragonfly", "Dragonfly" ], [ "Serving, fleet management, QCCL and NPU-direct roadmap", "服务、集群管理、QCCL 与 NPU-direct 路线" ] ], "sources": [ "P08" ] }, { "id": "modular", "values": [ [ "Modular acquisition", "Modular acquisition" ], [ "2026-07", "2026-07" ], [ "Cross-hardware AI software", "Cross-hardware AI software" ], [ "Completed acquisition; future hardware enablement separate", "已完成收购；未来硬件启用单独核验" ] ], "sources": [ "E14" ] } ], "panels": [ [ 0, 1, 2, 3 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "ratios": { "id": "ratios", "title": [ "Derived ratios with explicit scope", "明确统计范围的推导比例" ], "headers": [ [ "Configuration", "配置" ], [ "Derived quantity", "推导量" ], [ "Value", "数值" ], [ "Interpretation", "解释" ] ], "rows": [ { "id": "centriq", "values": [ [ "Centriq 48C", "Centriq 48C" ], [ "DRAM/core; LLC/core", "DRAM／核；LLC／核" ], [ "~2.67 GB/s; 1.25 MB", "~2.67 GB/s; 1.25 MB" ], [ "Theoretical equal share", "理论均分" ] ], "sources": [ "C01", "E02" ] }, { "id": "pro", "values": [ [ "AI 100 Pro", "AI 100 Pro" ], [ "Memory BW / FP16 peak", "内存带宽／FP16 峰值" ], [ "0.001096 byte/FLOP", "0.001096 byte/FLOP" ], [ "137 GB/s / 125 TFLOP/s; not BF16", "137 GB/s ÷ 125 TFLOP/s；非 BF16" ] ], "sources": [ "P01" ] }, { "id": "ultra", "values": [ [ "AI 100 Ultra", "AI 100 Ultra" ], [ "Memory BW / FP16 peak", "内存带宽／FP16 峰值" ], [ "0.001903 byte/FLOP", "0.001903 byte/FLOP" ], [ "548 GB/s / 288 TFLOP/s product figure", "548 GB/s ÷ 产品规格 288 TFLOP/s" ] ], "sources": [ "P03" ] }, { "id": "hostpro", "values": [ [ "AI 100 Pro", "AI 100 Pro" ], [ "Host / local memory bandwidth", "主机／本地内存带宽" ], [ "~0.115", "~0.115" ], [ "15.75 / 137; one direction; raw host link", "15.75 ÷ 137；单方向；主机原始链路" ] ], "sources": [ "P01" ] }, { "id": "hostultra", "values": [ [ "AI 100 Ultra", "AI 100 Ultra" ], [ "Host / summed local memory BW", "主机／本地内存带宽总和" ], [ "~0.0575", "~0.0575" ], [ "31.5 / 548; four memory domains", "31.5 ÷ 548；四个内存域" ] ], "sources": [ "P01" ] }, { "id": "rack", "values": [ [ "AI200", "AI200" ], [ "Memory/card; BW/card average", "每卡内存；每卡平均带宽" ], [ "768 GB; ~7.39 TB/s", "768 GB; ~7.39 TB/s" ], [ "414 TB/s / 56 cards; no card-power inference", "414 TB/s ÷ 56 卡；不推断整卡功耗" ] ], "sources": [ "P04" ] }, { "id": "powerpro", "values": [ [ "AI 100 Pro", "AI 100 Pro" ], [ "FP16 peak / rated TDP", "FP16 峰值／额定 TDP" ], [ "1.67 TFLOP/s/W", "1.67 TFLOP/s/W" ], [ "125 / 75; not measured tokens/W", "125 ÷ 75；非实测 tokens/W" ] ], "sources": [ "P01" ] }, { "id": "powerultra", "values": [ [ "AI 100 Ultra", "AI 100 Ultra" ], [ "FP16 peak / rated TDP", "FP16 峰值／额定 TDP" ], [ "1.92 TFLOP/s/W", "1.92 TFLOP/s/W" ], [ "288 / 150; not whole-system energy", "288 ÷ 150；非整机能耗" ] ], "sources": [ "P03" ] } ], "panels": [ [ 0, 1, 2, 3 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "conference": { "id": "conference", "title": [ "Verified disclosure anchors", "已核验披露依据" ], "headers": [ [ "Venue", "会议／活动" ], [ "Year", "年份" ], [ "Paper / talk / disclosure", "论文／演讲／披露" ], [ "Presenter / authors", "报告人／作者" ], [ "Product", "产品" ], [ "Evidence type", "证据类型" ], [ "Source", "来源" ] ], "rows": [ { "id": "falkor", "values": [ [ "Hot Chips", "Hot Chips" ], [ "2017", "2017" ], [ "Qualcomm Centriq 2400 Processor / Falkor", "Qualcomm Centriq 2400 Processor / Falkor" ], [ "Qualcomm", "Qualcomm" ], [ "Centriq", "Centriq" ], [ "Architecture", "架构" ], [ "C01 E01", "C01 E01" ] ], "sources": [ "C01", "E01" ] }, { "id": "cloud", "values": [ [ "Hot Chips", "Hot Chips" ], [ "2021", "2021" ], [ "Cloud AI 100: Scalable, High Performance and Low Latency Deep Learning Inference Accelerator", "Cloud AI 100: Scalable, High Performance and Low Latency Deep Learning Inference Accelerator" ], [ "Qualcomm", "Qualcomm" ], [ "Cloud AI 100", "Cloud AI 100" ], [ "Architecture", "架构" ], [ "C06 P01", "C06 P01" ] ], "sources": [ "C06", "P01" ] }, { "id": "oryon", "values": [ [ "Hot Chips / IEEE Micro", "Hot Chips / IEEE Micro" ], [ "2024 / 2025", "2024 / 2025" ], [ "Snapdragon X Elite Qualcomm Oryon CPU: Design & Architecture Overview", "Snapdragon X Elite Qualcomm Oryon CPU: Design & Architecture Overview" ], [ "Gerard Williams / Qualcomm", "Gerard Williams / Qualcomm" ], [ "Oryon", "Oryon" ], [ "Architecture", "架构" ], [ "C07 C08 C02", "C07 C08 C02" ] ], "sources": [ "C07", "C08", "C02" ] }, { "id": "acd", "values": [ [ "ISSCC / JSSC lineage", "ISSCC / JSSC lineage" ], [ "2015 / 2016", "2015 / 2016" ], [ "Auto-calibrating adaptive clock distribution", "Auto-calibrating adaptive clock distribution" ], [ "Keith Bowman et al.", "Keith Bowman et al." ], [ "Circuit research; Snapdragon 820 link", "Circuit research; Snapdragon 820 link" ], [ "Circuit research", "电路研究" ], [ "C04", "C04" ] ], "sources": [ "C04" ] }, { "id": "isscc", "values": [ [ "ISSCC", "ISSCC" ], [ "2025", "2025" ], [ "Generative AI on Edge Devices: Models, Hardware and Systems", "Generative AI on Edge Devices: Models, Hardware and Systems" ], [ "Paul Whatmough", "Paul Whatmough" ], [ "Edge AI context", "Edge AI context" ], [ "Tutorial", "教程" ], [ "C03", "C03" ] ], "sources": [ "C03" ] }, { "id": "asplos", "values": [ [ "ASPLOS", "ASPLOS" ], [ "2025", "2025" ], [ "Fast On-device LLM Inference with NPUs", "Fast On-device LLM Inference with NPUs" ], [ "Daliang Xu et al.", "Daliang Xu et al." ], [ "Snapdragon-class NPU use", "Snapdragon-class NPU use" ], [ "System research", "系统研究" ], [ "R04", "R04" ] ], "sources": [ "R04" ] }, { "id": "isca", "values": [ [ "ISCA", "ISCA" ], [ "2023", "2023" ], [ "With Shared Microexponents, A Little Shifting Goes a Long Way", "With Shared Microexponents, A Little Shifting Goes a Long Way" ], [ "B. Rouhani et al.", "B. Rouhani et al." ], [ "Numerical-format background", "Numerical-format background" ], [ "Related research", "相关研究" ], [ "R02", "R02" ] ], "sources": [ "R02" ] }, { "id": "ocp", "values": [ [ "OCP Summit", "OCP Summit" ], [ "2017", "2017" ], [ "Centriq Open Compute motherboard with Microsoft", "Centriq Open Compute motherboard with Microsoft" ], [ "Qualcomm / Microsoft", "Qualcomm / Microsoft" ], [ "Centriq", "Centriq" ], [ "System demonstration", "系统演示" ], [ "E12", "E12" ] ], "sources": [ "E12" ] }, { "id": "mwc", "values": [ [ "MWC-era announcement", "MWC-era announcement" ], [ "2021", "2021" ], [ "5G DU X100 accelerator", "5G DU X100 accelerator" ], [ "Qualcomm", "Qualcomm" ], [ "X100 RAN", "X100 RAN" ], [ "Product / system", "产品／系统" ], [ "E11", "E11" ] ], "sources": [ "E11" ] }, { "id": "summit", "values": [ [ "Snapdragon Summit", "Snapdragon Summit" ], [ "2023 / 2025", "2023 / 2025" ], [ "X Elite / X2 Elite", "X Elite / X2 Elite" ], [ "Qualcomm", "Qualcomm" ], [ "Oryon client lineage", "Oryon client lineage" ], [ "Product launch", "产品发布" ], [ "E17 P12", "E17 P12" ] ], "sources": [ "E17", "P12" ] }, { "id": "investor", "values": [ [ "Investor Day", "Investor Day" ], [ "2026", "2026" ], [ "Dragonfly CPU, HBC, accelerators and connectivity", "Dragonfly CPU, HBC, accelerators and connectivity" ], [ "Tony Pialis", "Tony Pialis" ], [ "C1000 / AI200-300 / DSPs", "C1000 / AI200-300 / DSPs" ], [ "Roadmap / system", "路线图／系统" ], [ "P08 E09 E10", "P08 E09 E10" ] ], "sources": [ "P08", "E09", "E10" ] }, { "id": "infra", "values": [ [ "AI Infra Summit", "AI Infra Summit" ], [ "2026", "2026" ], [ "Dragonfly inference demonstrations", "Dragonfly inference demonstrations" ], [ "Qualcomm", "Qualcomm" ], [ "AI200", "AI200" ], [ "Demonstration", "演示" ], [ "E07", "E07" ] ], "sources": [ "E07" ] } ], "panels": [ [ 0, 1, 2, 3 ], [ 0, 4, 5, 6 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "crosswalk": { "id": "crosswalk", "title": [ "Disambiguation map", "名称辨析" ], "headers": [ [ "Name", "名称" ], [ "Product identity", "产品身份" ], [ "Boundary", "边界" ] ], "rows": [ { "id": "falkor", "values": [ [ "Falkor", "Falkor" ], [ "Custom CPU core in Centriq 2400", "Centriq 2400 的定制 CPU 核心" ], [ "Not Neoverse; not Oryon", "不是 Neoverse，也不是 Oryon" ] ], "sources": [ "C01" ] }, { "id": "oryon", "values": [ [ "Oryon", "Oryon" ], [ "Custom CPU family; client and future server", "定制 CPU 家族；客户端与未来服务器" ], [ "Client SoC != C1000", "客户端 SoC 不等于 C1000" ] ], "sources": [ "C07", "P07" ] }, { "id": "cloud", "values": [ [ "Cloud AI 100 / Ultra", "Cloud AI 100 / Ultra" ], [ "Inference ASIC and PCIe cards", "推理 ASIC 与 PCIe 卡" ], [ "Not Adreno GPU; not X100 RAN", "不是 Adreno GPU，也不是 X100 RAN" ] ], "sources": [ "P01", "P11" ] }, { "id": "fly", "values": [ [ "Dragonfly", "Dragonfly" ], [ "Datacenter CPU, accelerator and connectivity brand", "数据中心 CPU、加速器与连接品牌" ], [ "C1000 / AI200 / AI250 / AI300 / DSPs", "C1000／AI200／AI250／AI300／DSP" ] ], "sources": [ "P08", "P09" ] }, { "id": "wing", "values": [ [ "Dragonwing X100", "Dragonwing X100" ], [ "5G baseband inline accelerator", "5G 基带内联加速器" ], [ "Telecom L1 offload", "电信 L1 卸载" ] ], "sources": [ "P11" ] }, { "id": "hbc", "values": [ [ "HBC", "HBC" ], [ "High Bandwidth Compute", "高带宽计算" ], [ "Near-memory compute; not HBM synonym", "近内存计算；不是 HBM 同义词" ] ], "sources": [ "P08" ] } ], "panels": [ [ 0, 1, 2 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "hierarchy": { "id": "hierarchy", "title": [ "Bandwidth hierarchy by era", "各时代带宽层次" ], "headers": [ [ "Era / reference", "时代／参考" ], [ "On-die / die-to-die", "片上／裸片间" ], [ "Local memory", "本地内存" ], [ "CPU / scale-up", "CPU／纵向扩展" ], [ "Scale-out", "横向扩展" ] ], "rows": [ { "id": "centriq", "values": [ [ "2017 Centriq", "2017 Centriq" ], [ "QSB >250 GB/s aggregate", "QSB 聚合 >250 GB/s" ], [ "~128 GB/s DDR4", "~128 GB/s DDR4" ], [ "PCIe 3; ~15.75 GB/s per x16 direction", "PCIe 3; ~15.75 GB/s per x16 direction" ], [ "External NIC; n/d", "外部 NIC；n/d" ] ], "sources": [ "C01" ] }, { "id": "pro", "values": [ [ "2021 AI 100 Pro", "2021 AI 100 Pro" ], [ "3 NoCs; aggregate scope not normalized", "3 类 NoC；聚合口径不归一化" ], [ "137 GB/s", "137 GB/s" ], [ "PCIe 4 x8 ~15.75 GB/s/direction", "PCIe 4 x8 ~15.75 GB/s/direction" ], [ "External NIC; n/d", "外部 NIC；n/d" ] ], "sources": [ "P01" ] }, { "id": "ultra", "values": [ [ "2023 Ultra", "2023 Ultra" ], [ "4 discrete SoCs; PCIe switch", "4 颗独立 SoC；PCIe 交换机" ], [ "548 GB/s summed", "548 GB/s summed" ], [ "PCIe 4 x16 ~31.5 GB/s/direction", "PCIe 4 x16 ~31.5 GB/s/direction" ], [ "External NIC; n/d", "外部 NIC；n/d" ] ], "sources": [ "P01" ] }, { "id": "future", "values": [ [ "2026 Dragonfly disclosure", "2026 Dragonfly disclosure" ], [ "HBC implementation details n/d", "HBC 实现细节 n/d" ], [ "AI200 ~7.39 TB/s/card; AI250 133 effective", "AI200 每卡约 7.39 TB/s；AI250 有效带宽 133" ], [ "PCIe 6 / future UALink; n/d", "PCIe 6 / future UALink; n/d" ], [ "RoCE; per-card bandwidth n/d", "RoCE；每卡带宽 n/d" ] ], "sources": [ "P04", "P05", "P06" ] } ], "panels": [ [ 0, 1, 2, 3, 4 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" } }, "figures": { "centriqera": { "id": "centriqera", "title": [ "2015-2018: the scale-out server attempt", "2015—2018：横向扩展服务器尝试" ], "nodes": [ [ "n0", [ "Falkor duplexes", "Falkor 双核模块" ], 0, 0 ], [ "n1", [ "DDR4 + QSB", "DDR4＋QSB" ], 1, 0 ], [ "n2", [ "Centriq 2400", "Centriq 2400" ], 0, 1 ], [ "n3", [ "PCIe NIC / storage", "PCIe NIC／存储" ], 1, 1 ], [ "n4", [ "Linux / server firmware", "Linux／服务器固件" ], 0, 2 ], [ "n5", [ "OCP / cloud evaluation", "OCP／云评估" ], 1, 2 ] ], "edges": [ [ "n0", "n2", [ "compute", "计算" ] ], [ "n1", "n3", [ "data path", "数据路径" ] ], [ "n2", "n4", [ "enable", "启用" ] ], [ "n3", "n5", [ "integrate", "集成" ] ], [ "n4", "n5", [ "software", "软件" ] ] ], "caption": [ "Conceptual composition, with statuses defined in the product chapters; external NIC ownership is not inferred.", "概念性组成图，状态以产品章节为准；不推断外部 NIC 的设计归属。" ] }, "aicera": { "id": "aicera", "title": [ "2019-2022: inference cards", "2019—2022：推理加速卡" ], "nodes": [ [ "n0", [ "Cloud AI 100 AIC", "Cloud AI 100 AIC" ], 0, 0 ], [ "n1", [ "SRAM + LPDDR4X", "SRAM＋LPDDR4X" ], 1, 0 ], [ "n2", [ "PCIe card + host CPU", "PCIe 卡＋主机 CPU" ], 0, 1 ], [ "n3", [ "External Ethernet", "外部以太网" ], 1, 1 ], [ "n4", [ "Cloud AI SDK", "Cloud AI SDK" ], 0, 2 ], [ "n5", [ "Inference server / edge", "推理服务器／边缘" ], 1, 2 ] ], "edges": [ [ "n0", "n2", [ "compute", "计算" ] ], [ "n1", "n3", [ "data path", "数据路径" ] ], [ "n2", "n4", [ "enable", "启用" ] ], [ "n3", "n5", [ "integrate", "集成" ] ], [ "n4", "n5", [ "software", "软件" ] ] ], "caption": [ "Conceptual composition, with statuses defined in the product chapters; external NIC ownership is not inferred.", "概念性组成图，状态以产品章节为准；不推断外部 NIC 的设计归属。" ] }, "ultraera": { "id": "ultraera", "title": [ "2023-2025: model capacity and new CPU cores", "2023—2025：模型容量与新 CPU 核心" ], "nodes": [ [ "n0", [ "4 x AI 100 SoCs", "4×AI 100 SoC" ], 0, 0 ], [ "n1", [ "128 GB card memory", "128 GB 整卡内存" ], 1, 0 ], [ "n2", [ "Ultra + PCIe host", "Ultra＋PCIe 主机" ], 0, 1 ], [ "n3", [ "Oryon client lineage", "Oryon 客户端谱系" ], 1, 1 ], [ "n4", [ "SDK + model partitioning", "SDK＋模型切分" ], 0, 2 ], [ "n5", [ "LLM serving / on-prem", "LLM 服务／本地部署" ], 1, 2 ] ], "edges": [ [ "n0", "n2", [ "compute", "计算" ] ], [ "n1", "n3", [ "data path", "数据路径" ] ], [ "n2", "n4", [ "enable", "启用" ] ], [ "n3", "n5", [ "integrate", "集成" ] ], [ "n4", "n5", [ "software", "软件" ] ] ], "caption": [ "Conceptual composition, with statuses defined in the product chapters; external NIC ownership is not inferred.", "概念性组成图，状态以产品章节为准；不推断外部 NIC 的设计归属。" ] }, "dragonflyera": { "id": "dragonflyera", "title": [ "2026 disclosures: the future rack portfolio", "2026 年披露：未来机架产品组合" ], "nodes": [ [ "n0", [ "C1000 roadmap CPU", "C1000 路线图 CPU" ], 0, 0 ], [ "n1", [ "AI200 / AI250 / AI300", "AI200／AI250／AI300" ], 1, 0 ], [ "n2", [ "PCIe / UALink roadmap", "PCIe／UALink 路线" ], 0, 1 ], [ "n3", [ "RoCE + DSP connectivity", "RoCE＋DSP 连接" ], 1, 1 ], [ "n4", [ "Inference Suite / Modular", "Inference Suite／Modular" ], 0, 2 ], [ "n5", [ "ORv3 inference racks", "ORv3 推理机架" ], 1, 2 ] ], "edges": [ [ "n0", "n2", [ "compute", "计算" ] ], [ "n1", "n3", [ "data path", "数据路径" ] ], [ "n2", "n4", [ "enable", "启用" ] ], [ "n3", "n5", [ "integrate", "集成" ] ], [ "n4", "n5", [ "software", "软件" ] ] ], "caption": [ "Conceptual composition, with statuses defined in the product chapters; external NIC ownership is not inferred.", "概念性组成图，状态以产品章节为准；不推断外部 NIC 的设计归属。" ] } }, "claims": { "cpu.centriq.0": { "value": "Centriq 2460", "field": "Generation / reference SKU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "E02", "E01" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "centriq" }, "cpu.centriq.1": { "value": "Falkor", "field": "Codename", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "E02", "E01" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "centriq" }, "cpu.centriq.2": { "value": "2017-11", "field": "GA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "E02", "E01" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "centriq" }, "cpu.centriq.3": { "value": "Historical shipping", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "E02", "E01" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "centriq" }, "cpu.centriq.4": { "value": "Custom Armv8", "field": "Core µarch", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "E02", "E01" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "centriq" }, "cpu.centriq.5": { "value": "48 / 48", "field": "Cores / threads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "E02", "E01" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "centriq" }, "cpu.centriq.6": { "value": "Samsung 10 nm", "field": "Process per die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "E02", "E01" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "centriq" }, "cpu.centriq.7": { "value": "Monolithic; 398 mm2; 18B transistors", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "E02", "E01" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "centriq" }, "cpu.centriq.8": { "value": "Shared by 2-core duplex; capacity n/d", "field": "L2 per core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "E02", "E01" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "centriq" }, "cpu.centriq.9": { "value": "60 MB", "field": "L3 / domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "E02", "E01" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "centriq" }, "cpu.centriq.10": { "value": "DDR4; 6; 2667 MT/s; ~128 GB/s", "field": "Memory: channels; rate; GB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "E02", "E01" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "centriq" }, "cpu.centriq.11": { "value": "1S; QSB internal", "field": "Sockets / links", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "E02", "E01" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "centriq" }, "cpu.centriq.12": { "value": "32 PCIe 3; CXL n/a", "field": "PCIe / CXL", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "E02", "E01" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "centriq" }, "cpu.centriq.13": { "value": "120 W", "field": "TDP", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "E02", "E01" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "centriq" }, "cpu.centriq.14": { "value": "NEON; AArch64", "field": "Vector / matrix ISA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "E02", "E01" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "centriq" }, "cpu.xelite.0": { "value": "Snapdragon X Elite", "field": "Generation / reference SKU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C07", "C08", "C02" ], "disclosure_date": "2024", "status": "historical shipping", "scope": "xelite" }, "cpu.xelite.1": { "value": "Oryon", "field": "Codename", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C07", "C08", "C02" ], "disclosure_date": "2024", "status": "historical shipping", "scope": "xelite" }, "cpu.xelite.2": { "value": "2024", "field": "GA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C07", "C08", "C02" ], "disclosure_date": "2024", "status": "historical shipping", "scope": "xelite" }, "cpu.xelite.3": { "value": "Historical shipping", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C07", "C08", "C02" ], "disclosure_date": "2024", "status": "historical shipping", "scope": "xelite" }, "cpu.xelite.4": { "value": "Oryon 1", "field": "Core µarch", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C07", "C08", "C02" ], "disclosure_date": "2024", "status": "historical shipping", "scope": "xelite" }, "cpu.xelite.5": { "value": "12 / 12", "field": "Cores / threads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C07", "C08", "C02" ], "disclosure_date": "2024", "status": "historical shipping", "scope": "xelite" }, "cpu.xelite.6": { "value": "4 nm", "field": "Process per die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C07", "C08", "C02" ], "disclosure_date": "2024", "status": "historical shipping", "scope": "xelite" }, "cpu.xelite.7": { "value": "Client SoC; 3 CPU clusters", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C07", "C08", "C02" ], "disclosure_date": "2024", "status": "historical shipping", "scope": "xelite" }, "cpu.xelite.8": { "value": "12 MB / 4-core cluster", "field": "L2 per core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C07", "C08", "C02" ], "disclosure_date": "2024", "status": "historical shipping", "scope": "xelite" }, "cpu.xelite.9": { "value": "System-cache accounting differs", "field": "L3 / domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C07", "C08", "C02" ], "disclosure_date": "2024", "status": "historical shipping", "scope": "xelite" }, "cpu.xelite.10": { "value": "LPDDR5X; 135 GB/s", "field": "Memory: channels; rate; GB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C07", "C08", "C02" ], "disclosure_date": "2024", "status": "historical shipping", "scope": "xelite" }, "cpu.xelite.11": { "value": "Client SoC; n/a", "field": "Sockets / links", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C07", "C08", "C02" ], "disclosure_date": "2024", "status": "historical shipping", "scope": "xelite" }, "cpu.xelite.12": { "value": "PCIe; CXL n/a", "field": "PCIe / CXL", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C07", "C08", "C02" ], "disclosure_date": "2024", "status": "historical shipping", "scope": "xelite" }, "cpu.xelite.13": { "value": "OEM configurable; n/d", "field": "TDP", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C07", "C08", "C02" ], "disclosure_date": "2024", "status": "historical shipping", "scope": "xelite" }, "cpu.xelite.14": { "value": "Arm64; NEON", "field": "Vector / matrix ISA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C07", "C08", "C02" ], "disclosure_date": "2024", "status": "historical shipping", "scope": "xelite" }, "cpu.x2.0": { "value": "Snapdragon X2 Elite Extreme", "field": "Generation / reference SKU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P12", "E16" ], "disclosure_date": "2025-2026", "status": "shipping client", "scope": "x2" }, "cpu.x2.1": { "value": "X2E-96-100", "field": "Codename", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P12", "E16" ], "disclosure_date": "2025-2026", "status": "shipping client", "scope": "x2" }, "cpu.x2.2": { "value": "2026 systems", "field": "GA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P12", "E16" ], "disclosure_date": "2025-2026", "status": "shipping client", "scope": "x2" }, "cpu.x2.3": { "value": "Shipping / available", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P12", "E16" ], "disclosure_date": "2025-2026", "status": "shipping client", "scope": "x2" }, "cpu.x2.4": { "value": "Oryon 3", "field": "Core µarch", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P12", "E16" ], "disclosure_date": "2025-2026", "status": "shipping client", "scope": "x2" }, "cpu.x2.5": { "value": "18 / 18", "field": "Cores / threads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P12", "E16" ], "disclosure_date": "2025-2026", "status": "shipping client", "scope": "x2" }, "cpu.x2.6": { "value": "3 nm", "field": "Process per die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P12", "E16" ], "disclosure_date": "2025-2026", "status": "shipping client", "scope": "x2" }, "cpu.x2.7": { "value": "Client SoC; Prime + Performance", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P12", "E16" ], "disclosure_date": "2025-2026", "status": "shipping client", "scope": "x2" }, "cpu.x2.8": { "value": "n/d", "field": "L2 per core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P12", "E16" ], "disclosure_date": "2025-2026", "status": "shipping client", "scope": "x2" }, "cpu.x2.9": { "value": "53 MB total CPU cache; not all L3", "field": "L3 / domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P12", "E16" ], "disclosure_date": "2025-2026", "status": "shipping client", "scope": "x2" }, "cpu.x2.10": { "value": "LPDDR5X; 192-bit; 228 GB/s", "field": "Memory: channels; rate; GB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P12", "E16" ], "disclosure_date": "2025-2026", "status": "shipping client", "scope": "x2" }, "cpu.x2.11": { "value": "Client SoC; n/a", "field": "Sockets / links", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P12", "E16" ], "disclosure_date": "2025-2026", "status": "shipping client", "scope": "x2" }, "cpu.x2.12": { "value": "PCIe; CXL n/a", "field": "PCIe / CXL", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P12", "E16" ], "disclosure_date": "2025-2026", "status": "shipping client", "scope": "x2" }, "cpu.x2.13": { "value": "OEM configurable; n/d", "field": "TDP", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P12", "E16" ], "disclosure_date": "2025-2026", "status": "shipping client", "scope": "x2" }, "cpu.x2.14": { "value": "Arm64; details n/d", "field": "Vector / matrix ISA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P12", "E16" ], "disclosure_date": "2025-2026", "status": "shipping client", "scope": "x2" }, "cpu.c1000.0": { "value": "Dragonfly C1000", "field": "Generation / reference SKU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "P08", "E10" ], "disclosure_date": "2026-06", "status": "roadmap", "scope": "c1000" }, "cpu.c1000.1": { "value": "n/d", "field": "Codename", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "P08", "E10" ], "disclosure_date": "2026-06", "status": "roadmap", "scope": "c1000" }, "cpu.c1000.2": { "value": "2028 H2 target", "field": "GA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "P08", "E10" ], "disclosure_date": "2026-06", "status": "roadmap", "scope": "c1000" }, "cpu.c1000.3": { "value": "Roadmap", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "P08", "E10" ], "disclosure_date": "2026-06", "status": "roadmap", "scope": "c1000" }, "cpu.c1000.4": { "value": "Oryon server", "field": "Core µarch", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "P08", "E10" ], "disclosure_date": "2026-06", "status": "roadmap", "scope": "c1000" }, "cpu.c1000.5": { "value": "250+ / n/d", "field": "Cores / threads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "P08", "E10" ], "disclosure_date": "2026-06", "status": "roadmap", "scope": "c1000" }, "cpu.c1000.6": { "value": "n/d", "field": "Process per die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "P08", "E10" ], "disclosure_date": "2026-06", "status": "roadmap", "scope": "c1000" }, "cpu.c1000.7": { "value": "Chiplet architecture", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "P08", "E10" ], "disclosure_date": "2026-06", "status": "roadmap", "scope": "c1000" }, "cpu.c1000.8": { "value": "n/d", "field": "L2 per core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "P08", "E10" ], "disclosure_date": "2026-06", "status": "roadmap", "scope": "c1000" }, "cpu.c1000.9": { "value": "n/d", "field": "L3 / domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "P08", "E10" ], "disclosure_date": "2026-06", "status": "roadmap", "scope": "c1000" }, "cpu.c1000.10": { "value": "LPDDR; channel count/rate n/d", "field": "Memory: channels; rate; GB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "P08", "E10" ], "disclosure_date": "2026-06", "status": "roadmap", "scope": "c1000" }, "cpu.c1000.11": { "value": "n/d", "field": "Sockets / links", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "P08", "E10" ], "disclosure_date": "2026-06", "status": "roadmap", "scope": "c1000" }, "cpu.c1000.12": { "value": "PCIe 7; CXL; lanes n/d", "field": "PCIe / CXL", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "P08", "E10" ], "disclosure_date": "2026-06", "status": "roadmap", "scope": "c1000" }, "cpu.c1000.13": { "value": "n/d", "field": "TDP", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "P08", "E10" ], "disclosure_date": "2026-06", "status": "roadmap", "scope": "c1000" }, "cpu.c1000.14": { "value": "Server ISA details n/d", "field": "Vector / matrix ISA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "P08", "E10" ], "disclosure_date": "2026-06", "status": "roadmap", "scope": "c1000" }, "accelerators.standard.0": { "value": "Cloud AI 100 Standard", "field": "Product", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "standard" }, "accelerators.standard.1": { "value": "AIC", "field": "Architecture", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "standard" }, "accelerators.standard.2": { "value": "2021 systems", "field": "GA / milestone", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "standard" }, "accelerators.standard.3": { "value": "Historical shipping", "field": "Status", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "standard" }, "accelerators.standard.4": { "value": "7 nm", "field": "Process", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "standard" }, "accelerators.standard.5": { "value": "1 SoC per card", "field": "Dies / packaging", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "standard" }, "accelerators.standard.6": { "value": "SKU-enabled count n/d", "field": "Compute units", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "standard" }, "accelerators.standard.7": { "value": "n/d", "field": "Dense BF16", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "standard" }, "accelerators.standard.8": { "value": "n/d", "field": "Dense FP8", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "standard" }, "accelerators.standard.9": { "value": "n/d", "field": "Dense FP6 / FP4", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "standard" }, "accelerators.standard.10": { "value": "n/a", "field": "FP64 vector / matrix", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "standard" }, "accelerators.standard.11": { "value": "LPDDR4X; n/a; 16; 0.137", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "standard" }, "accelerators.standard.12": { "value": "126 MB SRAM", "field": "LLC / SRAM", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "standard" }, "accelerators.standard.13": { "value": "PCIe; no dedicated scale-up link", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "standard" }, "accelerators.standard.14": { "value": "PCIe 4 x8", "field": "Host link", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "standard" }, "accelerators.standard.15": { "value": "75 W", "field": "Power / cooling", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "standard" }, "accelerators.standard.16": { "value": "HHHL PCIe", "field": "Form factor", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "standard" }, "accelerators.pro.0": { "value": "Cloud AI 100 Pro", "field": "Product", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "pro" }, "accelerators.pro.1": { "value": "AIC", "field": "Architecture", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "pro" }, "accelerators.pro.2": { "value": "2021 systems", "field": "GA / milestone", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "pro" }, "accelerators.pro.3": { "value": "Historical shipping", "field": "Status", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "pro" }, "accelerators.pro.4": { "value": "7 nm", "field": "Process", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "pro" }, "accelerators.pro.5": { "value": "1 SoC per card", "field": "Dies / packaging", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "pro" }, "accelerators.pro.6": { "value": "16 AIC nominal", "field": "Compute units", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "pro" }, "accelerators.pro.7": { "value": "n/d", "field": "Dense BF16", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "pro" }, "accelerators.pro.8": { "value": "n/d", "field": "Dense FP8", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "pro" }, "accelerators.pro.9": { "value": "n/d", "field": "Dense FP6 / FP4", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "pro" }, "accelerators.pro.10": { "value": "n/a", "field": "FP64 vector / matrix", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "pro" }, "accelerators.pro.11": { "value": "LPDDR4X; n/a; 32; 0.137", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "pro" }, "accelerators.pro.12": { "value": "144 MB SRAM", "field": "LLC / SRAM", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "pro" }, "accelerators.pro.13": { "value": "PCIe; topology-dependent", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "pro" }, "accelerators.pro.14": { "value": "PCIe 4 x8", "field": "Host link", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "pro" }, "accelerators.pro.15": { "value": "75 W", "field": "Power / cooling", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "pro" }, "accelerators.pro.16": { "value": "HHHL PCIe", "field": "Form factor", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P02", "E04" ], "disclosure_date": "2020-2021", "status": "historical shipping", "scope": "pro" }, "accelerators.ultra.0": { "value": "Cloud AI 100 Ultra", "field": "Product", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P03", "E05" ], "disclosure_date": "2023-2024", "status": "shipping", "scope": "ultra" }, "accelerators.ultra.1": { "value": "4 x AIC SoC", "field": "Architecture", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P03", "E05" ], "disclosure_date": "2023-2024", "status": "shipping", "scope": "ultra" }, "accelerators.ultra.2": { "value": "2023-2024", "field": "GA / milestone", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P03", "E05" ], "disclosure_date": "2023-2024", "status": "shipping", "scope": "ultra" }, "accelerators.ultra.3": { "value": "Shipping / available", "field": "Status", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P03", "E05" ], "disclosure_date": "2023-2024", "status": "shipping", "scope": "ultra" }, "accelerators.ultra.4": { "value": "7 nm", "field": "Process", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P03", "E05" ], "disclosure_date": "2023-2024", "status": "shipping", "scope": "ultra" }, "accelerators.ultra.5": { "value": "4 SoCs + PCIe switch", "field": "Dies / packaging", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P03", "E05" ], "disclosure_date": "2023-2024", "status": "shipping", "scope": "ultra" }, "accelerators.ultra.6": { "value": "4 x 16 AIC nominal", "field": "Compute units", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P03", "E05" ], "disclosure_date": "2023-2024", "status": "shipping", "scope": "ultra" }, "accelerators.ultra.7": { "value": "n/d", "field": "Dense BF16", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P03", "E05" ], "disclosure_date": "2023-2024", "status": "shipping", "scope": "ultra" }, "accelerators.ultra.8": { "value": "n/d", "field": "Dense FP8", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P03", "E05" ], "disclosure_date": "2023-2024", "status": "shipping", "scope": "ultra" }, "accelerators.ultra.9": { "value": "n/d", "field": "Dense FP6 / FP4", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P03", "E05" ], "disclosure_date": "2023-2024", "status": "shipping", "scope": "ultra" }, "accelerators.ultra.10": { "value": "n/a", "field": "FP64 vector / matrix", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P03", "E05" ], "disclosure_date": "2023-2024", "status": "shipping", "scope": "ultra" }, "accelerators.ultra.11": { "value": "LPDDR4X; n/a; 128; 0.548", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P03", "E05" ], "disclosure_date": "2023-2024", "status": "shipping", "scope": "ultra" }, "accelerators.ultra.12": { "value": "576 MB SRAM", "field": "LLC / SRAM", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P03", "E05" ], "disclosure_date": "2023-2024", "status": "shipping", "scope": "ultra" }, "accelerators.ultra.13": { "value": "On-card PCIe switching", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P03", "E05" ], "disclosure_date": "2023-2024", "status": "shipping", "scope": "ultra" }, "accelerators.ultra.14": { "value": "PCIe 4 x16", "field": "Host link", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P03", "E05" ], "disclosure_date": "2023-2024", "status": "shipping", "scope": "ultra" }, "accelerators.ultra.15": { "value": "150 W", "field": "Power / cooling", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P03", "E05" ], "disclosure_date": "2023-2024", "status": "shipping", "scope": "ultra" }, "accelerators.ultra.16": { "value": "FH 3/4 length PCIe", "field": "Form factor", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P01", "P03", "E05" ], "disclosure_date": "2023-2024", "status": "shipping", "scope": "ultra" }, "accelerators.ai200.0": { "value": "Dragonfly AI200", "field": "Product", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P04", "P08", "E07" ], "disclosure_date": "2026", "status": "sampling", "scope": "ai200" }, "accelerators.ai200.1": { "value": "Inference ASIC", "field": "Architecture", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P04", "P08", "E07" ], "disclosure_date": "2026", "status": "sampling", "scope": "ai200" }, "accelerators.ai200.2": { "value": "GA n/d", "field": "GA / milestone", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P04", "P08", "E07" ], "disclosure_date": "2026", "status": "sampling", "scope": "ai200" }, "accelerators.ai200.3": { "value": "Sampling / demonstrated", "field": "Status", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P04", "P08", "E07" ], "disclosure_date": "2026", "status": "sampling", "scope": "ai200" }, "accelerators.ai200.4": { "value": "n/d", "field": "Process", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P04", "P08", "E07" ], "disclosure_date": "2026", "status": "sampling", "scope": "ai200" }, "accelerators.ai200.5": { "value": "n/d", "field": "Dies / packaging", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P04", "P08", "E07" ], "disclosure_date": "2026", "status": "sampling", "scope": "ai200" }, "accelerators.ai200.6": { "value": "n/d", "field": "Compute units", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P04", "P08", "E07" ], "disclosure_date": "2026", "status": "sampling", "scope": "ai200" }, "accelerators.ai200.7": { "value": "n/d", "field": "Dense BF16", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P04", "P08", "E07" ], "disclosure_date": "2026", "status": "sampling", "scope": "ai200" }, "accelerators.ai200.8": { "value": "n/d", "field": "Dense FP8", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P04", "P08", "E07" ], "disclosure_date": "2026", "status": "sampling", "scope": "ai200" }, "accelerators.ai200.9": { "value": "n/d", "field": "Dense FP6 / FP4", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P04", "P08", "E07" ], "disclosure_date": "2026", "status": "sampling", "scope": "ai200" }, "accelerators.ai200.10": { "value": "n/d", "field": "FP64 vector / matrix", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P04", "P08", "E07" ], "disclosure_date": "2026", "status": "sampling", "scope": "ai200" }, "accelerators.ai200.11": { "value": "LPDDR5X; n/a; 768/card; ~7.39 derived", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P04", "P08", "E07" ], "disclosure_date": "2026", "status": "sampling", "scope": "ai200" }, "accelerators.ai200.12": { "value": "n/d", "field": "LLC / SRAM", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P04", "P08", "E07" ], "disclosure_date": "2026", "status": "sampling", "scope": "ai200" }, "accelerators.ai200.13": { "value": "PCIe 6; link count/BW n/d", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P04", "P08", "E07" ], "disclosure_date": "2026", "status": "sampling", "scope": "ai200" }, "accelerators.ai200.14": { "value": "PCIe; details n/d", "field": "Host link", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P04", "P08", "E07" ], "disclosure_date": "2026", "status": "sampling", "scope": "ai200" }, "accelerators.ai200.15": { "value": "Card n/d; rack 140 kW", "field": "Power / cooling", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P04", "P08", "E07" ], "disclosure_date": "2026", "status": "sampling", "scope": "ai200" }, "accelerators.ai200.16": { "value": "Card / ORv3 rack", "field": "Form factor", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P04", "P08", "E07" ], "disclosure_date": "2026", "status": "sampling", "scope": "ai200" }, "accelerators.ai250.0": { "value": "Dragonfly AI250", "field": "Product", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P05", "P08", "E06" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai250" }, "accelerators.ai250.1": { "value": "HBC Gen 1", "field": "Architecture", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P05", "P08", "E06" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai250" }, "accelerators.ai250.2": { "value": "2027 target", "field": "GA / milestone", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P05", "P08", "E06" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai250" }, "accelerators.ai250.3": { "value": "Roadmap", "field": "Status", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P05", "P08", "E06" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai250" }, "accelerators.ai250.4": { "value": "n/d", "field": "Process", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P05", "P08", "E06" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai250" }, "accelerators.ai250.5": { "value": "Near-memory architecture; die count n/d", "field": "Dies / packaging", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P05", "P08", "E06" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai250" }, "accelerators.ai250.6": { "value": "n/d", "field": "Compute units", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P05", "P08", "E06" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai250" }, "accelerators.ai250.7": { "value": "n/d", "field": "Dense BF16", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P05", "P08", "E06" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai250" }, "accelerators.ai250.8": { "value": "n/d", "field": "Dense FP8", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P05", "P08", "E06" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai250" }, "accelerators.ai250.9": { "value": "n/d", "field": "Dense FP6 / FP4", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P05", "P08", "E06" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai250" }, "accelerators.ai250.10": { "value": "n/d", "field": "FP64 vector / matrix", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P05", "P08", "E06" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai250" }, "accelerators.ai250.11": { "value": "HBC; n/a; 768/card; 133 effective", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P05", "P08", "E06" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai250" }, "accelerators.ai250.12": { "value": "n/d", "field": "LLC / SRAM", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P05", "P08", "E06" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai250" }, "accelerators.ai250.13": { "value": "PCIe 6; link count/BW n/d", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P05", "P08", "E06" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai250" }, "accelerators.ai250.14": { "value": "n/d", "field": "Host link", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P05", "P08", "E06" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai250" }, "accelerators.ai250.15": { "value": "Card n/d; air/DLC rack", "field": "Power / cooling", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P05", "P08", "E06" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai250" }, "accelerators.ai250.16": { "value": "Card / ORv3 rack", "field": "Form factor", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P05", "P08", "E06" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai250" }, "accelerators.ai300.0": { "value": "Dragonfly AI300", "field": "Product", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P06", "P08" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "accelerators.ai300.1": { "value": "HBC Gen 2", "field": "Architecture", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P06", "P08" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "accelerators.ai300.2": { "value": "FY28 roadmap", "field": "GA / milestone", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P06", "P08" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "accelerators.ai300.3": { "value": "Roadmap", "field": "Status", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P06", "P08" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "accelerators.ai300.4": { "value": "n/d", "field": "Process", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P06", "P08" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "accelerators.ai300.5": { "value": "n/d", "field": "Dies / packaging", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P06", "P08" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "accelerators.ai300.6": { "value": "n/d", "field": "Compute units", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P06", "P08" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "accelerators.ai300.7": { "value": "n/d", "field": "Dense BF16", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P06", "P08" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "accelerators.ai300.8": { "value": "n/d", "field": "Dense FP8", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P06", "P08" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "accelerators.ai300.9": { "value": "n/d", "field": "Dense FP6 / FP4", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P06", "P08" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "accelerators.ai300.10": { "value": "n/d", "field": "FP64 vector / matrix", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P06", "P08" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "accelerators.ai300.11": { "value": "HBC; capacity n/d; 54x AI200 effective BW target", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P06", "P08" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "accelerators.ai300.12": { "value": "n/d", "field": "LLC / SRAM", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P06", "P08" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "accelerators.ai300.13": { "value": "UALink / ESUN roadmap; all-to-all", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P06", "P08" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "accelerators.ai300.14": { "value": "n/d", "field": "Host link", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P06", "P08" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "accelerators.ai300.15": { "value": "n/d; liquid-cooled rack", "field": "Power / cooling", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P06", "P08" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "accelerators.ai300.16": { "value": "Rack platform", "field": "Form factor", "basis": "Per card unless stated; memory column permits LPDDR/HBC because HBM is not used; HBC effective bandwidth is not ordinary external bus bandwidth; normalized dense formats only where disclosed", "source": [ "P06", "P08" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "publishedcompute.s.0": { "value": "Standard", "field": "Card", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2026 retrieval", "status": "shipping", "scope": "s" }, "publishedcompute.s.1": { "value": "110", "field": "FP16 TFLOP/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2026 retrieval", "status": "shipping", "scope": "s" }, "publishedcompute.s.2": { "value": "325", "field": "INT8 TOPS", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2026 retrieval", "status": "shipping", "scope": "s" }, "publishedcompute.s.3": { "value": "75 W", "field": "Rated power", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2026 retrieval", "status": "shipping", "scope": "s" }, "publishedcompute.s.4": { "value": "SDK 1.12 SKU table", "field": "Source basis", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2026 retrieval", "status": "shipping", "scope": "s" }, "publishedcompute.p.0": { "value": "Pro", "field": "Card", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2026 retrieval", "status": "shipping", "scope": "p" }, "publishedcompute.p.1": { "value": "125", "field": "FP16 TFLOP/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2026 retrieval", "status": "shipping", "scope": "p" }, "publishedcompute.p.2": { "value": "375", "field": "INT8 TOPS", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2026 retrieval", "status": "shipping", "scope": "p" }, "publishedcompute.p.3": { "value": "75 W", "field": "Rated power", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2026 retrieval", "status": "shipping", "scope": "p" }, "publishedcompute.p.4": { "value": "SDK 1.12 SKU table", "field": "Source basis", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2026 retrieval", "status": "shipping", "scope": "p" }, "publishedcompute.u.0": { "value": "Ultra", "field": "Card", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "P03" ], "disclosure_date": "2026 retrieval", "status": "shipping", "scope": "u" }, "publishedcompute.u.1": { "value": "288 product / 290 SDK", "field": "FP16 TFLOP/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "P03" ], "disclosure_date": "2026 retrieval", "status": "shipping", "scope": "u" }, "publishedcompute.u.2": { "value": "870", "field": "INT8 TOPS", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "P03" ], "disclosure_date": "2026 retrieval", "status": "shipping", "scope": "u" }, "publishedcompute.u.3": { "value": "150 W", "field": "Rated power", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "P03" ], "disclosure_date": "2026 retrieval", "status": "shipping", "scope": "u" }, "publishedcompute.u.4": { "value": "Small document revision/rounding difference retained", "field": "Source basis", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "P03" ], "disclosure_date": "2026 retrieval", "status": "shipping", "scope": "u" }, "network.o100.0": { "value": "Dragonfly O100", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "o100" }, "network.o100.1": { "value": "2026 portfolio", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "o100" }, "network.o100.2": { "value": "Announced; GA n/d", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "o100" }, "network.o100.3": { "value": "Optical DSP", "field": "Class", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "o100" }, "network.o100.4": { "value": "n/a", "field": "Ports × speed", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "o100" }, "network.o100.5": { "value": "100G PAM4 class", "field": "SerDes", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "o100" }, "network.o100.6": { "value": "n/a", "field": "Host interface", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "o100" }, "network.o100.7": { "value": "Signal processing; packet pipeline n/a", "field": "Programmable engine", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "o100" }, "network.o100.8": { "value": "n/a", "field": "Embedded CPU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "o100" }, "network.o100.9": { "value": "n/a", "field": "On-card memory", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "o100" }, "network.o100.10": { "value": "n/a", "field": "Transport / RDMA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "o100" }, "network.o100.11": { "value": "n/a", "field": "Congestion control", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "o100" }, "network.o100.12": { "value": "Optical link DSP", "field": "Key offloads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "o100" }, "network.o100.13": { "value": "n/d", "field": "Power", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "o100" }, "network.o200.0": { "value": "Dragonfly O200", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "o200" }, "network.o200.1": { "value": "2026 portfolio", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "o200" }, "network.o200.2": { "value": "Announced; GA n/d", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "o200" }, "network.o200.3": { "value": "Optical DSP", "field": "Class", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "o200" }, "network.o200.4": { "value": "n/a", "field": "Ports × speed", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "o200" }, "network.o200.5": { "value": "200G PAM4 class", "field": "SerDes", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "o200" }, "network.o200.6": { "value": "n/a", "field": "Host interface", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "o200" }, "network.o200.7": { "value": "DSP", "field": "Programmable engine", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "o200" }, "network.o200.8": { "value": "n/a", "field": "Embedded CPU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "o200" }, "network.o200.9": { "value": "n/a", "field": "On-card memory", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "o200" }, "network.o200.10": { "value": "n/a", "field": "Transport / RDMA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "o200" }, "network.o200.11": { "value": "n/a", "field": "Congestion control", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "o200" }, "network.o200.12": { "value": "Optical link DSP", "field": "Key offloads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "o200" }, "network.o200.13": { "value": "n/d", "field": "Power", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "o200" }, "network.co400.0": { "value": "Dragonfly CO400", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "co400" }, "network.co400.1": { "value": "2026 portfolio", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "co400" }, "network.co400.2": { "value": "Announced; GA n/d", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "co400" }, "network.co400.3": { "value": "Coherent-lite DSP", "field": "Class", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "co400" }, "network.co400.4": { "value": "n/a", "field": "Ports × speed", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "co400" }, "network.co400.5": { "value": "400G 16QAM", "field": "SerDes", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "co400" }, "network.co400.6": { "value": "n/a", "field": "Host interface", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "co400" }, "network.co400.7": { "value": "DSP", "field": "Programmable engine", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "co400" }, "network.co400.8": { "value": "n/a", "field": "Embedded CPU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "co400" }, "network.co400.9": { "value": "n/a", "field": "On-card memory", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "co400" }, "network.co400.10": { "value": "n/a", "field": "Transport / RDMA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "co400" }, "network.co400.11": { "value": "n/a", "field": "Congestion control", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "co400" }, "network.co400.12": { "value": "Longer-reach optics", "field": "Key offloads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "co400" }, "network.co400.13": { "value": "n/d", "field": "Power", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "co400" }, "network.cu100.0": { "value": "Dragonfly CU100", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "cu100" }, "network.cu100.1": { "value": "2026 portfolio", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "cu100" }, "network.cu100.2": { "value": "Announced; GA n/d", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "cu100" }, "network.cu100.3": { "value": "AEC DSP; 4 nm", "field": "Class", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "cu100" }, "network.cu100.4": { "value": "n/a", "field": "Ports × speed", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "cu100" }, "network.cu100.5": { "value": "100G PAM4", "field": "SerDes", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "cu100" }, "network.cu100.6": { "value": "n/a", "field": "Host interface", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "cu100" }, "network.cu100.7": { "value": "DSP", "field": "Programmable engine", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "cu100" }, "network.cu100.8": { "value": "n/a", "field": "Embedded CPU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "cu100" }, "network.cu100.9": { "value": "n/a", "field": "On-card memory", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "cu100" }, "network.cu100.10": { "value": "n/a", "field": "Transport / RDMA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "cu100" }, "network.cu100.11": { "value": "n/a", "field": "Congestion control", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "cu100" }, "network.cu100.12": { "value": "Electrical retiming", "field": "Key offloads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "cu100" }, "network.cu100.13": { "value": "n/d", "field": "Power", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "cu100" }, "network.cu200.0": { "value": "Dragonfly CU200", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "cu200" }, "network.cu200.1": { "value": "2026 portfolio", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "cu200" }, "network.cu200.2": { "value": "Announced; GA n/d", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "cu200" }, "network.cu200.3": { "value": "AEC DSP", "field": "Class", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "cu200" }, "network.cu200.4": { "value": "n/a", "field": "Ports × speed", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "cu200" }, "network.cu200.5": { "value": "200G PAM4", "field": "SerDes", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "cu200" }, "network.cu200.6": { "value": "n/a", "field": "Host interface", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "cu200" }, "network.cu200.7": { "value": "DSP", "field": "Programmable engine", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "cu200" }, "network.cu200.8": { "value": "n/a", "field": "Embedded CPU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "cu200" }, "network.cu200.9": { "value": "n/a", "field": "On-card memory", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "cu200" }, "network.cu200.10": { "value": "n/a", "field": "Transport / RDMA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "cu200" }, "network.cu200.11": { "value": "n/a", "field": "Congestion control", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "cu200" }, "network.cu200.12": { "value": "Electrical retiming", "field": "Key offloads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "cu200" }, "network.cu200.13": { "value": "n/d", "field": "Power", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09" ], "disclosure_date": "2026", "status": "disclosed", "scope": "cu200" }, "network.x100.0": { "value": "Dragonwing X100", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2021-2026", "status": "commercial product", "scope": "x100" }, "network.x100.1": { "value": "2021 disclosure", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2021-2026", "status": "commercial product", "scope": "x100" }, "network.x100.2": { "value": "Shipping / available", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2021-2026", "status": "commercial product", "scope": "x100" }, "network.x100.3": { "value": "5G RAN inline accelerator", "field": "Class", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2021-2026", "status": "commercial product", "scope": "x100" }, "network.x100.4": { "value": "n/d", "field": "Ports × speed", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2021-2026", "status": "commercial product", "scope": "x100" }, "network.x100.5": { "value": "n/d", "field": "SerDes", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2021-2026", "status": "commercial product", "scope": "x100" }, "network.x100.6": { "value": "PCIe", "field": "Host interface", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2021-2026", "status": "commercial product", "scope": "x100" }, "network.x100.7": { "value": "5G L1 software", "field": "Programmable engine", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2021-2026", "status": "commercial product", "scope": "x100" }, "network.x100.8": { "value": "n/d", "field": "Embedded CPU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2021-2026", "status": "commercial product", "scope": "x100" }, "network.x100.9": { "value": "n/d", "field": "On-card memory", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2021-2026", "status": "commercial product", "scope": "x100" }, "network.x100.10": { "value": "O-RAN fronthaul; AI RDMA n/a", "field": "Transport / RDMA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2021-2026", "status": "commercial product", "scope": "x100" }, "network.x100.11": { "value": "n/a", "field": "Congestion control", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2021-2026", "status": "commercial product", "scope": "x100" }, "network.x100.12": { "value": "Baseband L1 processing", "field": "Key offloads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2021-2026", "status": "commercial product", "scope": "x100" }, "network.x100.13": { "value": "n/d", "field": "Power", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2021-2026", "status": "commercial product", "scope": "x100" }, "interconnect.qsb.0": { "value": "QSB", "field": "Interconnect", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "qsb" }, "interconnect.qsb.1": { "value": "2017", "field": "Year / generation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "qsb" }, "interconnect.qsb.2": { "value": "n/a", "field": "Lane rate", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "qsb" }, "interconnect.qsb.3": { "value": "n/a", "field": "Lanes / link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "qsb" }, "interconnect.qsb.4": { "value": "n/d; >250 GB/s aggregate internal", "field": "GB/s per link per direction", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "qsb" }, "interconnect.qsb.5": { "value": "n/a", "field": "Links / device", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "qsb" }, "interconnect.qsb.6": { "value": "Segmented coherent ring", "field": "Topology", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "qsb" }, "interconnect.qsb.7": { "value": "48 cores", "field": "Domain limit", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "qsb" }, "interconnect.qsb.8": { "value": "CPU/cache/I/O coherence", "field": "Coherence / semantics", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "qsb" }, "interconnect.ai100.0": { "value": "Cloud AI 100 host", "field": "Interconnect", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2021", "status": "shipping", "scope": "ai100" }, "interconnect.ai100.1": { "value": "2021", "field": "Year / generation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2021", "status": "shipping", "scope": "ai100" }, "interconnect.ai100.2": { "value": "16 GT/s", "field": "Lane rate", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2021", "status": "shipping", "scope": "ai100" }, "interconnect.ai100.3": { "value": "8", "field": "Lanes / link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2021", "status": "shipping", "scope": "ai100" }, "interconnect.ai100.4": { "value": "~15.75", "field": "GB/s per link per direction", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2021", "status": "shipping", "scope": "ai100" }, "interconnect.ai100.5": { "value": "1", "field": "Links / device", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2021", "status": "shipping", "scope": "ai100" }, "interconnect.ai100.6": { "value": "PCIe", "field": "Topology", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2021", "status": "shipping", "scope": "ai100" }, "interconnect.ai100.7": { "value": "1 card", "field": "Domain limit", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2021", "status": "shipping", "scope": "ai100" }, "interconnect.ai100.8": { "value": "DMA / host I/O", "field": "Coherence / semantics", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2021", "status": "shipping", "scope": "ai100" }, "interconnect.ultra.0": { "value": "Ultra host / local", "field": "Interconnect", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2023", "status": "shipping", "scope": "ultra" }, "interconnect.ultra.1": { "value": "2023", "field": "Year / generation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2023", "status": "shipping", "scope": "ultra" }, "interconnect.ultra.2": { "value": "16 GT/s", "field": "Lane rate", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2023", "status": "shipping", "scope": "ultra" }, "interconnect.ultra.3": { "value": "16 host; 8/SoC", "field": "Lanes / link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2023", "status": "shipping", "scope": "ultra" }, "interconnect.ultra.4": { "value": "~31.5 host; ~15.75/SoC", "field": "GB/s per link per direction", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2023", "status": "shipping", "scope": "ultra" }, "interconnect.ultra.5": { "value": "4 SoC links", "field": "Links / device", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2023", "status": "shipping", "scope": "ultra" }, "interconnect.ultra.6": { "value": "On-card PCIe switch", "field": "Topology", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2023", "status": "shipping", "scope": "ultra" }, "interconnect.ultra.7": { "value": "4 SoCs", "field": "Domain limit", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2023", "status": "shipping", "scope": "ultra" }, "interconnect.ultra.8": { "value": "Partitioned local memory; PCIe movement", "field": "Coherence / semantics", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2023", "status": "shipping", "scope": "ultra" }, "interconnect.ai200.0": { "value": "AI200 / AI250 scale-up", "field": "Interconnect", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P05" ], "disclosure_date": "2026", "status": "sampling / roadmap", "scope": "ai200" }, "interconnect.ai200.1": { "value": "2026-2027", "field": "Year / generation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P05" ], "disclosure_date": "2026", "status": "sampling / roadmap", "scope": "ai200" }, "interconnect.ai200.2": { "value": "64 GT/s", "field": "Lane rate", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P05" ], "disclosure_date": "2026", "status": "sampling / roadmap", "scope": "ai200" }, "interconnect.ai200.3": { "value": "n/d", "field": "Lanes / link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P05" ], "disclosure_date": "2026", "status": "sampling / roadmap", "scope": "ai200" }, "interconnect.ai200.4": { "value": "n/d", "field": "GB/s per link per direction", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P05" ], "disclosure_date": "2026", "status": "sampling / roadmap", "scope": "ai200" }, "interconnect.ai200.5": { "value": "n/d", "field": "Links / device", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P05" ], "disclosure_date": "2026", "status": "sampling / roadmap", "scope": "ai200" }, "interconnect.ai200.6": { "value": "PCIe 6", "field": "Topology", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P05" ], "disclosure_date": "2026", "status": "sampling / roadmap", "scope": "ai200" }, "interconnect.ai200.7": { "value": "Rack solution; topology n/d", "field": "Domain limit", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P05" ], "disclosure_date": "2026", "status": "sampling / roadmap", "scope": "ai200" }, "interconnect.ai200.8": { "value": "Coherence not established", "field": "Coherence / semantics", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P05" ], "disclosure_date": "2026", "status": "sampling / roadmap", "scope": "ai200" }, "interconnect.ai300.0": { "value": "AI300 UALink / ESUN", "field": "Interconnect", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P08" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "interconnect.ai300.1": { "value": "FY28", "field": "Year / generation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P08" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "interconnect.ai300.2": { "value": "n/d", "field": "Lane rate", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P08" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "interconnect.ai300.3": { "value": "n/d", "field": "Lanes / link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P08" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "interconnect.ai300.4": { "value": "n/d", "field": "GB/s per link per direction", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P08" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "interconnect.ai300.5": { "value": "n/d", "field": "Links / device", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P08" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "interconnect.ai300.6": { "value": "Single-hop all-to-all target", "field": "Topology", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P08" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "interconnect.ai300.7": { "value": "n/d", "field": "Domain limit", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P08" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "interconnect.ai300.8": { "value": "Protocol details n/d", "field": "Coherence / semantics", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P08" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "systems.centriq.0": { "value": "Centriq OCP motherboard", "field": "Platform", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E12" ], "disclosure_date": "2017", "status": "demonstrated", "scope": "centriq" }, "systems.centriq.1": { "value": "2017", "field": "Year / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E12" ], "disclosure_date": "2017", "status": "demonstrated", "scope": "centriq" }, "systems.centriq.2": { "value": "Centriq 2400", "field": "CPU / accelerator count", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E12" ], "disclosure_date": "2017", "status": "demonstrated", "scope": "centriq" }, "systems.centriq.3": { "value": "1 socket", "field": "Scale-up domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E12" ], "disclosure_date": "2017", "status": "demonstrated", "scope": "centriq" }, "systems.centriq.4": { "value": "n/a", "field": "Scale-out per accelerator", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E12" ], "disclosure_date": "2017", "status": "demonstrated", "scope": "centriq" }, "systems.centriq.5": { "value": "n/d", "field": "Rack power", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E12" ], "disclosure_date": "2017", "status": "demonstrated", "scope": "centriq" }, "systems.centriq.6": { "value": "Server-dependent", "field": "Cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E12" ], "disclosure_date": "2017", "status": "demonstrated", "scope": "centriq" }, "systems.ultra.0": { "value": "Ultra inference server", "field": "Platform", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "R01" ], "disclosure_date": "2025", "status": "shipping", "scope": "ultra" }, "systems.ultra.1": { "value": "2023-2025", "field": "Year / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "R01" ], "disclosure_date": "2025", "status": "shipping", "scope": "ultra" }, "systems.ultra.2": { "value": "Host CPU + PCIe cards", "field": "CPU / accelerator count", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "R01" ], "disclosure_date": "2025", "status": "shipping", "scope": "ultra" }, "systems.ultra.3": { "value": "4 SoCs per card; system-dependent", "field": "Scale-up domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "R01" ], "disclosure_date": "2025", "status": "shipping", "scope": "ultra" }, "systems.ultra.4": { "value": "n/d", "field": "Scale-out per accelerator", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "R01" ], "disclosure_date": "2025", "status": "shipping", "scope": "ultra" }, "systems.ultra.5": { "value": "n/d", "field": "Rack power", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "R01" ], "disclosure_date": "2025", "status": "shipping", "scope": "ultra" }, "systems.ultra.6": { "value": "Air, platform-dependent", "field": "Cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "R01" ], "disclosure_date": "2025", "status": "shipping", "scope": "ultra" }, "systems.ai200.0": { "value": "AI200 ORv3", "field": "Platform", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026", "status": "sampling", "scope": "ai200" }, "systems.ai200.1": { "value": "2026", "field": "Year / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026", "status": "sampling", "scope": "ai200" }, "systems.ai200.2": { "value": "56 cards", "field": "CPU / accelerator count", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026", "status": "sampling", "scope": "ai200" }, "systems.ai200.3": { "value": "PCIe 6 rack integration", "field": "Scale-up domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026", "status": "sampling", "scope": "ai200" }, "systems.ai200.4": { "value": "RoCE; per-card rate n/d", "field": "Scale-out per accelerator", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026", "status": "sampling", "scope": "ai200" }, "systems.ai200.5": { "value": "140 kW", "field": "Rack power", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026", "status": "sampling", "scope": "ai200" }, "systems.ai200.6": { "value": "DLC reference; air option disclosed", "field": "Cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026", "status": "sampling", "scope": "ai200" }, "systems.ai250.0": { "value": "AI250 ORv3", "field": "Platform", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai250" }, "systems.ai250.1": { "value": "2027 target", "field": "Year / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai250" }, "systems.ai250.2": { "value": "43 TB rack; card count n/d here", "field": "CPU / accelerator count", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai250" }, "systems.ai250.3": { "value": "PCIe 6", "field": "Scale-up domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai250" }, "systems.ai250.4": { "value": "RoCE; rate n/d", "field": "Scale-out per accelerator", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai250" }, "systems.ai250.5": { "value": "n/d", "field": "Rack power", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai250" }, "systems.ai250.6": { "value": "Air / DLC", "field": "Cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai250" }, "systems.ai300.0": { "value": "AI300 + C1000", "field": "Platform", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P08", "E10" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "systems.ai300.1": { "value": "2028 roadmap", "field": "Year / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P08", "E10" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "systems.ai300.2": { "value": "Future CPU + HBC accelerators", "field": "CPU / accelerator count", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P08", "E10" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "systems.ai300.3": { "value": "All-to-all target", "field": "Scale-up domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P08", "E10" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "systems.ai300.4": { "value": "n/d", "field": "Scale-out per accelerator", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P08", "E10" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "systems.ai300.5": { "value": "n/d", "field": "Rack power", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P08", "E10" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "systems.ai300.6": { "value": "Liquid", "field": "Cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P08", "E10" ], "disclosure_date": "2026", "status": "roadmap", "scope": "ai300" }, "software.sdk.0": { "value": "Cloud AI SDK", "field": "Release / component", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "P13" ], "disclosure_date": "2026", "status": "available", "scope": "sdk" }, "software.sdk.1": { "value": "2021-2026", "field": "Date", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "P13" ], "disclosure_date": "2026", "status": "available", "scope": "sdk" }, "software.sdk.2": { "value": "Cloud AI 100 / Ultra", "field": "Hardware enabled", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "P13" ], "disclosure_date": "2026", "status": "available", "scope": "sdk" }, "software.sdk.3": { "value": "Compile, deploy, profile; model support is release-specific", "field": "Key features", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "P13" ], "disclosure_date": "2026", "status": "available", "scope": "sdk" }, "software.qnn.0": { "value": "AI Engine Direct / QNN", "field": "Release / component", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P14", "R04" ], "disclosure_date": "2026", "status": "available", "scope": "qnn" }, "software.qnn.1": { "value": "2022-2026", "field": "Date", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P14", "R04" ], "disclosure_date": "2026", "status": "available", "scope": "qnn" }, "software.qnn.2": { "value": "Snapdragon / Hexagon / Adreno", "field": "Hardware enabled", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P14", "R04" ], "disclosure_date": "2026", "status": "available", "scope": "qnn" }, "software.qnn.3": { "value": "On-device heterogeneous execution", "field": "Key features", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P14", "R04" ], "disclosure_date": "2026", "status": "available", "scope": "qnn" }, "software.suite.0": { "value": "AI Inference Suite / AIMS", "field": "Release / component", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2026", "status": "disclosed", "scope": "suite" }, "software.suite.1": { "value": "2026 disclosure", "field": "Date", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2026", "status": "disclosed", "scope": "suite" }, "software.suite.2": { "value": "Dragonfly", "field": "Hardware enabled", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2026", "status": "disclosed", "scope": "suite" }, "software.suite.3": { "value": "Serving, fleet management, QCCL and NPU-direct roadmap", "field": "Key features", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2026", "status": "disclosed", "scope": "suite" }, "software.modular.0": { "value": "Modular acquisition", "field": "Release / component", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E14" ], "disclosure_date": "2026-07", "status": "completed transaction", "scope": "modular" }, "software.modular.1": { "value": "2026-07", "field": "Date", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E14" ], "disclosure_date": "2026-07", "status": "completed transaction", "scope": "modular" }, "software.modular.2": { "value": "Cross-hardware AI software", "field": "Hardware enabled", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E14" ], "disclosure_date": "2026-07", "status": "completed transaction", "scope": "modular" }, "software.modular.3": { "value": "Completed acquisition; future hardware enablement separate", "field": "Key features", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E14" ], "disclosure_date": "2026-07", "status": "completed transaction", "scope": "modular" }, "ratios.centriq.0": { "value": "Centriq 48C", "field": "Configuration", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "E02" ], "disclosure_date": "2017", "status": "derived", "scope": "centriq" }, "ratios.centriq.1": { "value": "DRAM/core; LLC/core", "field": "Derived quantity", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "E02" ], "disclosure_date": "2017", "status": "derived", "scope": "centriq" }, "ratios.centriq.2": { "value": "~2.67 GB/s; 1.25 MB", "field": "Value", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "E02" ], "disclosure_date": "2017", "status": "derived", "scope": "centriq" }, "ratios.centriq.3": { "value": "Theoretical equal share", "field": "Interpretation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "E02" ], "disclosure_date": "2017", "status": "derived", "scope": "centriq" }, "ratios.pro.0": { "value": "AI 100 Pro", "field": "Configuration", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2026 retrieval", "status": "derived", "scope": "pro" }, "ratios.pro.1": { "value": "Memory BW / FP16 peak", "field": "Derived quantity", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2026 retrieval", "status": "derived", "scope": "pro" }, "ratios.pro.2": { "value": "0.001096 byte/FLOP", "field": "Value", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2026 retrieval", "status": "derived", "scope": "pro" }, "ratios.pro.3": { "value": "137 GB/s / 125 TFLOP/s; not BF16", "field": "Interpretation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2026 retrieval", "status": "derived", "scope": "pro" }, "ratios.ultra.0": { "value": "AI 100 Ultra", "field": "Configuration", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P03" ], "disclosure_date": "2026 retrieval", "status": "derived", "scope": "ultra" }, "ratios.ultra.1": { "value": "Memory BW / FP16 peak", "field": "Derived quantity", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P03" ], "disclosure_date": "2026 retrieval", "status": "derived", "scope": "ultra" }, "ratios.ultra.2": { "value": "0.001903 byte/FLOP", "field": "Value", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P03" ], "disclosure_date": "2026 retrieval", "status": "derived", "scope": "ultra" }, "ratios.ultra.3": { "value": "548 GB/s / 288 TFLOP/s product figure", "field": "Interpretation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P03" ], "disclosure_date": "2026 retrieval", "status": "derived", "scope": "ultra" }, "ratios.hostpro.0": { "value": "AI 100 Pro", "field": "Configuration", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2026 retrieval", "status": "derived", "scope": "hostpro" }, "ratios.hostpro.1": { "value": "Host / local memory bandwidth", "field": "Derived quantity", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2026 retrieval", "status": "derived", "scope": "hostpro" }, "ratios.hostpro.2": { "value": "~0.115", "field": "Value", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2026 retrieval", "status": "derived", "scope": "hostpro" }, "ratios.hostpro.3": { "value": "15.75 / 137; one direction; raw host link", "field": "Interpretation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2026 retrieval", "status": "derived", "scope": "hostpro" }, "ratios.hostultra.0": { "value": "AI 100 Ultra", "field": "Configuration", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2026 retrieval", "status": "derived", "scope": "hostultra" }, "ratios.hostultra.1": { "value": "Host / summed local memory BW", "field": "Derived quantity", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2026 retrieval", "status": "derived", "scope": "hostultra" }, "ratios.hostultra.2": { "value": "~0.0575", "field": "Value", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2026 retrieval", "status": "derived", "scope": "hostultra" }, "ratios.hostultra.3": { "value": "31.5 / 548; four memory domains", "field": "Interpretation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2026 retrieval", "status": "derived", "scope": "hostultra" }, "ratios.rack.0": { "value": "AI200", "field": "Configuration", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026", "status": "derived", "scope": "rack" }, "ratios.rack.1": { "value": "Memory/card; BW/card average", "field": "Derived quantity", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026", "status": "derived", "scope": "rack" }, "ratios.rack.2": { "value": "768 GB; ~7.39 TB/s", "field": "Value", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026", "status": "derived", "scope": "rack" }, "ratios.rack.3": { "value": "414 TB/s / 56 cards; no card-power inference", "field": "Interpretation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026", "status": "derived", "scope": "rack" }, "ratios.powerpro.0": { "value": "AI 100 Pro", "field": "Configuration", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2026 retrieval", "status": "derived", "scope": "powerpro" }, "ratios.powerpro.1": { "value": "FP16 peak / rated TDP", "field": "Derived quantity", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2026 retrieval", "status": "derived", "scope": "powerpro" }, "ratios.powerpro.2": { "value": "1.67 TFLOP/s/W", "field": "Value", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2026 retrieval", "status": "derived", "scope": "powerpro" }, "ratios.powerpro.3": { "value": "125 / 75; not measured tokens/W", "field": "Interpretation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2026 retrieval", "status": "derived", "scope": "powerpro" }, "ratios.powerultra.0": { "value": "AI 100 Ultra", "field": "Configuration", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P03" ], "disclosure_date": "2026 retrieval", "status": "derived", "scope": "powerultra" }, "ratios.powerultra.1": { "value": "FP16 peak / rated TDP", "field": "Derived quantity", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P03" ], "disclosure_date": "2026 retrieval", "status": "derived", "scope": "powerultra" }, "ratios.powerultra.2": { "value": "1.92 TFLOP/s/W", "field": "Value", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P03" ], "disclosure_date": "2026 retrieval", "status": "derived", "scope": "powerultra" }, "ratios.powerultra.3": { "value": "288 / 150; not whole-system energy", "field": "Interpretation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P03" ], "disclosure_date": "2026 retrieval", "status": "derived", "scope": "powerultra" }, "conference.falkor.0": { "value": "Hot Chips", "field": "Venue", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "E01" ], "disclosure_date": "2017", "status": "disclosed", "scope": "falkor" }, "conference.falkor.1": { "value": "2017", "field": "Year", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "E01" ], "disclosure_date": "2017", "status": "disclosed", "scope": "falkor" }, "conference.falkor.2": { "value": "Qualcomm Centriq 2400 Processor / Falkor", "field": "Paper / talk / disclosure", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "E01" ], "disclosure_date": "2017", "status": "disclosed", "scope": "falkor" }, "conference.falkor.3": { "value": "Qualcomm", "field": "Presenter / authors", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "E01" ], "disclosure_date": "2017", "status": "disclosed", "scope": "falkor" }, "conference.falkor.4": { "value": "Centriq", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "E01" ], "disclosure_date": "2017", "status": "disclosed", "scope": "falkor" }, "conference.falkor.5": { "value": "Architecture", "field": "Evidence type", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "E01" ], "disclosure_date": "2017", "status": "disclosed", "scope": "falkor" }, "conference.falkor.6": { "value": "C01 E01", "field": "Source", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "E01" ], "disclosure_date": "2017", "status": "disclosed", "scope": "falkor" }, "conference.cloud.0": { "value": "Hot Chips", "field": "Venue", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C06", "P01" ], "disclosure_date": "2021", "status": "disclosed", "scope": "cloud" }, "conference.cloud.1": { "value": "2021", "field": "Year", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C06", "P01" ], "disclosure_date": "2021", "status": "disclosed", "scope": "cloud" }, "conference.cloud.2": { "value": "Cloud AI 100: Scalable, High Performance and Low Latency Deep Learning Inference Accelerator", "field": "Paper / talk / disclosure", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C06", "P01" ], "disclosure_date": "2021", "status": "disclosed", "scope": "cloud" }, "conference.cloud.3": { "value": "Qualcomm", "field": "Presenter / authors", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C06", "P01" ], "disclosure_date": "2021", "status": "disclosed", "scope": "cloud" }, "conference.cloud.4": { "value": "Cloud AI 100", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C06", "P01" ], "disclosure_date": "2021", "status": "disclosed", "scope": "cloud" }, "conference.cloud.5": { "value": "Architecture", "field": "Evidence type", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C06", "P01" ], "disclosure_date": "2021", "status": "disclosed", "scope": "cloud" }, "conference.cloud.6": { "value": "C06 P01", "field": "Source", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C06", "P01" ], "disclosure_date": "2021", "status": "disclosed", "scope": "cloud" }, "conference.oryon.0": { "value": "Hot Chips / IEEE Micro", "field": "Venue", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C07", "C08", "C02" ], "disclosure_date": "2024 / 2025", "status": "disclosed", "scope": "oryon" }, "conference.oryon.1": { "value": "2024 / 2025", "field": "Year", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C07", "C08", "C02" ], "disclosure_date": "2024 / 2025", "status": "disclosed", "scope": "oryon" }, "conference.oryon.2": { "value": "Snapdragon X Elite Qualcomm Oryon CPU: Design & Architecture Overview", "field": "Paper / talk / disclosure", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C07", "C08", "C02" ], "disclosure_date": "2024 / 2025", "status": "disclosed", "scope": "oryon" }, "conference.oryon.3": { "value": "Gerard Williams / Qualcomm", "field": "Presenter / authors", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C07", "C08", "C02" ], "disclosure_date": "2024 / 2025", "status": "disclosed", "scope": "oryon" }, "conference.oryon.4": { "value": "Oryon", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C07", "C08", "C02" ], "disclosure_date": "2024 / 2025", "status": "disclosed", "scope": "oryon" }, "conference.oryon.5": { "value": "Architecture", "field": "Evidence type", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C07", "C08", "C02" ], "disclosure_date": "2024 / 2025", "status": "disclosed", "scope": "oryon" }, "conference.oryon.6": { "value": "C07 C08 C02", "field": "Source", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C07", "C08", "C02" ], "disclosure_date": "2024 / 2025", "status": "disclosed", "scope": "oryon" }, "conference.acd.0": { "value": "ISSCC / JSSC lineage", "field": "Venue", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C04" ], "disclosure_date": "2015 / 2016", "status": "disclosed", "scope": "acd" }, "conference.acd.1": { "value": "2015 / 2016", "field": "Year", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C04" ], "disclosure_date": "2015 / 2016", "status": "disclosed", "scope": "acd" }, "conference.acd.2": { "value": "Auto-calibrating adaptive clock distribution", "field": "Paper / talk / disclosure", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C04" ], "disclosure_date": "2015 / 2016", "status": "disclosed", "scope": "acd" }, "conference.acd.3": { "value": "Keith Bowman et al.", "field": "Presenter / authors", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C04" ], "disclosure_date": "2015 / 2016", "status": "disclosed", "scope": "acd" }, "conference.acd.4": { "value": "Circuit research; Snapdragon 820 link", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C04" ], "disclosure_date": "2015 / 2016", "status": "disclosed", "scope": "acd" }, "conference.acd.5": { "value": "Circuit research", "field": "Evidence type", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C04" ], "disclosure_date": "2015 / 2016", "status": "disclosed", "scope": "acd" }, "conference.acd.6": { "value": "C04", "field": "Source", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C04" ], "disclosure_date": "2015 / 2016", "status": "disclosed", "scope": "acd" }, "conference.isscc.0": { "value": "ISSCC", "field": "Venue", "basis": "Per reference product; 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theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2025", "status": "disclosed", "scope": "isscc" }, "conference.isscc.5": { "value": "Tutorial", "field": "Evidence type", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2025", "status": "disclosed", "scope": "isscc" }, "conference.isscc.6": { "value": "C03", "field": "Source", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2025", "status": "disclosed", "scope": "isscc" }, "conference.asplos.0": { "value": "ASPLOS", "field": "Venue", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R04" ], "disclosure_date": "2025", "status": "disclosed", "scope": "asplos" }, "conference.asplos.1": { "value": "2025", "field": "Year", "basis": "Per reference product; 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Rouhani et al.", "field": "Presenter / authors", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R02" ], "disclosure_date": "2023", "status": "disclosed", "scope": "isca" }, "conference.isca.4": { "value": "Numerical-format background", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R02" ], "disclosure_date": "2023", "status": "disclosed", "scope": "isca" }, "conference.isca.5": { "value": "Related research", "field": "Evidence type", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R02" ], "disclosure_date": "2023", "status": "disclosed", "scope": "isca" }, "conference.isca.6": { "value": "R02", "field": "Source", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R02" ], "disclosure_date": "2023", "status": "disclosed", "scope": "isca" }, "conference.ocp.0": { "value": "OCP Summit", "field": "Venue", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E12" ], "disclosure_date": "2017", "status": "disclosed", "scope": "ocp" }, "conference.ocp.1": { "value": "2017", "field": "Year", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E12" ], "disclosure_date": "2017", "status": "disclosed", "scope": "ocp" }, "conference.ocp.2": { "value": "Centriq Open Compute motherboard with Microsoft", "field": "Paper / talk / disclosure", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E12" ], "disclosure_date": "2017", "status": "disclosed", "scope": "ocp" }, "conference.ocp.3": { "value": "Qualcomm / Microsoft", "field": "Presenter / authors", "basis": "Per reference product; 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"disclosed", "scope": "mwc" }, "conference.mwc.4": { "value": "X100 RAN", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E11" ], "disclosure_date": "2021", "status": "disclosed", "scope": "mwc" }, "conference.mwc.5": { "value": "Product / system", "field": "Evidence type", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E11" ], "disclosure_date": "2021", "status": "disclosed", "scope": "mwc" }, "conference.mwc.6": { "value": "E11", "field": "Source", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E11" ], "disclosure_date": "2021", "status": "disclosed", "scope": "mwc" }, "conference.summit.0": { "value": "Snapdragon Summit", "field": "Venue", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E17", "P12" ], "disclosure_date": "2023 / 2025", "status": "disclosed", "scope": "summit" }, "conference.summit.1": { "value": "2023 / 2025", "field": "Year", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E17", "P12" ], "disclosure_date": "2023 / 2025", "status": "disclosed", "scope": "summit" }, "conference.summit.2": { "value": "X Elite / X2 Elite", "field": "Paper / talk / disclosure", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E17", "P12" ], "disclosure_date": "2023 / 2025", "status": "disclosed", "scope": "summit" }, "conference.summit.3": { "value": "Qualcomm", "field": "Presenter / authors", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E17", "P12" ], "disclosure_date": "2023 / 2025", "status": "disclosed", "scope": "summit" }, "conference.summit.4": { "value": "Oryon client lineage", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E17", "P12" ], "disclosure_date": "2023 / 2025", "status": "disclosed", "scope": "summit" }, "conference.summit.5": { "value": "Product launch", "field": "Evidence type", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E17", "P12" ], "disclosure_date": "2023 / 2025", "status": "disclosed", "scope": "summit" }, "conference.summit.6": { "value": "E17 P12", "field": "Source", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E17", "P12" ], "disclosure_date": "2023 / 2025", "status": "disclosed", "scope": "summit" }, "conference.investor.0": { "value": "Investor Day", "field": "Venue", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E09", "E10" ], "disclosure_date": "2026", "status": "disclosed", "scope": "investor" }, "conference.investor.1": { "value": "2026", "field": "Year", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E09", "E10" ], "disclosure_date": "2026", "status": "disclosed", "scope": "investor" }, "conference.investor.2": { "value": "Dragonfly CPU, HBC, accelerators and connectivity", "field": "Paper / talk / disclosure", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E09", "E10" ], "disclosure_date": "2026", "status": "disclosed", "scope": "investor" }, "conference.investor.3": { "value": "Tony Pialis", "field": "Presenter / authors", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E09", "E10" ], "disclosure_date": "2026", "status": "disclosed", "scope": "investor" }, "conference.investor.4": { "value": "C1000 / AI200-300 / DSPs", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E09", "E10" ], "disclosure_date": "2026", "status": "disclosed", "scope": "investor" }, "conference.investor.5": { "value": "Roadmap / system", "field": "Evidence type", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E09", "E10" ], "disclosure_date": "2026", "status": "disclosed", "scope": "investor" }, "conference.investor.6": { "value": "P08 E09 E10", "field": "Source", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E09", "E10" ], "disclosure_date": "2026", "status": "disclosed", "scope": "investor" }, "conference.infra.0": { "value": "AI Infra Summit", "field": "Venue", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07" ], "disclosure_date": "2026", "status": "disclosed", "scope": "infra" }, "conference.infra.1": { "value": "2026", "field": "Year", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07" ], "disclosure_date": "2026", "status": "disclosed", "scope": "infra" }, "conference.infra.2": { "value": "Dragonfly inference demonstrations", "field": "Paper / talk / disclosure", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07" ], "disclosure_date": "2026", "status": "disclosed", "scope": "infra" }, "conference.infra.3": { "value": "Qualcomm", "field": "Presenter / authors", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07" ], "disclosure_date": "2026", "status": "disclosed", "scope": "infra" }, "conference.infra.4": { "value": "AI200", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07" ], "disclosure_date": "2026", "status": "disclosed", "scope": "infra" }, "conference.infra.5": { "value": "Demonstration", "field": "Evidence type", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07" ], "disclosure_date": "2026", "status": "disclosed", "scope": "infra" }, "conference.infra.6": { "value": "E07", "field": "Source", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07" ], "disclosure_date": "2026", "status": "disclosed", "scope": "infra" }, "crosswalk.falkor.0": { "value": "Falkor", "field": "Name", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01" ], "disclosure_date": "2017", "status": "historical", "scope": "falkor" }, "crosswalk.falkor.1": { "value": "Custom CPU core in Centriq 2400", "field": "Product identity", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01" ], "disclosure_date": "2017", "status": "historical", "scope": "falkor" }, "crosswalk.falkor.2": { "value": "Not Neoverse; not Oryon", "field": "Boundary", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01" ], "disclosure_date": "2017", "status": "historical", "scope": "falkor" }, "crosswalk.oryon.0": { "value": "Oryon", "field": "Name", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C07", "P07" ], "disclosure_date": "2026", "status": "mixed", "scope": "oryon" }, "crosswalk.oryon.1": { "value": "Custom CPU family; client and future server", "field": "Product identity", "basis": "Per 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and format as labelled", "source": [ "P01" ], "disclosure_date": "2021", "status": "shipping", "scope": "pro" }, "hierarchy.pro.3": { "value": "PCIe 4 x8 ~15.75 GB/s/direction", "field": "CPU / scale-up", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2021", "status": "shipping", "scope": "pro" }, "hierarchy.pro.4": { "value": "External NIC; n/d", "field": "Scale-out", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2021", "status": "shipping", "scope": "pro" }, "hierarchy.ultra.0": { "value": "2023 Ultra", "field": "Era / reference", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2023", "status": "shipping", "scope": "ultra" }, "hierarchy.ultra.1": { "value": "4 discrete SoCs; PCIe switch", "field": "On-die / die-to-die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2023", "status": "shipping", "scope": "ultra" }, "hierarchy.ultra.2": { "value": "548 GB/s summed", "field": "Local memory", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2023", "status": "shipping", "scope": "ultra" }, "hierarchy.ultra.3": { "value": "PCIe 4 x16 ~31.5 GB/s/direction", "field": "CPU / scale-up", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2023", "status": "shipping", "scope": "ultra" }, "hierarchy.ultra.4": { "value": "External NIC; n/d", "field": "Scale-out", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], 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], "status": "disclosed", "basis": "rated power", "direction": "n/a", "format": "n/a", "date": "2026-09-28" }, "ai200.cards": { "value": 56, "unit": "cards", "scope": "rack", "source": [ "P04" ], "status": "sampling", "basis": "published reference", "direction": "n/a", "format": "n/a", "date": "2026-09-28" }, "ai200.memory": { "value": 768, "unit": "GB", "scope": "card", "source": [ "P04" ], "status": "sampling", "basis": "LPDDR", "direction": "n/a", "format": "n/a", "date": "2026-09-28" }, "ai200.rackbw": { "value": 414, "unit": "TB/s", "scope": "rack", "source": [ "P04" ], "status": "sampling", "basis": "0.414 PB/s converted", "direction": "n/a", "format": "n/a", "date": "2026-09-28" }, "ai200.cardbw": { "value": 7.393, "unit": "TB/s", "scope": "card arithmetic average", "source": [ "P04" ], "status": "sampling", "basis": "rack bandwidth / cards", "direction": "n/a", "format": "n/a", "date": "2026-09-28" }, "ai200.rackpower": { "value": 140, "unit": "kW", "scope": "rack", "source": [ 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