{ "cutoff": "2026-09-28", "sections": [ { "id": "01", "title": [ "Executive synthesis", "执行摘要" ], "blocks": [ { "id": "01.thesis", "type": "prose", "text": [ "NVIDIA’s decade-long transition is best understood as a change in the unit of architecture: from a PCIe accelerator, to an NVLink-connected server, to a coherent CPU–GPU module, and finally to a rack-scale compute and networking platform. Tensor Core arithmetic is one part of that transition. Memory capacity, data movement, synchronization, network congestion, power delivery, and software scheduling increasingly determine how much of the arithmetic a deployed system can use.", "理解 NVIDIA 过去十余年的演进，关键是观察架构设计单元的变化：从 PCIe 加速卡，到通过 NVLink 连接的服务器，再到具有缓存一致性的 CPU–GPU 模块，最终扩展到机架级计算与网络平台。Tensor Core 算术单元只是其中一环。内存容量、数据搬移、同步、网络拥塞、供电和软件调度，日益决定实际系统能够利用多少标称算力。" ], "sources": [ "P01", "P02", "P04", "P08", "P11" ] }, { "id": "01.findings", "type": "prose", "text": [ "Five changes define the product history. Pascal made HBM and GPU-to-GPU links central to the datacenter GPU. Volta established programmable matrix acceleration. Ampere broadened numerical formats and introduced practical multi-instance partitioning. Hopper reorganized execution around asynchronous tensor computation and data movement while Grace supplied a coherent, high-bandwidth CPU memory tier. Blackwell crossed the reticle boundary and moved the primary scale-up domain into the rack. Rubin extends this system approach with a new CPU core, HBM4, faster fabrics, and a more explicit separation between GPU computation, infrastructure processing, and latency-oriented inference.", "产品史中有五项关键变化。Pascal 将 HBM 和 GPU 间高速互联确立为数据中心 GPU 的核心。Volta 建立了可编程矩阵加速路径。Ampere 扩展数值格式，并引入实用的多实例分区。Hopper 围绕异步张量计算和数据搬移重新组织执行，Grace 则提供高带宽且具有缓存一致性的 CPU 内存层。Blackwell 跨越光刻掩模尺寸限制，把主要的纵向扩展域推进到机架。Rubin 延续这一系统路线，引入新的 CPU 核心、HBM4、更快互联，并进一步区分 GPU 计算、基础设施处理与低延迟推理。" ], "sources": [ "P01", "P02", "P03", "P04", "P08", "P05", "P11", "P12" ] }, { "id": "01.scope", "type": "prose", "text": [ "This report covers 2015 through 28 September 2026. It is organized by product generation, not conference chronology. Hot Chips supplies high-level architecture; ISSCC supplies selected implementation disclosures; ISCA, MICRO, HPCA and ASPLOS supply research mechanisms and context. Vendor specifications, tuning guides and partner availability announcements connect those disclosures to commercial products. Research proposals are not treated as proof of adoption. The conference index is a curated map of the most useful disclosures, not an exhaustive bibliography of every NVIDIA-affiliated paper or appearance.", "本报告覆盖 2015 年至 2026 年 9 月 28 日，按产品代际而非会议时间编排。Hot Chips 提供高层架构信息；ISSCC 提供部分实现细节；ISCA、MICRO、HPCA 和 ASPLOS 提供研究机制及其背景。厂商规格、调优指南与合作伙伴商用公告，将这些披露与商业产品连接起来。研究提案不被视为已经应用于产品的证据。会议索引筛选最有价值的披露，并非穷尽 NVIDIA 参与的全部论文与活动。" ], "sources": [ "C01", "C04", "C08", "C09", "R01", "R04", "R05", "E14", "E15", "E16" ] }, { "id": "headline", "type": "table", "table": "headline" }, { "id": "01.status", "type": "prose", "text": [ "Availability is a product-level attribute. A production announcement, an OEM shipment, a cloud service reaching general availability, and an MLPerf preview submission are different milestones. Blackwell has direct cloud GA evidence in 2025. Rubin has production disclosures and September 2026 preview results; those do not, by themselves, establish broad cloud GA. The report therefore records announced capabilities and the deployment milestone separately. Roadmap products remain separate from shipping comparisons.", "可用性必须落实到具体产品。量产公告、OEM 出货、云服务正式商用，以及 MLPerf 预览提交，是不同里程碑。Blackwell 在 2025 年已有直接的云服务正式商用证据。Rubin 已有量产披露和 2026 年 9 月预览结果，但这些证据本身不能证明广泛的云端正式商用。因此，报告将已公布能力与部署里程碑分别记录，并把路线图产品与已出货产品比较分开。" ], "sources": [ "E01", "E08", "E14", "E15", "E16" ] } ] }, { "id": "02", "title": [ "Reading the specifications correctly", "规格口径与比较方法" ], "blocks": [ { "id": "02.basis", "type": "prose", "text": [ "All compute rates are peak theoretical rates unless explicitly identified as measured results. A multiply-add counts as two operations. Dense and structured-sparse rates are kept separate; a sparse headline is not a dense capability. FP16 is not BF16, INT8 TOPS are not floating-point TFLOPS, and emulated FP64 is not native FP64. The report uses decimal GB/s and TB/s for interface bandwidth. A full-duplex total is divided by two only when the source defines a symmetric aggregate bidirectional rate. Switch capacity, endpoint injection rate, bisection bandwidth and the sum of all links are different quantities.", "除明确标为实测结果外，算力均为理论峰值；一次乘加计为两次运算。稠密与结构化稀疏吞吐量分开记录，不能将稀疏宣传值当作稠密能力。FP16 不等于 BF16，INT8 TOPS 不等于浮点 TFLOPS，模拟 FP64 也不等于原生 FP64。接口带宽采用十进制 GB/s 和 TB/s。仅当来源明确给出对称的双向聚合速率时，才除以二得到单方向值。交换容量、端点注入带宽、二分带宽与所有链路带宽之和是不同指标。" ], "sources": [ "P03", "P06", "P11", "P37", "P38" ] }, { "id": "02.sku", "type": "prose", "text": [ "SKU identity matters as much as architecture identity. PCIe and SXM GPUs can differ in enabled SMs, clocks, HBM speed, power and NVLink support. B200 HGX specifications are not automatically GB200 specifications. Blackwell Ultra’s dense and sparse FP4 modes do not share a universal 2:1 ratio. The HGX page gives B200 and B300 different dense FP4 rates despite the same sparse headline. Similarly, the Rubin chip-level peak and the power-managed NVL72 configuration expose different HBM and NVLink bandwidths. Both are retained with their configuration labels instead of selecting the larger number everywhere.", "SKU 身份与架构身份同样重要。PCIe 与 SXM GPU 的启用 SM 数量、频率、HBM 速度、功耗和 NVLink 支持可能不同。不能把 B200 HGX 规格直接套用到 GB200。Blackwell Ultra 的稠密与稀疏 FP4 模式并不存在通用的 2:1 比例。HGX 页面中，B200 与 B300 的稀疏标称值相同，但稠密 FP4 不同。同样，Rubin 的芯片峰值与受功率管理约束的 NVL72 配置具有不同 HBM 和 NVLink 带宽。报告保留各自的配置标签，而非一律采用较大数字。" ], "sources": [ "P13", "P15", "P06", "P37", "P38" ] }, { "id": "02.notation", "type": "prose", "text": [ "n/d means the reviewed primary sources did not establish the value at the required product scope; it does not mean zero. n/a means the field does not apply. Historical shipping means commercial deployment occurred, not that every old SKU remains orderable. GA columns use the first commercial year where established; an explicit announcement or preview label is not a GA date. Table panels retain the complete family schema. Bibliography IDs are collected in the source map at the end so the technical narrative remains readable.", "n/d 表示已审阅的一手资料未能在要求的产品范围内确定该值，并不代表零；n/a 表示不适用。“历史已商用”表示曾有商业部署，不意味着所有旧型号目前仍可订购。GA 栏在证据明确时采用首次商用年份；明确标注的发布或预览时间不是正式商用日期。分面表格保留完整的产品族字段。文末按章节汇总来源编号，避免打断技术叙述。" ], "sources": [ "P01", "P02", "P03", "E08", "E14", "E15", "E16" ] } ] }, { "id": "03", "title": [ "GPU specification atlas", "GPU 规格总览" ], "blocks": [ { "id": "gpu", "type": "table", "table": "gpu" }, { "id": "03.notes", "type": "prose", "text": [ "The atlas selects one reference configuration rather than merging every variant. P100 and V100 accelerate FP16 but do not have native BF16 Tensor Cores. A100’s original 40 GB version has 1.555 TB/s HBM bandwidth; the table uses the later 80 GB SXM version. B200/B300 compute figures are normalized from the HGX eight-GPU aggregate. B300 nominal memory is up to 288 GB per GPU in the DGX guide, while the HGX page lists 2.1 TB per eight-GPU platform; these are not silently equated. Product-specific memory accounting must be checked before capacity planning. The Rubin row is a preliminary chip-peak reference, not a promise that a rack sustains those rates simultaneously.", "总览表选择代表性配置，而不混合所有变体。P100 和 V100 可以加速 FP16，但没有原生 BF16 Tensor Core。A100 最初的 40 GB 版本具有 1.555 TB/s HBM 带宽；表中使用后续 80 GB SXM 版本。B200／B300 算力由 HGX 八 GPU 聚合值归一化得到。DGX 指南列出的 B300 单 GPU 标称内存最高为 288 GB，而 HGX 页面列出八 GPU 平台共 2.1 TB；报告不将两者悄然视为相同值。容量规划前应核对具体产品的内存统计口径。Rubin 行为初步的芯片峰值参考，不代表机架能同时持续达到所有峰值。" ], "sources": [ "P01", "P02", "P03", "P15", "P17", "P37" ] } ] }, { "id": "04", "title": [ "Maxwell and Pascal: establishing the accelerator system", "Maxwell 与 Pascal：形成加速器系统" ], "blocks": [ { "id": "04.maxwell", "type": "prose", "text": [ "Tesla M40 is the useful 2015 baseline: a graphics-derived Maxwell GPU adapted to datacenter deep learning, with GDDR5, a PCIe host connection and conventional CUDA arithmetic. Its value was parallel FP32 throughput and a mature programming platform, not dedicated tensor hardware. This establishes why a chronology beginning with Tensor Cores misses a major transition: before optimizing matrix instructions, NVIDIA had to improve the bandwidth and topology around the processor.", "Tesla M40 是理解 2015 年起点的合适参照：它将源于图形处理的 Maxwell GPU 用于数据中心深度学习，采用 GDDR5、PCIe 主机连接和常规 CUDA 算术。其价值在于并行 FP32 吞吐量与成熟编程平台，而不是专用张量硬件。因此，如果产品史从 Tensor Core 才开始，就会遗漏一次重要转变：在优化矩阵指令之前，NVIDIA 首先需要改善处理器周边的带宽与拓扑。" ], "sources": [ "P42", "E18" ] }, { "id": "04.pascal", "type": "prose", "text": [ "P100’s GP100 die combines a compute-oriented SM, stronger FP64 capability, packed FP16 arithmetic, HBM2 and first-generation NVLink. Four HBM stacks move memory onto the advanced package; the resulting bandwidth comes with packaging complexity, stack capacity limits and thermal coupling. Four NVLink connections provide 80 GB/s in each direction in aggregate. That is a peer interconnect budget, not additional HBM bandwidth. PCIe still connects the host, and the actual usefulness of NVLink depends on which GPU pairs the server wires together.", "P100 的 GP100 裸片结合了面向计算的 SM、更强的 FP64 能力、打包 FP16 运算、HBM2 与第一代 NVLink。四个 HBM 堆栈将内存搬到先进封装上，在获得带宽的同时引入封装复杂性、堆栈容量限制和热耦合。四条 NVLink 的聚合单方向带宽为 80 GB/s。这是对等互联预算，不是额外的 HBM 带宽。主机仍通过 PCIe 连接，NVLink 的实际价值取决于服务器将哪些 GPU 对直接连接。" ], "sources": [ "P01", "P36", "C01" ] }, { "id": "04.variants", "type": "prose", "text": [ "Pascal also demonstrates why architecture names are insufficient for product comparisons. P4 and P40 use GDDR memory and emphasize efficient inference, including INT8, rather than reproducing GP100’s HBM and HPC balance. P4’s low-profile, low-power deployment target and P40’s larger inference card are separate points on the same market map. A system architect should therefore track training/HPC and inference/graphics derivatives as branches, not treat every Pascal product as a smaller P100. Hot Chips 2016 explains the P100/NVLink system direction; product briefs distinguish the commercial branches.", "Pascal 也说明，仅凭架构名称无法比较产品。P4 和 P40 采用 GDDR 内存，侧重包括 INT8 在内的高效推理，而非复制 GP100 的 HBM 与 HPC 配比。P4 面向低矮、低功耗部署，P40 则是更大规模的推理卡，它们是同一市场图谱中的不同分支。因此，系统架构师应分别追踪训练／HPC 与推理／图形衍生线，而不应将所有 Pascal 产品看成缩小版 P100。Hot Chips 2016 解释 P100／NVLink 的系统方向，产品资料则区分其商业分支。" ], "sources": [ "P01", "E18", "C01" ] } ] }, { "id": "05", "title": [ "Volta: matrix execution and switched scale-up", "Volta：矩阵执行与交换式纵向扩展" ], "blocks": [ { "id": "05.tensor", "type": "prose", "text": [ "Volta’s defining change is the Tensor Core: a matrix multiply-accumulate datapath exposed through CUDA programming abstractions and libraries. V100’s peak FP16 tensor rate is not a replacement for its conventional FP32 or FP64 rate; it applies to a particular operand format, accumulation behavior and matrix execution path. Algorithms must produce suitable tiles and feed those units. The SM also separates integer and floating-point execution resources and introduces independent thread scheduling, changing the assumptions under which warp-synchronous code is safe.", "Volta 的标志性变化是 Tensor Core：通过 CUDA 编程抽象和库向软件开放的矩阵乘加数据通路。V100 的 FP16 张量峰值并不能替代常规 FP32 或 FP64 指标；它对应特定输入格式、累加行为和矩阵执行路径。算法必须组织合适的矩阵分块并持续供数。SM 还分离了整数与浮点执行资源，并引入独立线程调度，从而改变了依赖 warp 同步执行的代码能够安全工作的条件。" ], "sources": [ "P02", "P35", "C02" ] }, { "id": "05.fabric", "type": "prose", "text": [ "Second-generation NVLink raises V100’s aggregate one-way peer bandwidth to 150 GB/s. NVSwitch subsequently changes the server from a collection of selected direct links into a switched GPU fabric, exemplified by the 16-GPU DGX-2 domain. The important gain is not only link speed: a more regular topology makes all-to-all communication and collective scheduling easier to exploit. It does not remove collective algorithm costs, synchronization or memory placement decisions. HBM remains physically local to each GPU even when remote data is addressable.", "第二代 NVLink 将 V100 的聚合单方向对等带宽提高到 150 GB/s。随后，NVSwitch 将服务器从若干特定直连链路组成的集合，变为交换式 GPU 网络，16 GPU 的 DGX-2 域是典型例子。其收益不只是链路速度：更规则的拓扑更利于全互联通信和集合通信调度。但它不会消除集合算法开销、同步或内存放置决策。即使可以寻址远端数据，HBM 在物理上仍属于各自 GPU。" ], "sources": [ "P02", "P18" ] }, { "id": "05.turing", "type": "prose", "text": [ "Turing’s T4 is the parallel inference branch. It combines Tensor Cores, low-precision inference support, video capability and a 70 W PCIe form factor with GDDR6 rather than HBM. That combination favors broad server deployment and inference density, not a large NVLink training domain. The distinction persists through L4, L40S and RTX PRO Blackwell: a shared numerical or shader lineage does not imply equivalent memory bandwidth, FP64 capability or scale-up connectivity.", "Turing 的 T4 是并行发展的推理分支。它将 Tensor Core、低精度推理支持、视频能力与 70 W PCIe 形态结合，采用 GDDR6 而非 HBM。这一组合利于广泛的服务器部署与推理密度，而不是构建大型 NVLink 训练域。类似区分延续到 L4、L40S 和 RTX PRO Blackwell：共享数值计算或着色器技术血缘，并不意味着内存带宽、FP64 能力或纵向扩展连接相同。" ], "sources": [ "P28", "P29", "P30", "P31" ] } ] }, { "id": "06", "title": [ "Ampere: numerical breadth, isolation and implementation", "Ampere：数值格式、隔离与实现" ], "blocks": [ { "id": "06.compute", "type": "prose", "text": [ "A100 makes the tensor path useful to a wider range of workloads. BF16 preserves a large exponent range for training; TF32 gives FP32-facing workloads a tensor execution option with reduced mantissa precision; FP64 Tensor Cores extend matrix acceleration into HPC. Structured sparsity increases throughput only when the required sparsity pattern and software path are satisfied. This is an algorithmic contract, not a universal doubling of the chip. The 40 MB L2 cache and software-managed data movement help reuse operands before going back to HBM.", "A100 将张量路径扩展到更广泛的负载。BF16 为训练保留较大的指数范围；TF32 为面向 FP32 的负载提供尾数精度降低的张量执行选项；FP64 Tensor Core 则将矩阵加速延伸至 HPC。结构化稀疏只有在满足规定稀疏模式和软件路径时才能提升吞吐量。这是算法与硬件之间的约定，并非芯片在所有情况下都翻倍。40 MB L2 缓存以及软件管理的数据搬移，有助于在再次访问 HBM 前复用操作数。" ], "sources": [ "P03", "P34" ] }, { "id": "06.mig", "type": "prose", "text": [ "Multi-Instance GPU partitions A100 into as many as seven hardware-isolated GPU instances, with assigned compute and memory-system resources. This is materially different from merely time-sharing a process context. It enables smaller services to consume fractions of an expensive accelerator with stronger performance isolation. The trade-off is fragmentation: fixed profiles and memory capacity can strand resources when requests do not match the available partitions. Cluster placement, model size and scheduling remain necessary complements to the hardware.", "Multi-Instance GPU（MIG，多实例 GPU）可将 A100 划分为最多七个硬件隔离实例，为各实例分配计算与内存系统资源。这与仅在时间上共享进程上下文有本质区别：较小服务可以只占用昂贵加速器的一部分，同时获得更强的性能隔离。代价是碎片化：当请求与可用分区不匹配时，固定配置和内存容量可能导致资源闲置。因此，集群放置、模型规模选择与调度仍是必需的软件配套。" ], "sources": [ "P03", "C08" ] }, { "id": "06.implementation", "type": "prose", "text": [ "The ISSCC 2021 A100 disclosure supplies a rare direct bridge from the marketed architecture to implementation: a 7 nm, approximately 54-billion-transistor, 826 mm² datacenter GPU. Combined with the Ampere whitepaper and Hot Chips material, it connects arithmetic, partitioning and I/O to a very large monolithic die. The 80 GB HBM2e refresh increases both capacity and bandwidth without a new SM generation. This is an early example of a recurring pattern: a memory refresh can materially improve model fit and utilization even when headline compute changes little.", "ISSCC 2021 的 A100 披露提供了一条少见的、从产品架构通向实现的直接证据链：7 nm 工艺、约 540 亿晶体管、826 mm² 的数据中心 GPU。结合 Ampere 白皮书和 Hot Chips 资料，可以将算术单元、分区与 I/O 对应到一颗极大的单片裸片。后续 80 GB HBM2e 版本在未改变 SM 代际的情况下，同时提高容量与带宽。这体现了此后反复出现的模式：即使标称算力变化很小，内存升级也可能明显改善模型容纳能力与利用率。" ], "sources": [ "C08", "C03", "P03", "P15" ] } ] }, { "id": "07", "title": [ "Hopper and H200: asynchronous computation and memory", "Hopper 与 H200：异步计算与内存" ], "blocks": [ { "id": "07.execution", "type": "prose", "text": [ "Hopper addresses the work required to keep tensor arithmetic busy. The Tensor Memory Accelerator moves multidimensional tiles with less thread involvement. Warp-group matrix instructions coordinate a larger execution group than the earlier warp-level path. Thread-block clusters and distributed shared memory allow cooperating blocks to share data and synchronize within a defined locality domain. Together these mechanisms encourage pipelined kernels: one stage prepares data while another computes. They do not eliminate resource constraints; registers, shared memory, barriers and cluster occupancy still bound the useful pipeline depth.", "Hopper 重点降低维持张量算术单元繁忙所需的开销。Tensor Memory Accelerator（TMA，张量内存加速器）以更少线程参与完成多维数据块搬移。Warp-group 矩阵指令协同的执行组比先前 warp 级路径更大。线程块集群与分布式共享内存，使协作线程块可以在规定的局部域内共享数据并同步。这些机制共同支持流水化内核：一个阶段准备数据，另一个阶段执行计算。但资源约束不会消失；寄存器、共享内存、屏障与集群占用率仍限制有效流水深度。" ], "sources": [ "P04", "P33", "C04" ] }, { "id": "07.formats", "type": "prose", "text": [ "The Transformer Engine couples FP8 hardware with software-managed scaling and precision selection. E4M3 and E5M2 serve different numerical needs, so a throughput figure without format and accuracy conditions is incomplete. Hopper also adds DPX instructions for dynamic programming and strengthens confidential-computing support. Those capabilities widen the GPU’s workload and deployment envelope; they should not be reduced to an LLM-only narrative. H100’s fourth-generation NVLink supplies 900 GB/s aggregate bidirectional bandwidth, or 450 GB/s per direction, while an eight-GPU HGX fabric remains a distinct resource from its external network.", "Transformer Engine 将 FP8 硬件与软件管理的缩放、精度选择结合。E4M3 与 E5M2 对应不同数值需求，因此，没有格式与精度条件的吞吐量是不完整的。Hopper 还为动态规划增加 DPX 指令，并强化机密计算支持。这些能力扩展了 GPU 的负载和部署范围，不能将 Hopper 仅描述为 LLM 芯片。H100 的第四代 NVLink 提供 900 GB/s 双向聚合带宽，即单方向 450 GB/s；八 GPU 的 HGX 互联仍是独立于外部网络的一层资源。" ], "sources": [ "P04", "P13", "P18", "P33" ] }, { "id": "07.h200", "type": "prose", "text": [ "H200 retains Hopper computation and replaces the memory balance: 141 GB HBM3e at 4.8 TB/s, compared with H100 SXM’s 80 GB at 3.35 TB/s. Capacity rises by about 1.76× and bandwidth by about 1.43×, while the selected dense BF16 peak is unchanged. This is particularly useful when inference is limited by weights or KV-cache traffic rather than arithmetic. It also changes how many devices a model needs simply to fit, potentially reducing communication. GH200 is a different product construction: a Grace CPU coherently attached to a Hopper GPU, with its own HBM configurations. H200’s 141 GB must not be copied onto every GH200.", "H200 保留 Hopper 计算结构，但重新平衡内存：141 GB HBM3e、4.8 TB/s，而 H100 SXM 为 80 GB、3.35 TB/s。容量约增至 1.76 倍，带宽约增至 1.43 倍，所选稠密 BF16 峰值不变。这对于受权重或 KV 缓存流量限制、而非受算术限制的推理尤为有价值。它还可能减少仅为容纳模型所需的设备数，从而降低通信。GH200 是另一种产品构造：Grace CPU 与 Hopper GPU 通过一致性互联相连，并具有自己的 HBM 配置。不能将 H200 的 141 GB 套用到所有 GH200。" ], "sources": [ "P13", "P14", "P08" ] } ] }, { "id": "08", "title": [ "Blackwell and Ultra: crossing die and rack boundaries", "Blackwell 与 Ultra：跨越裸片与机架边界" ], "blocks": [ { "id": "08.dies", "type": "prose", "text": [ "Blackwell combines two large compute dies through a 10 TB/s NV-HBI connection and presents them as one CUDA GPU. That boundary is fundamentally different from connecting two separate GPUs with NVLink. The on-package fabric must support the internal behavior of one processor, including the interaction between compute and the distributed memory hierarchy. The approximately 208-billion-transistor design uses TSMC 4NP. Packaging makes the larger logical processor possible, but does not make die-to-die traffic free: locality, buffering, power and physical routing remain architectural costs.", "Blackwell 通过 10 TB/s 的 NV-HBI 连接两颗大型计算裸片，并向 CUDA 呈现为一个 GPU。这与通过 NVLink 连接两个独立 GPU 有本质区别。封装内互联必须支撑单个处理器的内部行为，包括计算与分布式内存层次之间的交互。该设计约有 2080 亿晶体管，采用 TSMC 4NP。封装技术使更大的逻辑处理器成为可能，但裸片间通信并非没有成本：局部性、缓冲、功耗与物理布线仍是架构代价。" ], "sources": [ "P05", "C11", "P32" ] }, { "id": "08.tensor", "type": "prose", "text": [ "Fifth-generation Tensor Cores extend low-precision execution to FP4 and FP6, with fine-grained scaling. NVFP4 uses block scaling plus a tensor-level scale to improve the usable numerical range of four-bit values. Tensor Memory supplies storage associated with tensor execution, reducing pressure on the conventional register path; two-SM cooperation changes how matrix work is distributed. These features require compiler, kernel and quantization support. A model’s quality and latency target, not just supported bit width, determines whether FP4 is the right operating point.", "第五代 Tensor Core 通过细粒度缩放，将低精度执行扩展到 FP4 和 FP6。NVFP4 将分块缩放与张量级缩放结合，改善四位数值的可用数值范围。Tensor Memory 为张量执行提供专用存储，缓解常规寄存器路径的压力；两个 SM 的协同改变矩阵工作的分配方式。这些特性需要编译器、内核与量化软件配合。是否采用 FP4，取决于模型质量与延迟目标，而不只是硬件支持多少位。" ], "sources": [ "P06", "P32" ] }, { "id": "08.rack", "type": "prose", "text": [ "GB200 places Grace alongside two Blackwell GPUs, and NVL72 connects 72 GPU packages into a rack-scale NVLink domain. GB300 upgrades that construction with Blackwell Ultra. The rack is not simply nine unrelated eight-GPU servers: communication topology, cooling, serviceability, power and scheduling are co-designed around a larger domain. Conversely, an NVL72 does not imply a uniform-latency 72-GPU memory pool. Software still decides tensor, pipeline, expert and data parallel placement, and crossing the rack boundary invokes a different fabric and congestion regime.", "GB200 将 Grace 与两颗 Blackwell GPU 组合，NVL72 则将 72 个 GPU 封装连接为机架级 NVLink 域。GB300 用 Blackwell Ultra 升级这一构造。机架并非九台互不相关的八 GPU 服务器：通信拓扑、散热、维护、供电与调度围绕更大的域协同设计。另一方面，NVL72 也不等于具有统一延迟的 72 GPU 内存池。软件仍需决定张量、流水线、专家与数据并行的放置，跨机架通信则进入另一种互联与拥塞环境。" ], "sources": [ "P05", "P06", "P18", "P27", "E15", "E16" ] }, { "id": "08.ultra", "type": "prose", "text": [ "Ultra increases memory capacity and dense FP4 capability, but it is not a uniform multiplier across every datapath. The HGX comparison gives B300 much less native FP64 throughput than B200. That matters for mixed AI/HPC procurement and for numerical algorithms that cannot replace native FP64 with emulation. Cloud adoption also demonstrates configuration diversity: AWS P6e GB200 combines the GPU scale-up domain with EFA, while other deployments use NVIDIA networking. The GPU vendor’s reference platform is therefore an important baseline, not a universal description of every hyperscaler installation.", "Ultra 提高内存容量和稠密 FP4 能力，但并不是每条数据通路都按同一比例提升。HGX 对比中，B300 的原生 FP64 吞吐量显著低于 B200。这对混合 AI／HPC 采购，以及不能用模拟计算替代原生 FP64 的数值算法非常重要。云端部署也体现出配置差异：AWS P6e GB200 将 GPU 纵向扩展域与 EFA 结合，其他部署则使用 NVIDIA 网络。因此，GPU 厂商的参考平台是重要基线，而不是所有超大规模云部署的通用描述。" ], "sources": [ "P37", "E16", "E14", "E15" ] } ] }, { "id": "09", "title": [ "Rubin: a platform generation, with configuration-specific limits", "Rubin：平台代际与配置约束" ], "blocks": [ { "id": "09.platform", "type": "prose", "text": [ "Rubin couples a new GPU generation to Vera, NVLink 6, ConnectX-9, BlueField-4 and Spectrum networking. The GPU moves to HBM4 and a larger tensor-compute budget; Vera changes the host CPU microarchitecture rather than merely raising Grace’s clock. This increases the importance of balanced supply: more tensor work needs more operand bandwidth, collective bandwidth and orchestration capacity. The platform also introduces explicit support for infrastructure-side context storage and complementary low-latency inference, rather than requiring every task to occupy the same kind of GPU resource.", "Rubin 将新 GPU 代际与 Vera、NVLink 6、ConnectX-9、BlueField-4 及 Spectrum 网络结合。GPU 转向 HBM4，并扩大张量计算预算；Vera 则改变主机 CPU 微架构，而非仅提高 Grace 频率。这使均衡供给更加重要：更多张量计算需要更多操作数带宽、集合通信带宽和调度能力。平台还明确支持基础设施侧上下文存储及互补的低延迟推理，而非要求所有任务占用同一种 GPU 资源。" ], "sources": [ "P07", "P10", "P11", "P12", "P20" ] }, { "id": "09.normalize", "type": "prose", "text": [ "Two published Rubin configurations must remain distinct. The chip-oriented HGX specification lists 288 GB HBM4 at 22 TB/s and 3.6 TB/s aggregate bidirectional NVLink. The NVL72 page, under its DSX/MaxLPS at-scale configuration, lists 19.2 TB/s HBM bandwidth and 3 TB/s bidirectional NVLink per GPU. It also reports 0.45 TB/s bidirectional scale-out bandwidth per GPU. These values are operating-point and system-scope disclosures, not interchangeable descriptions of one unconstrained chip. Power management can trade instantaneous peaks for higher useful throughput across an entire facility.", "已公布的两种 Rubin 配置必须分开。面向芯片的 HGX 规格列出 288 GB HBM4、22 TB/s 带宽和 3.6 TB/s 双向聚合 NVLink。NVL72 页面在采用 DSX／MaxLPS 的大规模配置下，列出单 GPU 的 HBM 带宽为 19.2 TB/s、双向 NVLink 为 3 TB/s；其单 GPU 双向横向扩展带宽为 0.45 TB/s。这些是不同工作点与系统范围的披露，不能互换为一颗无约束芯片的描述。功率管理可以牺牲瞬时峰值，换取整个设施更高的有效吞吐量。" ], "sources": [ "P37", "P38", "E11" ] }, { "id": "09.compute", "type": "prose", "text": [ "The arithmetic table also needs execution-mode labels. Published Rubin training figures include dense FP4 at 35 PFLOPS and dense FP8/FP6 at 17.5 PFLOPS; the 50 PFLOPS NVFP4 inference headline has a sparse basis. It is unsafe to derive a single dense number by halving every headline. Native FP64 at 33 TFLOPS and an emulated FP64 DGEMM rate of 200 TFLOPS describe different mechanisms. An HPC application must validate accuracy, conditioning and library behavior before using the emulated rate in a performance model.", "算力表同样需要标明执行模式。已公布的 Rubin 训练指标包括稠密 FP4 35 PFLOPS、稠密 FP8／FP6 17.5 PFLOPS；50 PFLOPS 的 NVFP4 推理标称值采用稀疏口径。不能将每个宣传值一律除以二，得到所谓统一稠密值。原生 FP64 的 33 TFLOPS 与模拟 FP64 DGEMM 的 200 TFLOPS 是不同机制。HPC 应用在把模拟速率纳入性能模型前，必须验证精度、问题条件性和库行为。" ], "sources": [ "P37", "P11" ] }, { "id": "09.timeline", "type": "prose", "text": [ "Hot Chips 2026 and the associated technical disclosures deepen the public architecture record. September 2026 MLPerf results are preview submissions, including a partner submission, and demonstrate working systems rather than a universal GA date. Rubin CPX remains a separately announced long-context branch in the evidence reviewed here: its original 2025 disclosure described GDDR7 and a late-2026 target, but this report does not infer final configuration or cancellation from later omission. Rubin Ultra and Feynman belong in the roadmap, not in shipping specification comparisons.", "Hot Chips 2026 及相关技术披露深化了公开架构记录。2026 年 9 月的 MLPerf 结果属于预览提交，其中包括合作伙伴提交；它们证明系统已经运行，却不代表统一的正式商用日期。在本报告审阅的证据中，Rubin CPX 仍是独立发布的长上下文分支：2025 年最初披露采用 GDDR7，并计划在 2026 年末推出；报告不会依据后续材料未提及它，就推断最终配置或取消。Rubin Ultra 与 Feynman 属于路线图，不进入已商用规格比较。" ], "sources": [ "C07", "E08", "E04", "E03" ] } ] }, { "id": "10", "title": [ "Grace and Vera CPUs: the host becomes architectural", "Grace 与 Vera CPU：主机进入协同架构" ], "blocks": [ { "id": "cpu", "type": "table", "table": "cpu" }, { "id": "10.grace", "type": "prose", "text": [ "Grace’s value is the CPU memory system and its connection to the accelerator. Seventy-two Neoverse V2 cores share a mesh and a large system cache, while LPDDR5X supplies high bandwidth with a different power and serviceability trade-off from conventional DIMMs. A two-CPU Grace Superchip doubles the cores and memory resources; GH200 instead couples Grace to Hopper. Coherent C2C allows fine-grained CPU–GPU sharing and access to a larger memory capacity without treating every transfer as an explicit bulk copy. Remote CPU memory remains slower for the GPU than local HBM, so coherence simplifies programming without erasing locality.", "Grace 的价值在于 CPU 内存系统及其与加速器的连接。72 个 Neoverse V2 核心共享网格互联和较大的系统缓存；LPDDR5X 以不同于传统 DIMM 的功耗与维护取舍提供高带宽。双 CPU Grace Superchip 将核心和内存资源翻倍，GH200 则将 Grace 与 Hopper 组合。一致性 C2C 支持细粒度 CPU–GPU 共享，以及对更大内存容量的访问，无需把每次传输都处理成显式的大块拷贝。但对 GPU 而言，远端 CPU 内存仍慢于本地 HBM，因此一致性简化了编程，却没有消除局部性。" ], "sources": [ "P08", "P09" ] }, { "id": "10.circuit", "type": "prose", "text": [ "ISSCC 2023’s NVLink-C2C disclosure makes this connection unusually concrete. It describes a 40 Gb/s-per-pin, single-ended off-package coherent interface, including a 5 nm PHY and clocking/skew techniques. Ten links support the disclosed 900 GB/s bidirectional interface. The older ISSCC 2018 ground-referenced-signaling research is relevant circuit lineage, but its 25 Gb/s-per-pin test vehicle is not the production Grace interface. This is precisely where conference synthesis is valuable: Hot Chips explains the memory-system purpose, while ISSCC reveals how an electrically demanding package boundary is implemented.", "ISSCC 2023 的 NVLink-C2C 披露为这一连接提供了具体实现证据：每引脚 40 Gb/s 的单端、跨封装一致性接口，包括 5 nm PHY 以及时钟与偏斜处理技术。十条链路支撑所披露的 900 GB/s 双向接口。ISSCC 2018 的地参考信号研究与其电路技术演进相关，但其每引脚 25 Gb/s 的测试载体并不是 Grace 的量产接口。会议综合的价值正在于此：Hot Chips 解释内存系统目的，ISSCC 则揭示如何实现电气要求很高的封装边界。" ], "sources": [ "C09", "R07", "P08" ] }, { "id": "10.vera", "type": "prose", "text": [ "Vera replaces licensed Neoverse cores with NVIDIA’s Olympus design. Its 88 cores expose 176 spatial threads, with a ten-wide front end, advanced prediction, memory renaming, value prediction and graph-oriented prefetching among the disclosed mechanisms. The architecture is aimed at host-side work that cannot simply be pushed into a large matrix operation: orchestration, irregular access, graph traversal and agent execution. Public descriptions do not establish every queue size or execution latency, so those are not reverse-engineered from marketing comparisons.", "Vera 用 NVIDIA 自研 Olympus 取代授权的 Neoverse 核心。88 个核心提供 176 个空间线程；已披露机制包括十宽前端、先进预测、内存重命名、值预测及面向图的预取。该架构面向无法简单转换为大型矩阵运算的主机侧工作，例如调度、不规则访问、图遍历和智能体执行。公开资料未确定所有队列规模或执行延迟，因此报告不从营销对比中反推这些数值。" ], "sources": [ "P10", "C07" ] }, { "id": "10.memory", "type": "prose", "text": [ "Vera’s memory changes are equally consequential: up to 1.5 TB of replaceable SOCAMM2 LPDDR5X at 1.2 TB/s, larger private and shared caches, and twice Grace’s C2C bidirectional rate. Using peak specifications, memory bandwidth per core rises from roughly 7.1 to 13.6 GB/s. Spatial threading does not double the memory system, so per-thread bandwidth is a different ratio. CXL 3.1 and Arm confidential-computing mechanisms broaden deployment options. The key trajectory is from a high-bandwidth accelerator companion to a CPU designed as a first-class component of the AI serving system.", "Vera 的内存变化同样重要：采用可更换的 SOCAMM2 LPDDR5X，最高 1.5 TB、1.2 TB/s，扩大私有与共享缓存，并将 C2C 双向速率提升到 Grace 的两倍。按峰值规格计算，每核内存带宽从约 7.1 提高到 13.6 GB/s。空间线程并未将内存系统翻倍，因此每线程带宽是另一种比例。CXL 3.1 与 Arm 机密计算机制扩展了部署选择。整体轨迹是从高带宽的加速器伴随处理器，走向作为 AI 服务系统核心组成部分而设计的 CPU。" ], "sources": [ "P09", "P10", "P11" ] } ] }, { "id": "11", "title": [ "Inference, workstation and edge branches", "推理、工作站与边缘分支" ], "blocks": [ { "id": "derivatives", "type": "table", "table": "derivatives" }, { "id": "11.meaning", "type": "prose", "text": [ "These branches share programming tools and selected architectural mechanisms with datacenter accelerators, but optimize different constraints. GDDR-based cards can fit existing air-cooled servers and serve graphics, media and inference together. HBM-based GPUs prioritize bandwidth and large-scale compute fabrics. GB10 instead uses a coherent unified LPDDR memory system: its 128 GB capacity can be attractive for local model development, but 273 GB/s is far below a flagship HBM GPU’s bandwidth. Its one-PFLOPS FP4 headline should not be read as a one-PFLOPS dense training guarantee. The 240 W power supply rating is also not the 140 W SoC TDP.", "这些分支与数据中心加速器共享编程工具和部分架构机制，但优化的约束不同。采用 GDDR 的板卡可以适配既有风冷服务器，同时承载图形、媒体和推理。采用 HBM 的 GPU 则侧重带宽与大规模计算互联。GB10 使用具有缓存一致性的统一 LPDDR 内存系统：128 GB 容量有利于本地模型开发，但 273 GB/s 远低于旗舰 HBM GPU 带宽。其 1 PFLOPS FP4 标称值不应被理解为稠密训练保证值。240 W 电源额定功率也不等于 140 W SoC TDP。" ], "sources": [ "P29", "P30", "P31", "P46" ] } ] }, { "id": "12", "title": [ "NVLink, NVSwitch and coherent C2C", "NVLink、NVSwitch 与一致性 C2C" ], "blocks": [ { "id": "interconnect", "type": "table", "table": "interconnect" }, { "id": "12.fusion", "type": "prose", "text": [ "NVLink Fusion opens selected NVLink system integration paths to custom CPUs and accelerators. It should be understood as an integration and ecosystem program, not as proof that every participating chip implements the same coherence semantics as Grace–Hopper. A custom processor must still satisfy interface, switch, software and platform requirements. This matters strategically because the scale-up fabric can remain NVIDIA-centered even when one compute component is supplied by another vendor. It does not mean Ethernet or InfiniBand disappear; those still serve scale-out and infrastructure roles.", "NVLink Fusion 向定制 CPU 和加速器开放部分 NVLink 系统集成路径。应将其理解为集成与生态计划，而不是所有参与芯片都实现 Grace–Hopper 相同一致性语义的证据。定制处理器仍需满足接口、交换、软件与平台要求。其系统意义在于，即使某个计算组件由其他厂商提供，纵向扩展网络仍可能以 NVIDIA 为中心。这不意味着以太网或 InfiniBand 消失；它们仍承担横向扩展与基础设施任务。" ], "sources": [ "P27", "E13" ] } ] }, { "id": "13", "title": [ "ConnectX and BlueField: endpoints and infrastructure", "ConnectX 与 BlueField：端点与基础设施" ], "blocks": [ { "id": "13.roles", "type": "prose", "text": [ "NVIDIA’s 2020 acquisition of Mellanox brought a mature network endpoint, switch and software portfolio into the compute platform. Three roles should remain separate. A ConnectX adapter is an efficient network endpoint with transport and offload engines. A SuperNIC is an AI-networking product role focused on the GPU back-end fabric; it does not automatically mean a general-purpose host CPU replacement. A BlueField DPU adds independently managed CPU and infrastructure processing for networking, storage and security. NVLink remains the separate scale-up fabric. Conflating these roles hides both trust boundaries and bandwidth bottlenecks.", "NVIDIA 在 2020 年完成对 Mellanox 的收购，将成熟的网络端点、交换与软件产品纳入计算平台。应区分三种角色：ConnectX 网卡是带有传输与卸载引擎的高效网络端点；SuperNIC 是面向 GPU 后端互联的 AI 网络产品角色，并不自动意味着可替代通用主机 CPU；BlueField DPU 则加入可独立管理的 CPU 与基础设施处理能力，承担网络、存储和安全任务。NVLink 仍是另一层纵向扩展网络。混淆这些角色会掩盖信任边界和带宽瓶颈。" ], "sources": [ "E05", "P19", "P20", "P22", "P24", "P25" ] }, { "id": "network", "type": "table", "table": "network" }, { "id": "13.nic", "type": "prose", "text": [ "The ConnectX trajectory follows both network SerDes and the host interface. Moving from 100 to 200, 400 and 800 Gb/s requires sufficient PCIe bandwidth and suitable server wiring. Socket Direct can split connectivity across two CPU roots; an advertised aggregate port rate does not guarantee that a single older PCIe link can sustain it. ConnectX-8’s integrated PCIe Gen6 switch is therefore a system feature, not just a faster MAC: it changes GPU-to-NIC attachment and permits high-bandwidth local paths without assuming every CPU root complex has the newest PCIe generation.", "ConnectX 的演进同时受网络 SerDes 与主机接口影响。从 100 提升到 200、400 和 800 Gb/s，需要足够的 PCIe 带宽及合适的服务器布线。Socket Direct 可以把连接分配到两个 CPU 根端；宣传的聚合端口速率并不保证单条较旧 PCIe 链路能够持续承载。因此，ConnectX-8 集成 PCIe Gen6 交换机是一项系统特性，而不仅是更快的 MAC：它改变 GPU 到 NIC 的连接方式，在不要求所有 CPU 根端都采用最新 PCIe 代际的条件下，提供高带宽本地路径。" ], "sources": [ "P49", "P50", "P19", "P21" ] }, { "id": "13.dpu", "type": "prose", "text": [ "BlueField evolves from an Arm-plus-ConnectX storage/network processor into a separately managed infrastructure subsystem. BlueField-3 adds a programmable data-path accelerator alongside Arm control cores and fixed-function packet engines. The Arm cores should not be assumed to forward every packet in software at line rate. BlueField-4 combines Grace-class CPU resources with ConnectX-9 and targets infrastructure services, including storage for AI context. Moving KV-cache or context data outside GPU HBM can improve capacity economics, but introduces a hierarchy: storage/network bandwidth and access granularity must match the serving scheduler’s decisions.", "BlueField 从 Arm 与 ConnectX 结合的存储／网络处理器，演进为可独立管理的基础设施子系统。BlueField-3 在 Arm 控制核心与固定功能报文引擎旁加入可编程数据路径加速器。不能假设 Arm 核心通过软件以线速转发每个报文。BlueField-4 将 Grace 级 CPU 资源与 ConnectX-9 结合，面向包括 AI 上下文存储在内的基础设施服务。把 KV 缓存或上下文移出 GPU HBM 可能改善容量成本，但同时引入新的层次：存储／网络带宽和访问粒度必须与服务调度器的决策匹配。" ], "sources": [ "P24", "P20", "P11" ] } ] }, { "id": "14", "title": [ "Spectrum, Quantum and photonics", "Spectrum、Quantum 与光互联" ], "blocks": [ { "id": "switch", "type": "table", "table": "switch" }, { "id": "14.ethernet", "type": "prose", "text": [ "Spectrum-X is a coordinated Ethernet platform rather than a switch ASIC renamed for AI. Its value comes from the interaction of adaptive packet routing, endpoint congestion response, telemetry, ordering support and collective software. Multiplane designs distribute traffic across parallel network planes and use endpoint intelligence to avoid hotspots. These mechanisms address the synchronized bursts and all-to-all exchanges common in distributed training and mixture-of-experts inference. A nominally nonblocking topology can still perform poorly if congestion control reacts too slowly or tenant traffic interferes.", "Spectrum-X 是协同设计的以太网平台，而不是给交换 ASIC 加上 AI 名称。其价值来自自适应报文路由、端点拥塞响应、遥测、顺序处理支持与集合通信软件之间的配合。多平面设计将流量分散到并行网络平面，并利用端点智能避免热点。这些机制针对分布式训练和混合专家推理中常见的同步突发与全互联交换。即使拓扑在标称上无阻塞，如果拥塞控制响应过慢或租户流量相互干扰，性能仍可能较差。" ], "sources": [ "P39", "E09" ] }, { "id": "14.ib", "type": "prose", "text": [ "Quantum serves the InfiniBand branch, with a transport and management model designed for tightly coupled clusters. SHARP moves selected collective reduction work into the network; it does not execute arbitrary GPU kernels inside the switch. Comparing Quantum with Spectrum therefore requires matching the collective, topology, software and operational model, not only port speed. Quantum-2 illustrates a common accounting trap: 64 ports at 400 Gb/s are 25.6 Tb/s in one direction; a 51.2 Tb/s full-duplex total is not twice the one-way switching capacity.", "Quantum 对应 InfiniBand 分支，其传输与管理模型面向紧密耦合的集群。SHARP 将部分集合归约操作移入网络，而不是在交换机内执行任意 GPU 内核。因此，比较 Quantum 与 Spectrum 必须匹配集合通信、拓扑、软件及运维模型，不能只比较端口速度。Quantum-2 展示了常见统计陷阱：64 个 400 Gb/s 端口的单方向总量为 25.6 Tb/s；51.2 Tb/s 的全双工总值，并不代表单方向交换能力翻倍。" ], "sources": [ "P40", "P44" ] }, { "id": "14.optics", "type": "prose", "text": [ "Co-packaged optics shortens the electrical path between switch silicon and optical conversion. The expected system benefit is lower electrical I/O power and improved reach at very high aggregate bandwidth, but it changes packaging, laser supply, fiber attachment, repair and qualification requirements. A photonic switch assembly may contain multiple switching elements; its aggregate capacity must not be assigned to one ASIC. ISSCC optical-link research and product CPO disclosures belong in the same technology map, but a research test chip is not proof of the exact production optical implementation.", "共封装光学缩短交换芯片与光电转换之间的电气路径。在极高聚合带宽下，其系统目标是降低电气 I/O 功耗并改善传输距离，但也改变了封装、激光源、光纤连接、维修与认证要求。光子交换组件可能包含多个交换单元，不能把组件总容量归给单颗 ASIC。ISSCC 光链路研究与产品 CPO 披露属于同一技术图谱，但研究测试芯片不能证明量产光学实现与其完全相同。" ], "sources": [ "P23", "R08", "C06" ] } ] }, { "id": "15", "title": [ "Groq 3 LPX and specialized inference", "Groq 3 LPX 与专用推理" ], "blocks": [ { "id": "15.license", "type": "prose", "text": [ "The 2025 agreement between Groq and NVIDIA is a non-exclusive inference-technology licensing agreement, not an acquisition of Groq as a company. Groq 3 LPX subsequently appears as a complementary NVIDIA inference platform, with production disclosed in August 2026. This changes the portfolio map: NVIDIA does not need a merchant FPGA line to have a non-GPU inference architecture. The correct comparison is between execution and memory organizations, not merely between two vendors’ TOPS figures.", "Groq 与 NVIDIA 在 2025 年达成的是非独家推理技术许可协议，而不是 NVIDIA 收购 Groq 公司。随后，Groq 3 LPX 作为 NVIDIA 的互补推理平台出现，并在 2026 年 8 月披露量产。这改变了产品组合图谱：NVIDIA 无需拥有通用 FPGA 产品线，也可以拥有非 GPU 推理架构。正确比较对象是执行与内存组织方式，而不只是两家厂商的 TOPS 数字。" ], "sources": [ "E06", "P12", "E09" ] }, { "id": "15.arch", "type": "prose", "text": [ "LPX organizes computation around compiler-scheduled execution and substantial on-chip SRAM. The disclosed LP30 LPU has approximately 500 MB SRAM and 150 TB/s local SRAM bandwidth; a 256-LPU rack aggregates 128 GB SRAM and about 40 PB/s of local bandwidth. Those sums are not a uniform 128 GB cache with 40 PB/s available to any one operator. The compiler must place and stream model state across devices and their interconnect. Small, predictable working sets can exploit low-latency local access; large models still confront distributed capacity and communication constraints.", "LPX 围绕编译器调度的执行和大量片上 SRAM 组织计算。披露的 LP30 LPU 约有 500 MB SRAM 和 150 TB/s 本地 SRAM 带宽；256 LPU 机架聚合为 128 GB SRAM、约 40 PB/s 本地带宽。但这些总和不是任意算子都能以 40 PB/s 访问的统一 128 GB 缓存。编译器必须在设备及其互联之间放置、流送模型状态。小而可预测的工作集能够利用低延迟本地访问；大模型仍受分布式容量与通信约束。" ], "sources": [ "P12" ] }, { "id": "15.balance", "type": "prose", "text": [ "The architectural attraction is heterogeneous serving. HBM GPUs offer large capacity and flexible computation; SRAM-centric LPUs offer a different latency/bandwidth operating point. A serving system can place suitable work on each, but the split must account for transfer costs, batching, KV-cache location and end-to-end latency. It is not enough for one feed-forward stage to become faster if the interface or another stage becomes the critical path. LPX therefore belongs beside the GPU and DPU chapters as a complementary execution tier, not inside a table pretending it is another CUDA GPU.", "其架构吸引力在于异构服务。HBM GPU 提供较大容量和灵活计算，SRAM 型 LPU 则提供另一种延迟／带宽工作点。服务系统可以将合适的工作分配给两者，但划分必须考虑传输成本、批处理、KV 缓存位置和端到端延迟。如果接口或其他阶段成为关键路径，仅让某个前馈阶段更快并不足够。因此，LPX 应作为互补执行层，与 GPU 和 DPU 并列讨论，而不应被放进一张将其假装成另一款 CUDA GPU 的表格。" ], "sources": [ "P12", "E17" ] } ] }, { "id": "16", "title": [ "Integrated systems and the bandwidth hierarchy", "集成系统与带宽层次" ], "blocks": [ { "id": "systems", "type": "table", "table": "systems" }, { "id": "16.platforms", "type": "prose", "text": [ "DGX is an integrated system product; HGX is a GPU baseboard/platform building block; MGX is a modular server and rack design ecosystem; NVL describes an NVLink-centered system configuration. These labels should not be used interchangeably. OEMs can vary CPU, network, storage, cooling and power around common GPU building blocks. Rack power also includes CPUs, switches, fans or pumps, memory and conversion losses, so multiplying GPU TDP by GPU count is not a rack-power specification. Power-limited operating points further break that shortcut.", "DGX 是集成系统产品；HGX 是 GPU 基板／平台构件；MGX 是模块化服务器与机架设计生态；NVL 描述以 NVLink 为中心的系统配置。这些名称不能互换。OEM 可以围绕相同 GPU 构件改变 CPU、网络、存储、散热与供电。机架功耗还包括 CPU、交换机、风扇或水泵、内存及电源转换损耗，因此 GPU TDP 乘以数量并不是机架功耗规格。受功率限制的工作点进一步使这一捷径失效。" ], "sources": [ "P16", "P17", "P27", "P38", "E12" ] }, { "id": "fig.early", "type": "figure", "figure": "fig.early" }, { "id": "fig.hopper", "type": "figure", "figure": "fig.hopper" }, { "id": "fig.blackwell", "type": "figure", "figure": "fig.blackwell" }, { "id": "fig.rubin", "type": "figure", "figure": "fig.rubin" }, { "id": "ratios", "type": "table", "table": "ratios" }, { "id": "16.roofline", "type": "prose", "text": [ "These ratios expose the hierarchy without predicting application speed. A kernel’s roofline is the minimum of compute throughput and operational intensity times the relevant memory bandwidth. Distributed execution adds communication and synchronization ceilings. Moving from HBM to peer GPU memory, CPU memory, network-attached context storage or LPX SRAM changes both the bandwidth and the ownership of data. The architectural task is to place reuse at the cheapest sufficiently large tier, not to add the advertised bandwidths together.", "这些比例揭示层次关系，但不直接预测应用速度。内核的 Roofline 上限由计算吞吐量与“运算强度乘以相关内存带宽”两者的较小值决定；分布式执行还受到通信与同步上限约束。从 HBM 转向对等 GPU 内存、CPU 内存、网络上下文存储或 LPX SRAM，会同时改变带宽与数据归属。架构任务是把数据复用放在成本最低且容量足够的层次，而不是把各层宣传带宽相加。" ], "sources": [ "P08", "P12", "P20", "P38" ] } ] }, { "id": "17", "title": [ "Software makes the hardware hierarchy usable", "软件将硬件层次变为可用能力" ], "blocks": [ { "id": "software", "type": "table", "table": "software" }, { "id": "17.layers", "type": "prose", "text": [ "CUDA provides the execution and memory model, while cuBLAS, cuDNN, CUTLASS and related libraries turn architectural features into optimized kernels. TensorRT and TensorRT-LLM specialize inference execution; NCCL coordinates collectives across the actual topology. These layers are not interchangeable. A Tensor Core format can exist in silicon before every framework or model uses it well. Likewise, a new network adapter does not automatically accelerate a collective unless the transport, topology discovery and algorithm can exploit it.", "CUDA 提供执行与内存模型，cuBLAS、cuDNN、CUTLASS 等库将架构特性转化为优化内核。TensorRT 与 TensorRT-LLM 专门优化推理执行，NCCL 则针对实际拓扑协调集合通信。这些层次不能互换。某种 Tensor Core 格式可以先存在于芯片中，而框架或模型尚未充分利用它。同样，新网卡不会自动加速集合通信，传输机制、拓扑发现与算法必须能够利用其能力。" ], "sources": [ "P32", "P33", "P34", "P44", "E17" ] }, { "id": "17.serving", "type": "prose", "text": [ "Dynamo reflects the shift from optimizing one model invocation to managing a distributed serving pipeline. Prefill, decode, expert placement and KV-cache movement have different resource profiles. Separating them can improve utilization, but also creates network traffic and scheduling dependencies. BlueField context storage and LPX introduce more placement choices, making the scheduler part of the architecture. Performance comparisons should therefore fix model, precision, quality target, input/output length, batching and latency objective before attributing gains to a new GPU generation.", "Dynamo 体现了优化对象从单次模型调用转向分布式服务流水线。预填充、解码、专家放置和 KV 缓存搬移具有不同资源特征。分离这些工作可能提高利用率，但也产生网络流量和调度依赖。BlueField 上下文存储与 LPX 增加了放置选择，使调度器成为架构的一部分。因此，在将性能收益归因于新 GPU 代际之前，应固定模型、精度、质量目标、输入／输出长度、批处理方式与延迟目标。" ], "sources": [ "E17", "E08", "P12", "P20" ] } ] }, { "id": "18", "title": [ "What the architecture conferences actually establish", "架构会议究竟证明了什么" ], "blocks": [ { "id": "18.research", "type": "prose", "text": [ "ISCA 2017’s MCM-GPU explores how several GPU modules could behave as a scalable logical accelerator and why inter-module locality matters. MICRO 2017’s Beyond the Socket studies NUMA-aware GPUs; Fine-Grained DRAM studies energy-efficient memory organization. HPCA 2015 and ASPLOS 2015 examine bandwidth and page placement in heterogeneous coherent-memory systems. These papers explain persistent design pressures visible later in Blackwell and Grace: packaging boundaries, nonuniform bandwidth, placement and locality. They do not establish that a later commercial product implements the paper’s exact mechanism.", "ISCA 2017 的 MCM-GPU 研究多个 GPU 模块如何组成可扩展的逻辑加速器，以及模块间局部性为何重要。MICRO 2017 的 Beyond the Socket 研究 NUMA 感知 GPU，Fine-Grained DRAM 研究高能效内存组织。HPCA 2015 与 ASPLOS 2015 探讨异构一致性内存系统中的带宽和页面放置。这些论文解释了后来在 Blackwell 与 Grace 中仍可见的设计压力：封装边界、非均匀带宽、放置与局部性。但它们不能证明后续商业产品实现了论文中的同一机制。" ], "sources": [ "R01", "R02", "R03", "R04", "R05" ] }, { "id": "18.simba", "type": "prose", "text": [ "MICRO 2019’s Simba is especially useful as a counterpoint to the general-purpose GPU: it studies a multi-chip inference accelerator with distributed local storage and a deliberately structured communication hierarchy. Its circuit implementation was disclosed at VLSI and in journal work; it should not be mislabeled an ISSCC 2019 GPU product paper. COPA-GPU, published in the ACM TACO line, explores composing different memory and compute organizations for different domains. Both broaden the design-space discussion without serving as a hidden specification for Blackwell or LPX.", "MICRO 2019 的 Simba 是理解通用 GPU 之外设计空间的重要参照：它研究多芯片推理加速器，采用分布式本地存储及明确组织的通信层次。其电路实现通过 VLSI 和期刊工作披露，不应误标为 ISSCC 2019 的 GPU 产品论文。发表于 ACM TACO 系列的 COPA-GPU 探讨针对不同领域组合不同内存与计算组织。二者扩展了设计空间讨论，但不是 Blackwell 或 LPX 的隐含规格说明。" ], "sources": [ "R10", "R06" ] }, { "id": "18.direct", "type": "prose", "text": [ "Direct product linkage is strongest where the source explicitly names it. ISSCC’s A100 and NVLink-C2C disclosures are implementation evidence for those products. NVIDIA’s account of PrefixRL states that Hopper includes thousands of arithmetic circuits designed using the method; that supports a concrete design-tool adoption claim, not the statement that the whole GPU was designed by AI. Hot Chips 2026 names Vera, Rubin, BlueField-4 and LPU presentations, but a program entry proves that a talk occurred, not that every slide or undisclosed microarchitectural detail was publicly inspected.", "来源明确点名产品时，产品关联证据最强。ISSCC 的 A100 与 NVLink-C2C 披露是相应产品的实现证据。NVIDIA 对 PrefixRL 的介绍称，Hopper 包含数千个利用该方法设计的算术电路；这支持具体设计工具已被采用的说法，而不是“整个 GPU 由 AI 设计”。Hot Chips 2026 列出了 Vera、Rubin、BlueField-4 和 LPU 演讲，但会议程序只能证明演讲安排与发生，不能证明所有幻灯片或未公开微架构细节都已被审阅。" ], "sources": [ "C08", "C09", "P41", "C07" ] } ] }, { "id": "19", "title": [ "Conference-to-product index", "会议—产品索引" ], "blocks": [ { "id": "venues", "type": "table", "table": "venues" } ] }, { "id": "20", "title": [ "Cross-generation conclusions and open disclosures", "跨代结论与尚未披露事项" ], "blocks": [ { "id": "20.conclusions", "type": "prose", "text": [ "The central trend is specialization inside a programmable system, not a simple replacement of programmability by fixed function. Tensor Cores specialize arithmetic; TMA specializes data movement; NVSwitch specializes scale-up communication; SHARP specializes selected reductions; BlueField specializes infrastructure; LPX specializes a different inference execution regime. CUDA and the serving stack bind these resources together. The system becomes more capable, but also more dependent on placement, numerical choices and coordinated software.", "核心趋势是在可编程系统内部进行专用化，而不是简单用固定功能替代可编程性。Tensor Core 专用化算术，TMA 专用化数据搬移，NVSwitch 专用化纵向扩展通信，SHARP 专用化部分归约，BlueField 专用化基础设施，LPX 则专用化另一种推理执行方式。CUDA 与服务软件栈将这些资源连接起来。系统能力增强的同时，也更加依赖数据放置、数值选择和软件协同。" ], "sources": [ "P03", "P04", "P18", "P40", "P20", "P12", "E17" ] }, { "id": "20.constraints", "type": "prose", "text": [ "The durable engineering constraints are clear. HBM capacity and bandwidth determine model fit and reuse. Die-to-die interfaces let the processor grow but impose locality costs. Rack-scale fabrics reduce some communication penalties while raising power, cooling and serviceability demands. Faster network line rates require host-interface bandwidth and congestion control. Coherent CPU memory and external context stores expand capacity without becoming substitutes for local HBM performance. Each generation moves these boundaries; none abolishes them.", "长期工程约束十分清晰。HBM 容量与带宽决定模型能否容纳及数据复用。裸片间接口允许处理器扩大，但引入局部性成本。机架级互联降低部分通信代价，同时提高供电、散热与维护要求。更高网络线速需要主机接口带宽和拥塞控制配合。一致性 CPU 内存与外部上下文存储扩展容量，却不能替代本地 HBM 性能。每代产品都在移动这些边界，而非消除它们。" ], "sources": [ "P01", "P08", "P19", "P20", "P38" ] }, { "id": "20.gaps", "type": "prose", "text": [ "Important public gaps remain: complete CPU queue and pipeline parameters; some enabled-unit counts and power points by Blackwell SKU; reconciled usable-memory accounting across DGX and HGX pages; final Rubin configuration and broad GA milestones; production optical implementation details; and the final commercial configuration of CPX. These gaps are concentrated here rather than repeated as confidence labels throughout the report. They should be closed with dated primary disclosures, not by averaging inconsistent specifications or importing rumor into a product table.", "公开资料仍存在重要缺口：完整 CPU 队列与流水线参数、部分 Blackwell SKU 的启用单元数量与功耗工作点、DGX 与 HGX 页面可用内存统计的统一解释、Rubin 最终配置与广泛正式商用里程碑、量产光学实现细节，以及 CPX 最终商业配置。报告将这些缺口集中列于此处，而不是在全文反复标注置信度。后续应通过有日期的一手披露补全，而非平均不一致的规格或把传闻写入产品表。" ], "sources": [ "P10", "P17", "P32", "P37", "P38", "E04", "E08", "P23" ] } ] }, { "id": "21", "title": [ "Codename crosswalk and source guide", "代号对照与来源指南" ], "blocks": [ { "id": "crosswalk", "type": "table", "table": "crosswalk" }, { "id": "21.sources", "type": "prose", "text": [ "Sources are grouped below into product documentation, conference records, research papers and event/deployment disclosures. The source map associates each report section with its evidence. The accompanying canonical data file preserves table-cell claims, basis, product scope, source IDs and dates for future updates. Conference programs and press kits are identified as such; this report does not imply access to paywalled papers or restricted recordings. Specifications are a snapshot at the cutoff, and live product pages may subsequently change.", "下列来源分为产品文档、会议记录、研究论文和活动／部署披露。来源映射将报告各章节与证据关联。配套规范数据文件保留表格单元格事实、口径、产品范围、来源编号与日期，便于后续更新。会议程序和新闻资料均按其实际类型标识；报告不暗示已访问付费论文或受限录像。规格是截止日期时的快照，在线产品页面此后可能变化。" ], "sources": [ "P37", "P38", "C08", "C09", "C10" ] } ] } ], "tables": { "headline": { "id": "headline", "title": [ "The main architecture transitions", "主要架构转折" ], "headers": [ [ "Era", "时期" ], [ "Flagship", "代表产品" ], [ "Architectural change", "架构变化" ], [ "System implication", "系统意义" ] ], "rows": [ { "id": "pascal", "values": [ [ "2015–2016", "2015–2016" ], [ "M40 → P100", "M40 → P100" ], [ "HBM2; NVLink 1", "HBM2；NVLink 1" ], [ "Move beyond host-mediated PCIe data movement", "减少依赖主机中转的 PCIe 数据搬移" ] ], "sources": [ "P01", "P42" ] }, { "id": "volta", "values": [ [ "2017–2019", "2017–2019" ], [ "V100 / DGX-2", "V100 / DGX-2" ], [ "Tensor Cores; NVSwitch", "Tensor Core；NVSwitch" ], [ "Matrix acceleration plus a switched GPU domain", "矩阵加速与交换式 GPU 域结合" ] ], "sources": [ "P02" ] }, { "id": "ampere", "values": [ [ "2020–2021", "2020–2021" ], [ "A100", "A100" ], [ "BF16 / TF32 / FP64 Tensor Cores; MIG", "BF16／TF32／FP64 Tensor Core；MIG" ], [ "One architecture serves AI, HPC and isolated instances", "同一架构覆盖 AI、HPC 和隔离实例" ] ], "sources": [ "P03", "C08" ] }, { "id": "hopper", "values": [ [ "2022–2024", "2022–2024" ], [ "H100 / H200 / GH200", "H100 / H200 / GH200" ], [ "FP8; TMA; clusters; coherent C2C", "FP8；TMA；线程块集群；一致性 C2C" ], [ "Hide movement and extend the memory hierarchy", "隐藏数据搬移开销并扩展内存层次" ] ], "sources": [ "P04", "P08", "P14" ] }, { "id": "blackwell", "values": [ [ "2024–2025", "2024–2025" ], [ "B200 / B300 / GB200 / GB300", "B200 / B300 / GB200 / GB300" ], [ "Two compute dies; FP4; NVL72", "双计算裸片；FP4；NVL72" ], [ "Package and rack become coordinated design units", "封装与机架成为协同设计单元" ] ], "sources": [ "P05", "P06", "P37" ] }, { "id": "rubin", "values": [ [ "2026", "2026" ], [ "Vera Rubin / BlueField-4 / LPX", "Vera Rubin / BlueField-4 / LPX" ], [ "HBM4; Olympus; NVLink 6; inference specialization", "HBM4；Olympus；NVLink 6；推理专用化" ], [ "Co-design across compute, fabric, storage and serving", "计算、互联、存储与服务调度协同设计" ] ], "sources": [ "P07", "P10", "P11", "P12", "E08", "E09" ] } ], "panels": [ [ 0, 1, 2, 3 ] ], "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources" }, "gpu": { "id": "gpu", "title": [ "Datacenter GPU generations: representative configurations", "数据中心 GPU 代际：代表性配置" ], "headers": [ [ "Generation", "代际" ], [ "Codename / architecture", "代号／架构" ], [ "GA / milestone", "商用／里程碑" ], [ "Status", "状态" ], [ "Process", "工艺" ], [ "Dies and packaging", "裸片与封装" ], [ "Compute units", "计算单元" ], [ "Dense BF16", "稠密 BF16" ], [ "Dense FP8", "稠密 FP8" ], [ "Dense FP6 / FP4", "稠密 FP6／FP4" ], [ "FP64 vector / matrix", "FP64 向量／矩阵" ], [ "HBM: generation; stacks; GB; TB/s", "HBM：代际；堆栈；GB；TB/s" ], [ "Last-level cache", "末级缓存" ], [ "Scale-up: links; GB/s one-way; domain", "纵向扩展：链路；单向 GB/s；域" ], [ "Host link", "主机连接" ], [ "TBP and cooling", "板级功耗与散热" ], [ "Form factor", "形态" ] ], "rows": [ { "id": "m40", "values": [ [ "M40", "M40" ], [ "GM200 / Maxwell", "GM200 / Maxwell" ], [ "2015", "2015" ], [ "Historical shipping", "历史已商用" ], [ "28 nm", "28 nm" ], [ "1 die; GDDR board", "单裸片；GDDR 板卡" ], [ "24 SM / 3072 CUDA", "24 SM / 3072 CUDA" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/d / n/a", "n/d / n/a" ], [ "n/a; GDDR5 24 GB; 0.288 TB/s", "n/a；GDDR5 24 GB；0.288 TB/s" ], [ "3 MB", "3 MB" ], [ "n/a", "n/a" ], [ "PCIe 3 x16", "PCIe 3 x16" ], [ "250 W; air", "250 W；风冷" ], [ "PCIe", "PCIe" ] ], "sources": [ "P42", "E18" ] }, { "id": "p100", "values": [ [ "P100 SXM2", "P100 SXM2" ], [ "GP100 / Pascal", "GP100 / Pascal" ], [ "2016", "2016" ], [ "Historical shipping", "历史已商用" ], [ "16 nm", "16 nm" ], [ "1 die + HBM interposer", "单裸片＋HBM 中介层" ], [ "56 SM / 3584 CUDA", "56 SM / 3584 CUDA" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "5.3 TF / n/a", "5.3 TF / n/a" ], [ "HBM2; 4; 16; 0.732", "HBM2; 4; 16; 0.732" ], [ "4 MB", "4 MB" ], [ "4; 80; server topology", "4；80；服务器拓扑" ], [ "PCIe 3", "PCIe 3" ], [ "300 W; platform-dependent", "300 W；依平台" ], [ "SXM2", "SXM2" ] ], "sources": [ "P01", "P36" ] }, { "id": "v100", "values": [ [ "V100 SXM2", "V100 SXM2" ], [ "GV100 / Volta", "GV100 / Volta" ], [ "2017", "2017" ], [ "Historical shipping", "历史已商用" ], [ "12 nm", "12 nm" ], [ "1 die + HBM interposer", "单裸片＋HBM 中介层" ], [ "80 SM / 640 TC", "80 SM / 640 TC" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "7.8 TF / n/a", "7.8 TF / n/a" ], [ "HBM2; 4; 16/32; 0.900", "HBM2; 4; 16/32; 0.900" ], [ "6 MB", "6 MB" ], [ "6; 150; up to 16 via NVSwitch", "6；150；NVSwitch 可连接 16 个 GPU" ], [ "PCIe 3", "PCIe 3" ], [ "300 W; platform-dependent", "300 W；依平台" ], [ "SXM2", "SXM2" ] ], "sources": [ "P02", "P35" ] }, { "id": "a100", "values": [ [ "A100 SXM 80 GB", "A100 SXM 80 GB" ], [ "GA100 / Ampere", "GA100 / Ampere" ], [ "2020", "2020" ], [ "Historical shipping", "历史已商用" ], [ "7 nm", "7 nm" ], [ "1 die + HBM interposer", "单裸片＋HBM 中介层" ], [ "108 SM / 432 TC", "108 SM / 432 TC" ], [ "312 TF", "312 TF" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "9.7 / 19.5 TF", "9.7 / 19.5 TF" ], [ "HBM2e; 5 active; 80; 2.039", "HBM2e; 5 active; 80; 2.039" ], [ "40 MB", "40 MB" ], [ "12; 300; 8-GPU HGX", "12；300；8 GPU HGX" ], [ "PCIe 4", "PCIe 4" ], [ "400 W; platform-dependent", "400 W；依平台" ], [ "SXM4", "SXM4" ] ], "sources": [ "P03", "P15", "P34" ] }, { "id": "h100", "values": [ [ "H100 SXM", "H100 SXM" ], [ "GH100 / Hopper", "GH100 / Hopper" ], [ "2022", "2022" ], [ "Shipping", "已商用" ], [ "4N", "4N" ], [ "1 die + HBM interposer", "单裸片＋HBM 中介层" ], [ "132 SM / 528 TC", "132 SM / 528 TC" ], [ "989 TF", "989 TF" ], [ "1.979 PF", "1.979 PF" ], [ "n/a", "n/a" ], [ "34 / 67 TF", "34 / 67 TF" ], [ "HBM3; 5 active; 80; 3.35", "HBM3; 5 active; 80; 3.35" ], [ "50 MB", "50 MB" ], [ "18; 450; 8-GPU HGX", "18；450；8 GPU HGX" ], [ "PCIe 5", "PCIe 5" ], [ "700 W; platform-dependent", "700 W；依平台" ], [ "SXM5", "SXM5" ] ], "sources": [ "P04", "P13", "P33" ] }, { "id": "h200", "values": [ [ "H200 SXM", "H200 SXM" ], [ "GH100 / Hopper", "GH100 / Hopper" ], [ "2024", "2024" ], [ "Shipping", "已商用" ], [ "4N", "4N" ], [ "Hopper + HBM3e", "Hopper＋HBM3e" ], [ "132 SM / 528 TC", "132 SM / 528 TC" ], [ "989 TF", "989 TF" ], [ "1.979 PF", "1.979 PF" ], [ "n/a", "n/a" ], [ "34 / 67 TF", "34 / 67 TF" ], [ "HBM3e; n/d; 141; 4.8", "HBM3e; n/d; 141; 4.8" ], [ "50 MB", "50 MB" ], [ "18; 450; 8-GPU HGX", "18；450；8 GPU HGX" ], [ "PCIe 5", "PCIe 5" ], [ "700 W; platform-dependent", "700 W；依平台" ], [ "SXM5", "SXM5" ] ], "sources": [ "P14", "P33" ] }, { "id": "b200", "values": [ [ "B200 / HGX basis", "B200 / HGX basis" ], [ "Blackwell", "Blackwell" ], [ "2024–2025", "2024–2025" ], [ "Shipping", "已商用" ], [ "4NP", "4NP" ], [ "2 compute dies; NV-HBI; HBM", "双计算裸片；NV-HBI；HBM" ], [ "SKU-dependent", "SKU-dependent" ], [ "2.25 PF", "2.25 PF" ], [ "4.5 PF", "4.5 PF" ], [ "4.5 / 9 PF", "4.5 / 9 PF" ], [ "37 TF published FP64; split n/d", "公布 FP64 37 TF；向量／矩阵拆分 n/d" ], [ "HBM3e; 8; 180; 8", "HBM3e; 8; 180; 8" ], [ "126 MB GB200 reference; SKU-specific", "GB200 参考值 126 MB；依 SKU" ], [ "18; 900; 8-GPU HGX", "18；900；8 GPU HGX" ], [ "PCIe 6", "PCIe 6" ], [ "Up to 1000 W module; cooling by system", "模块最高 1000 W；散热依系统" ], [ "SXM", "SXM" ] ], "sources": [ "P05", "P16", "P32", "P37" ] }, { "id": "b300", "values": [ [ "B300 / HGX basis", "B300 / HGX basis" ], [ "Blackwell Ultra", "Blackwell Ultra" ], [ "2025", "2025" ], [ "Shipping", "已商用" ], [ "4NP", "4NP" ], [ "2 compute dies; NV-HBI; HBM", "双计算裸片；NV-HBI；HBM" ], [ "Up to 160 SM / 640 TC; SKU-dependent", "最高 160 SM／640 TC；依 SKU" ], [ "2.25 PF", "2.25 PF" ], [ "4.5 PF", "4.5 PF" ], [ "4.5 / 13.5 PF", "4.5 / 13.5 PF" ], [ "1.25 TF published FP64; split n/d", "公布 FP64 1.25 TF；向量／矩阵拆分 n/d" ], [ "HBM3e; 8; up to 288; 8", "HBM3e；8；最高 288；8" ], [ "n/d", "n/d" ], [ "18; 900; 8-GPU HGX", "18；900；8 GPU HGX" ], [ "PCIe 6", "PCIe 6" ], [ "n/d at uniform module basis", "统一模块口径 n/d" ], [ "SXM", "SXM" ] ], "sources": [ "P06", "P17", "P37" ] }, { "id": "rubin", "values": [ [ "Rubin / chip peak", "Rubin / chip peak" ], [ "Rubin", "Rubin" ], [ "2026 preview; GA n/d", "2026 预览；GA n/d" ], [ "Production / preview", "量产／预览" ], [ "n/d", "n/d" ], [ "2 compute dies; NV-HBI; HBM4", "双计算裸片；NV-HBI；HBM4" ], [ "224 SM / 896 TC", "224 SM / 896 TC" ], [ "4 PF", "4 PF" ], [ "17.5 PF training", "训练 17.5 PF" ], [ "17.5 / 35 PF training", "训练 17.5／35 PF" ], [ "33 TF native; 200 TF DGEMM emulated", "原生 33 TF；模拟 DGEMM 200 TF" ], [ "HBM4; 8; 288; 22", "HBM4; 8; 288; 22" ], [ "n/d", "n/d" ], [ "n/d; 1800 peak; NVL72", "n/d；峰值 1800；NVL72" ], [ "PCIe 6", "PCIe 6" ], [ "Configuration-dependent; liquid", "依配置；液冷" ], [ "NVL / HGX", "NVL / HGX" ] ], "sources": [ "P07", "P11", "P37", "E08" ] } ], "panels": [ [ 0, 1, 2, 3, 4, 5 ], [ 0, 6, 7, 8, 9, 10 ], [ 0, 11, 12, 13 ], [ 0, 14, 15, 16 ] ], "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction" }, "cpu": { "id": "cpu", "title": [ "CPU generations: one CPU chip unless specified", "CPU 代际：除注明外按单颗 CPU" ], "headers": [ [ "Generation", "代际" ], [ "Codename", "代号" ], [ "GA / milestone", "商用／里程碑" ], [ "Status", "状态" ], [ "Core µarch", "核心微架构" ], [ "Max cores / threads", "最大核心／线程" ], [ "Process per die", "各裸片工艺" ], [ "Chiplets and packaging", "芯粒与封装" ], [ "L2 per core", "每核 L2" ], [ "L3 total / domain", "L3 总量／共享域" ], [ "Memory: type / channels / speed / GB/s", "内存：类型／通道／速率／GB/s" ], [ "Sockets and socket links", "插槽与插槽互联" ], [ "PCIe / CXL", "PCIe／CXL" ], [ "Max TDP", "最大 TDP" ], [ "Matrix / vector ISA", "矩阵／向量 ISA" ] ], "rows": [ { "id": "grace", "values": [ [ "Grace", "Grace" ], [ "Grace", "Grace" ], [ "2023", "2023" ], [ "Shipping", "已商用" ], [ "Arm Neoverse V2", "Arm Neoverse V2" ], [ "72 / 72", "72 / 72" ], [ "4N", "4N" ], [ "CPU + LPDDR; dual CPU or CPU–GPU C2C", "CPU＋LPDDR；双 CPU 或 CPU–GPU C2C" ], [ "1 MB", "1 MB" ], [ "114 MB / chip", "114 MB / chip" ], [ "LPDDR5X; up to 480 GB; 512 GB/s; channel/speed SKU-dependent", "LPDDR5X；最高 480 GB；512 GB/s；通道／速率依 SKU" ], [ "1 or 2; C2C 900 GB/s bidirectional", "1 或 2；C2C 双向 900 GB/s" ], [ "64 lanes PCIe 5; CXL n/d", "64 lanes PCIe 5; CXL n/d" ], [ "500 W dual-CPU Superchip including memory; single-chip n/d", "双 CPU Superchip 含内存 500 W；单芯片 n/d" ], [ "Armv9.0-A; 4 × 128-bit SVE2", "Armv9.0-A; 4 × 128-bit SVE2" ] ], "sources": [ "P08", "P09", "P11" ] }, { "id": "vera", "values": [ [ "Vera", "Vera" ], [ "Olympus", "Olympus" ], [ "2026 production / preview", "2026 量产／预览" ], [ "GA n/d", "GA n/d" ], [ "NVIDIA Olympus", "NVIDIA Olympus" ], [ "88 / 176", "88 / 176" ], [ "n/d", "n/d" ], [ "CPU + SOCAMM2; C2C platform", "CPU＋SOCAMM2；C2C 平台" ], [ "2 MB", "2 MB" ], [ "164 MB / chip", "164 MB / chip" ], [ "LPDDR5X SOCAMM2; up to 1.5 TB; 1200 GB/s; channel/speed n/d", "LPDDR5X SOCAMM2；最高 1.5 TB；1200 GB/s；通道／速率 n/d" ], [ "1 or 2; C2C 1800 GB/s bidirectional", "1 或 2；C2C 双向 1800 GB/s" ], [ "PCIe 6 / CXL 3.1; lane count n/d", "PCIe 6 / CXL 3.1; lane count n/d" ], [ "n/d", "n/d" ], [ "Armv9.2; 6 × 128-bit SVE2; FP8", "Armv9.2; 6 × 128-bit SVE2; FP8" ] ], "sources": [ "P10", "P11", "E08" ] } ], "panels": [ [ 0, 1, 2, 3, 4, 5 ], [ 0, 6, 7, 8, 9 ], [ 0, 10, 11, 12 ], [ 0, 13, 14 ] ], "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources" }, "derivatives": { "id": "derivatives", "title": [ "Related product branches", "相关产品分支" ], "headers": [ [ "Product", "产品" ], [ "Era", "时期" ], [ "Memory", "内存" ], [ "Deployment distinction", "部署区别" ] ], "rows": [ { "id": "p4p40", "values": [ [ "P4 / P40", "P4 / P40" ], [ "2016", "2016" ], [ "GDDR5", "GDDR5" ], [ "Pascal INT8 inference; not GP100 HBM/NVLink equivalence", "Pascal INT8 推理；不等同于 GP100 的 HBM／NVLink" ] ], "sources": [ "E18" ] }, { "id": "t4", "values": [ [ "T4", "T4" ], [ "2018", "2018" ], [ "16 GB GDDR6; 320 GB/s", "16 GB GDDR6; 320 GB/s" ], [ "70 W PCIe; inference and video; no NVLink", "70 W PCIe；推理与视频；无 NVLink" ] ], "sources": [ "P28" ] }, { "id": "l4", "values": [ [ "L4", "L4" ], [ "2023", "2023" ], [ "24 GB GDDR6; 300 GB/s", "24 GB GDDR6; 300 GB/s" ], [ "72 W Ada inference/video; no NVLink", "72 W Ada 推理／视频；无 NVLink" ] ], "sources": [ "P29" ] }, { "id": "l40s", "values": [ [ "L40S", "L40S" ], [ "2023", "2023" ], [ "48 GB GDDR6; 864 GB/s", "48 GB GDDR6; 864 GB/s" ], [ "350 W; graphics plus AI; no NVLink", "350 W；图形与 AI；无 NVLink" ] ], "sources": [ "P30" ] }, { "id": "rtxpro", "values": [ [ "RTX PRO 6000 Blackwell Server Edition", "RTX PRO 6000 Blackwell Server Edition" ], [ "2025", "2025" ], [ "96 GB GDDR7; 1597 GB/s", "96 GB GDDR7; 1597 GB/s" ], [ "Up to 600 W; graphics, AI and partitioned services", "最高 600 W；图形、AI 与分区服务" ] ], "sources": [ "P31" ] }, { "id": "gb10", "values": [ [ "GB10 / DGX Spark", "GB10 / DGX Spark" ], [ "2025–2026", "2025–2026" ], [ "128 GB LPDDR5X; 273 GB/s", "128 GB LPDDR5X; 273 GB/s" ], [ "20 Arm cores; coherent shared memory; desktop AI; 140 W SoC TDP", "20 个 Arm 核心；一致性共享内存；桌面 AI；SoC TDP 140 W" ] ], "sources": [ "P46", "C10" ] }, { "id": "thor", "values": [ [ "Jetson AGX Thor", "Jetson AGX Thor" ], [ "2025–2026", "2025–2026" ], [ "Edge configuration; not server HBM equivalence", "边缘配置；不等同于服务器 HBM" ], [ "Blackwell-derived edge/robotics branch; benchmark scope differs", "源于 Blackwell 的边缘／机器人分支；基准范围不同" ] ], "sources": [ "E08" ] } ], "panels": [ [ 0, 1, 2, 3 ] ], "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources" }, "interconnect": { "id": "interconnect", "title": [ "Interconnect generations", "互联代际" ], "headers": [ [ "Name / version", "名称／版本" ], [ "Year", "年份" ], [ "Lane rate", "通道速率" ], [ "Lanes per link", "每链路通道数" ], [ "GB/s per link per direction", "每链路单向 GB/s" ], [ "Links per device", "每设备链路数" ], [ "Topology", "拓扑" ], [ "Max / reference domain", "最大／参考域" ], [ "Coherence / memory semantics", "一致性／内存语义" ] ], "rows": [ { "id": "nv1", "values": [ [ "NVLink 1", "NVLink 1" ], [ "2016", "2016" ], [ "20 Gb/s", "20 Gb/s" ], [ "8", "8" ], [ "20", "20" ], [ "4", "4" ], [ "Direct peer links", "对等直连" ], [ "Server wiring-dependent", "依服务器布线" ], [ "GPU peer access; not uniform memory", "GPU 对等访问；非统一内存" ] ], "sources": [ "P01" ] }, { "id": "nv2", "values": [ [ "NVLink 2", "NVLink 2" ], [ "2017–2018", "2017–2018" ], [ "25 Gb/s", "25 Gb/s" ], [ "8", "8" ], [ "25", "25" ], [ "6", "6" ], [ "Direct + NVSwitch", "直连＋NVSwitch" ], [ "16 GPUs (DGX-2)", "16 GPUs (DGX-2)" ], [ "Peer memory; platform-specific CPU coherence", "对等内存；CPU 一致性依平台" ] ], "sources": [ "P02", "P18" ] }, { "id": "nv3", "values": [ [ "NVLink 3", "NVLink 3" ], [ "2020", "2020" ], [ "50 Gb/s", "50 Gb/s" ], [ "4", "4" ], [ "25", "25" ], [ "12", "12" ], [ "NVSwitch", "NVSwitch" ], [ "8 GPUs (HGX)", "8 GPUs (HGX)" ], [ "GPU peer memory", "GPU 对等内存" ] ], "sources": [ "P03" ] }, { "id": "nv4", "values": [ [ "NVLink 4", "NVLink 4" ], [ "2022", "2022" ], [ "100 Gb/s", "100 Gb/s" ], [ "2", "2" ], [ "25", "25" ], [ "18", "18" ], [ "NVSwitch", "NVSwitch" ], [ "8 HGX; larger external switch systems", "HGX 8 个；外部交换可扩展" ], [ "GPU peer memory / collectives", "GPU 对等内存／集合通信" ] ], "sources": [ "P04", "P18" ] }, { "id": "nv5", "values": [ [ "NVLink 5", "NVLink 5" ], [ "2024–2025", "2024–2025" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "50", "50" ], [ "18", "18" ], [ "NVSwitch", "NVSwitch" ], [ "72 GPUs (NVL72)", "72 GPUs (NVL72)" ], [ "Rack peer domain; not uniform latency", "机架对等域；非统一延迟" ] ], "sources": [ "P18", "P05" ] }, { "id": "nv6", "values": [ [ "NVLink 6", "NVLink 6" ], [ "2026", "2026" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "NVSwitch", "NVSwitch" ], [ "72 GPUs (NVL72)", "72 GPUs (NVL72)" ], [ "3600 GB/s bidirectional peak per GPU; configured 3000", "单 GPU 双向峰值 3600 GB/s；配置值 3000" ] ], "sources": [ "P11", "P18", "P38" ] }, { "id": "c2c1", "values": [ [ "NVLink-C2C / Grace", "NVLink-C2C / Grace" ], [ "2023", "2023" ], [ "40 Gb/s/pin", "40 Gb/s/pin" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "10", "10" ], [ "CPU–CPU / CPU–GPU", "CPU–CPU／CPU–GPU" ], [ "Coherent module", "一致性模块" ], [ "900 GB/s bidirectional; coherent access", "双向 900 GB/s；一致性访问" ] ], "sources": [ "C09", "P08" ] }, { "id": "c2c2", "values": [ [ "NVLink-C2C / Vera", "NVLink-C2C / Vera" ], [ "2026", "2026" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "CPU–GPU / CPU–CPU", "CPU–GPU／CPU–CPU" ], [ "Coherent platform", "一致性平台" ], [ "1800 GB/s bidirectional", "双向 1800 GB/s" ] ], "sources": [ "P10", "P11" ] } ], "panels": [ [ 0, 1, 2, 3, 4, 5 ], [ 0, 6, 7, 8 ] ], "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional" }, "network": { "id": "network", "title": [ "NIC and DPU evolution", "NIC 与 DPU 演进" ], "headers": [ [ "Product", "产品" ], [ "GA / milestone", "商用／里程碑" ], [ "Status", "状态" ], [ "Class", "类别" ], [ "Ports × speed", "端口×速率" ], [ "SerDes", "SerDes" ], [ "Host interface", "主机接口" ], [ "Programmable engine", "可编程引擎" ], [ "Embedded CPU", "嵌入式 CPU" ], [ "On-card memory", "板载内存" ], [ "Transport / RDMA", "传输／RDMA" ], [ "Congestion control", "拥塞控制" ], [ "Key offloads", "主要卸载" ], [ "Power", "功耗" ] ], "rows": [ { "id": "cx4lx", "values": [ [ "ConnectX-4 Lx", "ConnectX-4 Lx" ], [ "2015–2016 era", "2015–2016 时期" ], [ "Historical shipping", "历史已商用" ], [ "NIC", "NIC" ], [ "25/50 GbE variants", "25／50 GbE 变体" ], [ "25G NRZ", "25G NRZ" ], [ "PCIe 3 x8/x16", "PCIe 3 x8/x16" ], [ "eSwitch / steering", "eSwitch／流量引导" ], [ "n/a", "n/a" ], [ "Adapter buffers; capacity n/d", "网卡缓冲；容量 n/d" ], [ "Ethernet / RoCE", "Ethernet / RoCE" ], [ "ECN / PFC", "ECN / PFC" ], [ "Overlay, virtualization, RDMA", "覆盖网络、虚拟化、RDMA" ], [ "SKU-dependent", "SKU-dependent" ] ], "sources": [ "P43" ] }, { "id": "cx5", "values": [ [ "ConnectX-5 / Ex", "ConnectX-5 / Ex" ], [ "2017 era", "2017 时期" ], [ "Historical shipping", "历史已商用" ], [ "NIC", "NIC" ], [ "up to 2 × 100 Gb/s", "up to 2 × 100 Gb/s" ], [ "25G NRZ", "25G NRZ" ], [ "PCIe 3 x16; Ex PCIe 4", "PCIe 3 x16; Ex PCIe 4" ], [ "eSwitch / steering", "eSwitch／流量引导" ], [ "n/a", "n/a" ], [ "n/d", "n/d" ], [ "Ethernet / IB / RoCE", "Ethernet / IB / RoCE" ], [ "ECN / PFC", "ECN / PFC" ], [ "GPUDirect RDMA; storage; switching", "GPUDirect RDMA；存储；交换" ], [ "SKU-dependent", "SKU-dependent" ] ], "sources": [ "P49", "P48" ] }, { "id": "cx6", "values": [ [ "ConnectX-6", "ConnectX-6" ], [ "2019 era", "2019 时期" ], [ "Historical shipping", "历史已商用" ], [ "NIC", "NIC" ], [ "up to 200 Gb/s", "up to 200 Gb/s" ], [ "50G PAM4", "50G PAM4" ], [ "PCIe 4 x16", "PCIe 4 x16" ], [ "Transport / steering", "传输／流量引导" ], [ "n/a", "n/a" ], [ "n/d", "n/d" ], [ "Ethernet / HDR IB / RoCE", "Ethernet / HDR IB / RoCE" ], [ "ECN / PFC", "ECN / PFC" ], [ "GPUDirect RDMA; variant-specific crypto", "GPUDirect RDMA；加密依变体" ], [ "SKU-dependent", "SKU-dependent" ] ], "sources": [ "P26" ] }, { "id": "cx7", "values": [ [ "ConnectX-7", "ConnectX-7" ], [ "2022 era", "2022 时期" ], [ "Shipping", "已商用" ], [ "NIC / SuperNIC", "NIC / SuperNIC" ], [ "1 × 400 / 2 × 200 Gb/s", "1 × 400 / 2 × 200 Gb/s" ], [ "100G PAM4", "100G PAM4" ], [ "PCIe 5 x16; Socket Direct", "PCIe 5 x16; Socket Direct" ], [ "Transport / steering", "传输／流量引导" ], [ "n/a", "n/a" ], [ "n/d", "n/d" ], [ "Ethernet / NDR IB / RoCE", "Ethernet / NDR IB / RoCE" ], [ "Adaptive routing / ECN by fabric", "按网络采用自适应路由／ECN" ], [ "GPUDirect; virtualization; crypto", "GPUDirect；虚拟化；加密" ], [ "SKU-dependent", "SKU-dependent" ] ], "sources": [ "P50", "P22" ] }, { "id": "cx8", "values": [ [ "ConnectX-8", "ConnectX-8" ], [ "2025", "2025" ], [ "Shipping platform generation", "已商用平台代际" ], [ "SuperNIC", "SuperNIC" ], [ "800 Gb/s class", "800 Gb/s 级" ], [ "n/d", "n/d" ], [ "PCIe 6 + integrated switch", "PCIe 6 + integrated switch" ], [ "Programmable transport / steering", "可编程传输／流量引导" ], [ "n/a", "n/a" ], [ "n/d", "n/d" ], [ "Ethernet / IB / RoCE", "Ethernet / IB / RoCE" ], [ "AI adaptive routing / congestion control", "AI 自适应路由／拥塞控制" ], [ "GPU/NIC PCIe switching; GPUDirect", "GPU／NIC PCIe 交换；GPUDirect" ], [ "SKU-dependent", "SKU-dependent" ] ], "sources": [ "P19", "P22", "C06" ] }, { "id": "cx9", "values": [ [ "ConnectX-9", "ConnectX-9" ], [ "2026", "2026" ], [ "Production; configuration-dependent", "量产；依配置" ], [ "SuperNIC", "SuperNIC" ], [ "800 Gb/s card; up to 1600 Gb/s per GPU platform", "800 Gb/s 网卡；平台单 GPU 最高 1600 Gb/s" ], [ "200G class", "200G class" ], [ "PCIe 6 x16 / Socket Direct x32", "PCIe 6 x16 / Socket Direct x32" ], [ "AI transport / steering", "AI 传输／流量引导" ], [ "n/a", "n/a" ], [ "n/d", "n/d" ], [ "Ethernet / XDR IB / RoCE", "Ethernet / XDR IB / RoCE" ], [ "Spectrum-X multiplane / adaptive routing", "Spectrum-X 多平面／自适应路由" ], [ "GPUDirect; PCIe fabric; security", "GPUDirect；PCIe 互联；安全" ], [ "SKU-dependent", "SKU-dependent" ] ], "sources": [ "P21", "P22", "P11", "E09" ] }, { "id": "bf1", "values": [ [ "BlueField", "BlueField" ], [ "Pre-2020; exact GA n/d", "2020 年前；确切 GA n/d" ], [ "Historical shipping", "历史已商用" ], [ "DPU", "DPU" ], [ "up to 2 × 100 Gb/s", "up to 2 × 100 Gb/s" ], [ "25G class", "25G class" ], [ "up to 32 lanes PCIe 3/4", "up to 32 lanes PCIe 3/4" ], [ "ConnectX-5 eSwitch", "ConnectX-5 eSwitch" ], [ "up to 16 Arm A72", "up to 16 Arm A72" ], [ "DDR4; capacity SKU-dependent", "DDR4; capacity SKU-dependent" ], [ "Ethernet / IB / RoCE", "Ethernet / IB / RoCE" ], [ "ECN / PFC", "ECN / PFC" ], [ "NVMe-oF; switching; virtualization", "NVMe-oF；交换；虚拟化" ], [ "SKU-dependent", "SKU-dependent" ] ], "sources": [ "P48", "E05" ] }, { "id": "bf2", "values": [ [ "BlueField-2", "BlueField-2" ], [ "2020–2021 generation", "2020–2021 代际" ], [ "Shipping", "已商用" ], [ "DPU", "DPU" ], [ "up to 200 Gb/s", "up to 200 Gb/s" ], [ "50G class", "50G class" ], [ "PCIe 4 x16", "PCIe 4 x16" ], [ "ConnectX-6 Dx + Arm", "ConnectX-6 Dx + Arm" ], [ "8 Arm A72", "8 Arm A72" ], [ "DDR4; SKU-dependent", "DDR4; SKU-dependent" ], [ "Ethernet / RoCE; variants", "Ethernet / RoCE; variants" ], [ "ECN / PFC", "ECN / PFC" ], [ "DOCA; storage; crypto; virtual switch", "DOCA；存储；加密；虚拟交换" ], [ "SKU-dependent", "SKU-dependent" ] ], "sources": [ "P25" ] }, { "id": "bf3", "values": [ [ "BlueField-3", "BlueField-3" ], [ "2023 generation", "2023 代际" ], [ "Shipping", "已商用" ], [ "DPU / SuperNIC", "DPU / SuperNIC" ], [ "up to 400 Gb/s", "up to 400 Gb/s" ], [ "100G class", "100G class" ], [ "up to 32 lanes PCIe 5", "up to 32 lanes PCIe 5" ], [ "ConnectX-7 + DPA + Arm", "ConnectX-7 + DPA + Arm" ], [ "up to 16 Arm A78", "up to 16 Arm A78" ], [ "16/32 GB DDR5; SKU-dependent", "16/32 GB DDR5; SKU-dependent" ], [ "Ethernet / NDR IB / RoCE", "Ethernet / NDR IB / RoCE" ], [ "Spectrum-X / adaptive congestion control", "Spectrum-X／自适应拥塞控制" ], [ "DOCA; storage/security; asynchronous offload", "DOCA；存储／安全；异步卸载" ], [ "SKU-dependent", "SKU-dependent" ] ], "sources": [ "P24", "P22" ] }, { "id": "bf4", "values": [ [ "BlueField-4", "BlueField-4" ], [ "2026", "2026" ], [ "Production disclosure", "已披露量产" ], [ "DPU", "DPU" ], [ "800 Gb/s", "800 Gb/s" ], [ "200G class", "200G class" ], [ "PCIe 6", "PCIe 6" ], [ "ConnectX-9 + Grace", "ConnectX-9 + Grace" ], [ "64 Neoverse V2", "64 Neoverse V2" ], [ "LPDDR5X; 250 GB/s", "LPDDR5X; 250 GB/s" ], [ "Ethernet / RDMA", "Ethernet / RDMA" ], [ "Platform-dependent", "依平台" ], [ "Infrastructure OS; STX / context storage; security", "基础设施操作系统；STX／上下文存储；安全" ], [ "n/d", "n/d" ] ], "sources": [ "P20", "P11", "E01" ] } ], "panels": [ [ 0, 1, 2, 3, 4 ], [ 0, 5, 6, 7 ], [ 0, 8, 9, 10 ], [ 0, 11, 12, 13 ] ], "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent" }, "switch": { "id": "switch", "title": [ "Switch and fabric evolution", "交换芯片与网络演进" ], "headers": [ [ "Family", "产品族" ], [ "Milestone", "里程碑" ], [ "Published capacity", "公布容量" ], [ "Architecture / deployment meaning", "架构／部署意义" ] ], "rows": [ { "id": "s1", "values": [ [ "Spectrum-1", "Spectrum-1" ], [ "2015 generation", "2015 代际" ], [ "3.2 Tb/s", "3.2 Tb/s" ], [ "Ethernet switching baseline", "以太网交换起点" ] ], "sources": [ "P47" ] }, { "id": "s2", "values": [ [ "Spectrum-2", "Spectrum-2" ], [ "2018–2019 generation", "2018–2019 代际" ], [ "6.4 Tb/s", "6.4 Tb/s" ], [ "50G-class lanes; 200GbE ports", "50G 级通道；200GbE 端口" ] ], "sources": [ "P51" ] }, { "id": "s3", "values": [ [ "Spectrum-3", "Spectrum-3" ], [ "2020 generation", "2020 代际" ], [ "12.8 Tb/s", "12.8 Tb/s" ], [ "400GbE generation", "400GbE 代际" ] ], "sources": [ "P47" ] }, { "id": "s4", "values": [ [ "Spectrum-4 / Spectrum-X", "Spectrum-4 / Spectrum-X" ], [ "2022 chip; 2023 platform", "2022 芯片；2023 平台" ], [ "51.2 Tb/s", "51.2 Tb/s" ], [ "400/800GbE; switch + SuperNIC + software co-design", "400／800GbE；交换机＋SuperNIC＋软件协同" ] ], "sources": [ "E02", "P39" ] }, { "id": "s6", "values": [ [ "Spectrum-6", "Spectrum-6" ], [ "2026 production / adoption", "2026 量产／采用" ], [ "102.4 Tb/s ASIC", "102.4 Tb/s ASIC" ], [ "Multiplane AI Ethernet; Vera Rubin ecosystem", "多平面 AI 以太网；Vera Rubin 生态" ] ], "sources": [ "E10", "E09", "P39" ] }, { "id": "photonics", "values": [ [ "Spectrum-X / Quantum-X photonics", "Spectrum-X / Quantum-X photonics" ], [ "2025–2026 disclosures", "2025–2026 披露" ], [ "Up to 409.6 Tb/s Spectrum-X assembly; not one ASIC", "Spectrum-X 组件最高 409.6 Tb/s；不是单颗 ASIC" ], [ "Co-packaged optics; product configuration and rollout vary", "共封装光学；配置与推出节奏因产品而异" ] ], "sources": [ "P23" ] }, { "id": "qx", "values": [ [ "Quantum-X800 / Q3450-LD", "Quantum-X800 / Q3450-LD" ], [ "2025–2026 disclosures", "2025–2026 披露" ], [ "144 × 800 Gb/s", "144 × 800 Gb/s" ], [ "CPO-based InfiniBand switch; 200G SerDes; liquid cooling", "基于 CPO 的 InfiniBand 交换机；200G SerDes；液冷" ] ], "sources": [ "P23" ] }, { "id": "q2", "values": [ [ "Quantum-2", "Quantum-2" ], [ "2021 announcement; 2022 generation", "2021 发布；2022 代际" ], [ "64 × 400 Gb/s = 25.6 Tb/s one-way", "64 × 400 Gb/s = 25.6 Tb/s one-way" ], [ "NDR InfiniBand; adaptive routing; SHARP collectives", "NDR InfiniBand；自适应路由；SHARP 集合通信" ] ], "sources": [ "P40" ] } ], "panels": [ [ 0, 1, 2, 3 ] ], "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources" }, "systems": { "id": "systems", "title": [ "System reference configurations", "系统参考配置" ], "headers": [ [ "Platform", "平台" ], [ "Year", "年份" ], [ "CPUs / accelerators", "CPU／加速器" ], [ "Scale-up domain", "纵向扩展域" ], [ "Scale-out per accelerator", "每加速器横向扩展" ], [ "Rack / system power", "机架／系统功耗" ], [ "Cooling", "散热" ] ], "rows": [ { "id": "dgx1", "values": [ [ "DGX-1 / P100", "DGX-1 / P100" ], [ "2016", "2016" ], [ "x86 + 8 P100", "x86 + 8 P100" ], [ "8 GPUs; nonuniform direct topology", "8 GPU；非均匀直连拓扑" ], [ "configuration-dependent", "configuration-dependent" ], [ "n/d", "n/d" ], [ "Air", "风冷" ] ], "sources": [ "P01" ] }, { "id": "dgx2", "values": [ [ "DGX-2 / V100", "DGX-2 / V100" ], [ "2018", "2018" ], [ "x86 + 16 V100", "x86 + 16 V100" ], [ "16 GPUs / NVSwitch", "16 GPUs / NVSwitch" ], [ "configuration-dependent", "configuration-dependent" ], [ "n/d", "n/d" ], [ "Air", "风冷" ] ], "sources": [ "P02", "P18" ] }, { "id": "hgxa", "values": [ [ "HGX / DGX A100", "HGX / DGX A100" ], [ "2020", "2020" ], [ "x86 + 8 A100", "x86 + 8 A100" ], [ "8 GPUs / NVSwitch", "8 GPUs / NVSwitch" ], [ "configuration-dependent", "configuration-dependent" ], [ "n/d", "n/d" ], [ "Platform-dependent", "依平台" ] ], "sources": [ "P03" ] }, { "id": "hgxh", "values": [ [ "HGX H100 / H200", "HGX H100 / H200" ], [ "2022–2024", "2022–2024" ], [ "x86 + 8 GPUs", "x86 + 8 GPUs" ], [ "8 GPUs / NVSwitch", "8 GPUs / NVSwitch" ], [ "configuration-dependent", "configuration-dependent" ], [ "n/d", "n/d" ], [ "Air / liquid by system", "按系统采用风冷／液冷" ] ], "sources": [ "P13", "P14" ] }, { "id": "gh", "values": [ [ "GH200 systems", "GH200 systems" ], [ "2023–2024", "2023–2024" ], [ "Grace + Hopper", "Grace + Hopper" ], [ "Coherent module; wider topology by system", "一致性模块；更大拓扑依系统" ], [ "configuration-dependent", "configuration-dependent" ], [ "n/d", "n/d" ], [ "Platform-dependent", "依平台" ] ], "sources": [ "P08" ] }, { "id": "gb200", "values": [ [ "GB200 NVL72", "GB200 NVL72" ], [ "2025", "2025" ], [ "36 Grace + 72 Blackwell", "36 Grace + 72 Blackwell" ], [ "72 GPU packages", "72 GPU packages" ], [ "Reference / cloud-specific; AWS 400 Gb/s EFA per GPU", "依参考／云配置；AWS 单 GPU 400 Gb/s EFA" ], [ "configuration-dependent", "configuration-dependent" ], [ "Liquid", "液冷" ] ], "sources": [ "E16", "P27" ] }, { "id": "gb300", "values": [ [ "GB300 NVL72", "GB300 NVL72" ], [ "2025", "2025" ], [ "36 Grace + 72 Blackwell Ultra", "36 Grace + 72 Blackwell Ultra" ], [ "72 GPU packages", "72 GPU packages" ], [ "configuration-dependent", "configuration-dependent" ], [ "configuration-dependent", "configuration-dependent" ], [ "Liquid", "液冷" ] ], "sources": [ "P06", "E15" ] }, { "id": "rubin", "values": [ [ "Vera Rubin NVL72", "Vera Rubin NVL72" ], [ "2026", "2026" ], [ "36 Vera + 72 Rubin", "36 Vera + 72 Rubin" ], [ "72 GPU packages", "72 GPU packages" ], [ "200 GB/s one-way reference; 225 GB/s MaxLPS page", "参考单向 200 GB/s；MaxLPS 页面 225 GB/s" ], [ "configuration-dependent", "configuration-dependent" ], [ "Liquid", "液冷" ] ], "sources": [ "P11", "P38", "E08" ] }, { "id": "lpx", "values": [ [ "Groq 3 LPX", "Groq 3 LPX" ], [ "2026", "2026" ], [ "256 LPUs; 32 trays", "256 LPUs; 32 trays" ], [ "LPU fabric; not NVLink GPU domain", "LPU 互联；非 NVLink GPU 域" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "Liquid", "液冷" ] ], "sources": [ "P12", "E09" ] } ], "panels": [ [ 0, 1, 2, 3 ], [ 0, 4, 5, 6 ] ], "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources" }, "ratios": { "id": "ratios", "title": [ "Normalized comparisons and derived implications", "归一化比较与推导" ], "headers": [ [ "Comparison", "比较" ], [ "Calculation", "计算" ], [ "Interpretation", "解释" ] ], "rows": [ { "id": "h200cap", "values": [ [ "H200 / H100 capacity", "H200／H100 容量" ], [ "141 / 80 = 1.76×", "141 / 80 = 1.76×" ], [ "More model / KV capacity without a new SM generation", "不改变 SM 代际即可增加模型／KV 容量" ] ], "sources": [ "P13", "P14" ] }, { "id": "h200bw", "values": [ [ "H200 / H100 HBM bandwidth", "H200／H100 HBM 带宽" ], [ "4.8 / 3.35 = 1.43×", "4.8 / 3.35 = 1.43×" ], [ "Bandwidth gain differs from capacity gain", "带宽增幅不同于容量增幅" ] ], "sources": [ "P13", "P14" ] }, { "id": "gracecore", "values": [ [ "Grace peak memory per core", "Grace 每核峰值内存带宽" ], [ "512 / 72 = 7.11 GB/s", "512 / 72 = 7.11 GB/s" ], [ "Aggregate divided by cores; not a guarantee per core", "总量除以核心数；非每核保证值" ] ], "sources": [ "P09", "P11" ] }, { "id": "veracore", "values": [ [ "Vera peak memory per core", "Vera 每核峰值内存带宽" ], [ "1200 / 88 = 13.64 GB/s", "1200 / 88 = 13.64 GB/s" ], [ "1.92× Grace on this basis", "此口径约为 Grace 的 1.92 倍" ] ], "sources": [ "P10", "P11" ] }, { "id": "rubinbw", "values": [ [ "Rubin HBM / NVLink, MaxLPS", "Rubin HBM／NVLink，MaxLPS" ], [ "19.2 / (3 / 2) = 12.8×", "19.2 / (3 / 2) = 12.8×" ], [ "Local HBM bandwidth exceeds one-way peer injection", "本地 HBM 带宽高于单向对等注入带宽" ] ], "sources": [ "P38" ] }, { "id": "rubinnet", "values": [ [ "Rubin NVLink / scale-out, MaxLPS", "Rubin NVLink／横向扩展，MaxLPS" ], [ "(3 / 2) / (0.45 / 2) = 6.67×", "(3 / 2) / (0.45 / 2) = 6.67×" ], [ "Rack-local placement can avoid a slower network tier", "机架内放置可避免较慢的网络层" ] ], "sources": [ "P38" ] }, { "id": "cx", "values": [ [ "800 Gb/s network conversion", "800 Gb/s 网络换算" ], [ "800 / 8 = 100 GB/s", "800 / 8 = 100 GB/s" ], [ "Line rate before protocol and PCIe overheads", "未扣除协议与 PCIe 开销的线速" ] ], "sources": [ "P19", "P21" ] } ], "panels": [ [ 0, 1, 2 ] ], "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources" }, "software": { "id": "software", "title": [ "Software and programming milestones", "软件与编程里程碑" ], "headers": [ [ "Release / family", "版本／产品族" ], [ "Date / era", "日期／时期" ], [ "Hardware enabled", "关联硬件" ], [ "Key features", "关键能力" ] ], "rows": [ { "id": "cuda8", "values": [ [ "CUDA / Pascal", "CUDA / Pascal" ], [ "2016", "2016" ], [ "P100", "P100" ], [ "Unified memory evolution; Pascal programming", "统一内存演进；Pascal 编程" ] ], "sources": [ "P01", "P36" ] }, { "id": "cuda9", "values": [ [ "CUDA / Volta", "CUDA / Volta" ], [ "2017", "2017" ], [ "V100", "V100" ], [ "Tensor programming; independent scheduling", "张量编程；独立线程调度" ] ], "sources": [ "P02", "P35" ] }, { "id": "ampere", "values": [ [ "Ampere software generation", "Ampere software generation" ], [ "2020", "2020" ], [ "A100", "A100" ], [ "TF32 / BF16 libraries; MIG; sparsity support", "TF32／BF16 库；MIG；稀疏支持" ] ], "sources": [ "P03", "P34" ] }, { "id": "hopper", "values": [ [ "Hopper software generation", "Hopper software generation" ], [ "2022–2024", "2022–2024" ], [ "H100 / H200 / GH200", "H100 / H200 / GH200" ], [ "Transformer Engine; TMA; clusters; FP8", "Transformer Engine；TMA；集群；FP8" ] ], "sources": [ "P04", "P33" ] }, { "id": "blackwell", "values": [ [ "Blackwell software generation", "Blackwell software generation" ], [ "2024–2026", "2024–2026" ], [ "B200 / B300 / GB200 / GB300", "B200 / B300 / GB200 / GB300" ], [ "FP4 / FP6; Tensor Memory; revised kernels", "FP4／FP6；Tensor Memory；新内核" ] ], "sources": [ "P06", "P32" ] }, { "id": "nccl", "values": [ [ "NCCL / NVSHMEM ecosystem", "NCCL / NVSHMEM ecosystem" ], [ "Cross-generation", "跨代" ], [ "GPU fabrics", "GPU fabrics" ], [ "Collective communication and GPU-oriented communication; topology-aware algorithms", "集合通信与面向 GPU 的通信；拓扑感知算法" ] ], "sources": [ "P44", "P39" ] }, { "id": "doca", "values": [ [ "DOCA", "DOCA" ], [ "BlueField era", "BlueField 时期" ], [ "BlueField / ConnectX", "BlueField / ConnectX" ], [ "Infrastructure offload APIs and services", "基础设施卸载 API 与服务" ] ], "sources": [ "P20", "P24", "P25" ] }, { "id": "dynamo", "values": [ [ "Dynamo", "Dynamo" ], [ "2025 onward", "2025 onward" ], [ "Distributed inference", "Distributed inference" ], [ "Disaggregated serving; scheduling and data movement", "分离式服务；调度与数据搬移" ] ], "sources": [ "E17", "E08" ] } ], "panels": [ [ 0, 1, 2, 3 ] ], "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources" }, "venues": { "id": "venues", "title": [ "Selected disclosures and their evidentiary role", "精选披露及其证据作用" ], "headers": [ [ "Venue", "会议" ], [ "Year", "年份" ], [ "Paper / talk", "论文／演讲" ], [ "Presenters / authors", "演讲者／作者" ], [ "Product / generation", "产品／代际" ], [ "Disclosure type", "披露类型" ], [ "Source / link ID", "来源／链接编号" ] ], "rows": [ { "id": "hc16", "values": [ [ "Hot Chips", "Hot Chips" ], [ "2016", "2016" ], [ "Ultra-Performance Pascal GPU and NVLink Interconnect", "Ultra-Performance Pascal GPU and NVLink Interconnect" ], [ "Denis Foley", "Denis Foley" ], [ "P100 / NVLink 1", "P100 / NVLink 1" ], [ "Product architecture", "产品架构" ], [ "C01", "C01" ] ], "sources": [ "C01" ] }, { "id": "hc17", "values": [ [ "Hot Chips", "Hot Chips" ], [ "2017", "2017" ], [ "NVIDIA’s Volta GPU: Programmability and Performance for GPU Computing", "NVIDIA’s Volta GPU: Programmability and Performance for GPU Computing" ], [ "Jack Choquette", "Jack Choquette" ], [ "V100", "V100" ], [ "Product architecture", "产品架构" ], [ "C02", "C02" ] ], "sources": [ "C02" ] }, { "id": "hc20", "values": [ [ "Hot Chips", "Hot Chips" ], [ "2020", "2020" ], [ "A100 / Ampere architecture", "A100 / Ampere architecture" ], [ "NVIDIA", "NVIDIA" ], [ "A100", "A100" ], [ "Product architecture", "产品架构" ], [ "C03", "C03" ] ], "sources": [ "C03" ] }, { "id": "hc22h", "values": [ [ "Hot Chips", "Hot Chips" ], [ "2022", "2022" ], [ "NVIDIA’s Hopper GPU: Scaling Performance", "NVIDIA’s Hopper GPU: Scaling Performance" ], [ "Jack Choquette", "Jack Choquette" ], [ "H100", "H100" ], [ "Product architecture", "产品架构" ], [ "C04", "C04" ] ], "sources": [ "C04" ] }, { "id": "hc22g", "values": [ [ "Hot Chips", "Hot Chips" ], [ "2022", "2022" ], [ "NVIDIA’s Grace CPU", "NVIDIA’s Grace CPU" ], [ "NVIDIA", "NVIDIA" ], [ "Grace", "Grace" ], [ "CPU / memory system", "CPU／内存系统" ], [ "C04", "C04" ] ], "sources": [ "C04" ] }, { "id": "hc22n", "values": [ [ "Hot Chips", "Hot Chips" ], [ "2022", "2022" ], [ "NVLink-Network Switch", "NVLink-Network Switch" ], [ "NVIDIA", "NVIDIA" ], [ "NVLink switch", "NVLink switch" ], [ "Scale-up architecture", "纵向扩展架构" ], [ "C04", "C04" ] ], "sources": [ "C04" ] }, { "id": "hc24", "values": [ [ "Hot Chips", "Hot Chips" ], [ "2024", "2024" ], [ "NVIDIA Blackwell Platform: Advancing Generative AI and Accelerated Computing", "NVIDIA Blackwell Platform: Advancing Generative AI and Accelerated Computing" ], [ "Ajay Tirumala; Raymond Wong", "Ajay Tirumala; Raymond Wong" ], [ "Blackwell / GB200", "Blackwell / GB200" ], [ "Product and system architecture", "产品与系统架构" ], [ "C05 C11", "C05 C11" ] ], "sources": [ "C05", "C11" ] }, { "id": "hc25n", "values": [ [ "Hot Chips", "Hot Chips" ], [ "2025", "2025" ], [ "GB200 NVL72 case study", "GB200 NVL72 case study" ], [ "John Norton", "John Norton" ], [ "GB200 NVL72", "GB200 NVL72" ], [ "System tutorial", "系统教程" ], [ "C06", "C06" ] ], "sources": [ "C06" ] }, { "id": "hc25c", "values": [ [ "Hot Chips", "Hot Chips" ], [ "2025", "2025" ], [ "ConnectX-8 SuperNIC: A Programmable RoCE Architecture for AI Data Centers", "ConnectX-8 SuperNIC: A Programmable RoCE Architecture for AI Data Centers" ], [ "Idan Burstein", "Idan Burstein" ], [ "ConnectX-8", "ConnectX-8" ], [ "Network endpoint architecture", "网络端点架构" ], [ "C06 P19", "C06 P19" ] ], "sources": [ "C06", "P19" ] }, { "id": "hc25p", "values": [ [ "Hot Chips", "Hot Chips" ], [ "2025", "2025" ], [ "Co-Packaged Silicon Photonics Switches for Gigawatt AI Factories", "Co-Packaged Silicon Photonics Switches for Gigawatt AI Factories" ], [ "Gilad Shainer", "Gilad Shainer" ], [ "Photonics", "Photonics" ], [ "Optical networking", "光网络" ], [ "C06 P23", "C06 P23" ] ], "sources": [ "C06", "P23" ] }, { "id": "hc25g", "values": [ [ "Hot Chips", "Hot Chips" ], [ "2025", "2025" ], [ "NVIDIA’s GB10 SoC: AI Supercomputer On Your Desk", "NVIDIA’s GB10 SoC: AI Supercomputer On Your Desk" ], [ "Andi Skende", "Andi Skende" ], [ "GB10", "GB10" ], [ "SoC architecture", "SoC 架构" ], [ "C06", "C06" ] ], "sources": [ "C06" ] }, { "id": "hc25r", "values": [ [ "Hot Chips", "Hot Chips" ], [ "2025", "2025" ], [ "RTX 5090: Designed for the Age of Neural Rendering", "RTX 5090: Designed for the Age of Neural Rendering" ], [ "Marc Blackstein", "Marc Blackstein" ], [ "Client Blackwell", "Client Blackwell" ], [ "Related graphics branch", "相关图形分支" ], [ "C06", "C06" ] ], "sources": [ "C06" ] }, { "id": "hc26v", "values": [ [ "Hot Chips", "Hot Chips" ], [ "2026", "2026" ], [ "Vera CPU", "Vera CPU" ], [ "Jonathon Evans; Polychronis Xekalakis", "Jonathon Evans; Polychronis Xekalakis" ], [ "Vera", "Vera" ], [ "Program + vendor technical disclosure", "程序＋厂商技术披露" ], [ "C07 P10", "C07 P10" ] ], "sources": [ "C07", "P10" ] }, { "id": "hc26r", "values": [ [ "Hot Chips", "Hot Chips" ], [ "2026", "2026" ], [ "Rubin GPU: Driving the Era of Agentic AI", "Rubin GPU: Driving the Era of Agentic AI" ], [ "Manas Mandal; Rajballav Dash; Rouslan Dimitrov", "Manas Mandal; Rajballav Dash; Rouslan Dimitrov" ], [ "Rubin", "Rubin" ], [ "Program + vendor technical disclosure", "程序＋厂商技术披露" ], [ "C07 P07", "C07 P07" ] ], "sources": [ "C07", "P07" ] }, { "id": "hc26b", "values": [ [ "Hot Chips", "Hot Chips" ], [ "2026", "2026" ], [ "BlueField-4 Processor Powers the AI Factory Operating System", "BlueField-4 Processor Powers the AI Factory Operating System" ], [ "Idan Burstein", "Idan Burstein" ], [ "BlueField-4", "BlueField-4" ], [ "Program + vendor technical disclosure", "程序＋厂商技术披露" ], [ "C07 P20", "C07 P20" ] ], "sources": [ "C07", "P20" ] }, { "id": "hc26s", "values": [ [ "Hot Chips", "Hot Chips" ], [ "2026", "2026" ], [ "Spectrum-X Multiplane Network Architecture", "Spectrum-X Multiplane Network Architecture" ], [ "Gilad Shainer", "Gilad Shainer" ], [ "Spectrum-X", "Spectrum-X" ], [ "Program + vendor technical disclosure", "程序＋厂商技术披露" ], [ "C07 P39", "C07 P39" ] ], "sources": [ "C07", "P39" ] }, { "id": "hc26l", "values": [ [ "Hot Chips", "Hot Chips" ], [ "2026", "2026" ], [ "Think Fast: LPU Accelerator for Heterogeneous Compute", "Think Fast: LPU Accelerator for Heterogeneous Compute" ], [ "Igor Arsovski; Santosh Raghavan", "Igor Arsovski; Santosh Raghavan" ], [ "LPX", "LPX" ], [ "Program + vendor technical disclosure", "程序＋厂商技术披露" ], [ "C07 P12", "C07 P12" ] ], "sources": [ "C07", "P12" ] }, { "id": "iss18", "values": [ [ "ISSCC", "ISSCC" ], [ "2018", "2018" ], [ "1.17pJ/b 25Gb/s/pin Ground-Referenced Single-Ended Serial Link", "1.17pJ/b 25Gb/s/pin Ground-Referenced Single-Ended Serial Link" ], [ "NVIDIA research team", "NVIDIA research team" ], [ "Signaling research", "信号研究" ], [ "Research circuit; not Grace production PHY", "研究电路；非 Grace 量产 PHY" ], [ "R07", "R07" ] ], "sources": [ "R07" ] }, { "id": "iss21", "values": [ [ "ISSCC", "ISSCC" ], [ "2021", "2021" ], [ "3.2 The A100 Datacenter GPU and Ampere Architecture", "3.2 The A100 Datacenter GPU and Ampere Architecture" ], [ "Jack Choquette et al.", "Jack Choquette et al." ], [ "A100", "A100" ], [ "Official press kit; direct implementation", "官方新闻资料；直接实现披露" ], [ "C08", "C08" ] ], "sources": [ "C08" ] }, { "id": "iss23", "values": [ [ "ISSCC", "ISSCC" ], [ "2023", "2023" ], [ "9.3 NVLink-C2C: A Coherent Off-Package Chip-to-Chip Interconnect with 40Gbps/pin Single-Ended Signaling", "9.3 NVLink-C2C: A Coherent Off-Package Chip-to-Chip Interconnect with 40Gbps/pin Single-Ended Signaling" ], [ "Ying Wei et al.", "Ying Wei et al." ], [ "Grace / Hopper C2C", "Grace / Hopper C2C" ], [ "Official press kit; PHY implementation", "官方新闻资料；PHY 实现" ], [ "C09", "C09" ] ], "sources": [ "C09" ] }, { "id": "iss26", "values": [ [ "ISSCC", "ISSCC" ], [ "2026", "2026" ], [ "17.1 GB10 SoC Built for AI Acceleration", "17.1 GB10 SoC Built for AI Acceleration" ], [ "Andi Skende; G. Rosseel; N. Pinckney", "Andi Skende; G. Rosseel; N. Pinckney" ], [ "GB10", "GB10" ], [ "Official program; full paper not inspected", "官方程序；未审阅论文全文" ], [ "C10", "C10" ] ], "sources": [ "C10" ] }, { "id": "isca17", "values": [ [ "ISCA", "ISCA" ], [ "2017", "2017" ], [ "MCM-GPU: Multi-Chip-Module GPUs for Continued Performance Scalability", "MCM-GPU: Multi-Chip-Module GPUs for Continued Performance Scalability" ], [ "NVIDIA research collaborators", "NVIDIA research collaborators" ], [ "Multi-chip GPU research", "多芯片 GPU 研究" ], [ "Research; no automatic Blackwell attribution", "研究；不自动归因于 Blackwell" ], [ "R01", "R01" ] ], "sources": [ "R01" ] }, { "id": "micro17a", "values": [ [ "MICRO", "MICRO" ], [ "2017", "2017" ], [ "Beyond the Socket: NUMA-Aware GPUs", "Beyond the Socket: NUMA-Aware GPUs" ], [ "Ugljesa Milic et al.", "Ugljesa Milic et al." ], [ "NUMA GPU research", "NUMA GPU 研究" ], [ "Research mechanism", "研究机制" ], [ "R02", "R02" ] ], "sources": [ "R02" ] }, { "id": "micro17b", "values": [ [ "MICRO", "MICRO" ], [ "2017", "2017" ], [ "Fine-Grained DRAM: Energy-Efficient DRAM for Extreme Bandwidth Systems", "Fine-Grained DRAM: Energy-Efficient DRAM for Extreme Bandwidth Systems" ], [ "Mike O’Connor et al.", "Mike O’Connor et al." ], [ "Memory research", "内存研究" ], [ "Research mechanism", "研究机制" ], [ "R03", "R03" ] ], "sources": [ "R03" ] }, { "id": "micro19", "values": [ [ "MICRO", "MICRO" ], [ "2019", "2019" ], [ "Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture", "Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture" ], [ "Yakun Sophia Shao et al.", "Yakun Sophia Shao et al." ], [ "Simba", "Simba" ], [ "Research accelerator", "研究加速器" ], [ "R10", "R10" ] ], "sources": [ "R10" ] }, { "id": "hpca15", "values": [ [ "HPCA", "HPCA" ], [ "2015", "2015" ], [ "Unlocking Bandwidth for GPUs in CC-NUMA Systems", "Unlocking Bandwidth for GPUs in CC-NUMA Systems" ], [ "Neha Agarwal et al.", "Neha Agarwal et al." ], [ "Coherent-memory placement", "一致性内存放置" ], [ "Research; not Grace specification", "研究；非 Grace 规格" ], [ "R04", "R04" ] ], "sources": [ "R04" ] }, { "id": "asplos15", "values": [ [ "ASPLOS", "ASPLOS" ], [ "2015", "2015" ], [ "Page Placement Strategies for GPUs within Heterogeneous Memory Systems", "Page Placement Strategies for GPUs within Heterogeneous Memory Systems" ], [ "Neha Agarwal et al.", "Neha Agarwal et al." ], [ "Page placement", "页面放置" ], [ "Research; not Grace specification", "研究；非 Grace 规格" ], [ "R05", "R05" ] ], "sources": [ "R05" ] }, { "id": "taco21", "values": [ [ "ACM TACO", "ACM TACO" ], [ "2021", "2021" ], [ "GPU Domain Specialization via Composable On-Package Architecture", "GPU Domain Specialization via Composable On-Package Architecture" ], [ "NVIDIA research collaborators", "NVIDIA research collaborators" ], [ "COPA-GPU", "COPA-GPU" ], [ "Research; journal, not a Big Four talk", "研究；期刊，非四大会演讲" ], [ "R06", "R06" ] ], "sources": [ "R06" ] }, { "id": "dac21", "values": [ [ "DAC / follow-up", "DAC / follow-up" ], [ "2021–2022", "2021–2022" ], [ "PrefixRL / arithmetic circuit design", "PrefixRL / arithmetic circuit design" ], [ "NVIDIA research team", "NVIDIA research team" ], [ "Hopper design flow", "Hopper design flow" ], [ "Explicit product adoption in follow-up", "后续资料明确产品采用" ], [ "P41", "P41" ] ], "sources": [ "P41" ] }, { "id": "gtc", "values": [ [ "GTC", "GTC" ], [ "2016–2026", "2016–2026" ], [ "P100 → Volta → Ampere → Hopper → Blackwell → Rubin", "P100 → Volta → Ampere → Hopper → Blackwell → Rubin" ], [ "NVIDIA", "NVIDIA" ], [ "Full platform", "完整平台" ], [ "Launch, architecture, software, roadmap", "发布、架构、软件、路线图" ], [ "P01 P02 P03 P04 E03 E07", "P01 P02 P03 P04 E03 E07" ] ], "sources": [ "P01", "P02", "P03", "P04", "E03", "E07" ] }, { "id": "computex", "values": [ [ "Computex", "Computex" ], [ "2025", "2025" ], [ "ConnectX-8 and NVLink Fusion", "ConnectX-8 与 NVLink Fusion" ], [ "NVIDIA", "NVIDIA" ], [ "Network and ecosystem", "网络与生态" ], [ "Product / ecosystem", "产品／生态" ], [ "P19 P27", "P19 P27" ] ], "sources": [ "P19", "P27" ] }, { "id": "sc20", "values": [ [ "SC20", "SC20" ], [ "2020", "2020" ], [ "A100 80 GB", "A100 80 GB" ], [ "NVIDIA", "NVIDIA" ], [ "A100 / HGX", "A100 / HGX" ], [ "Memory refresh announcement", "内存升级发布" ], [ "E20 P15", "E20 P15" ] ], "sources": [ "E20", "P15" ] }, { "id": "ocp", "values": [ [ "OCP Global Summit", "OCP Global Summit" ], [ "2025", "2025" ], [ "MGX, power delivery and AI-factory infrastructure", "MGX、供电与 AI 工厂基础设施" ], [ "NVIDIA / partners", "NVIDIA / partners" ], [ "Rack ecosystem; future power designs", "机架生态；未来供电设计" ], [ "System integration / roadmap", "系统集成／路线图" ], [ "E12", "E12" ] ], "sources": [ "E12" ] }, { "id": "aws", "values": [ [ "AWS re:Invent", "AWS re:Invent" ], [ "2025", "2025" ], [ "NVIDIA platforms and NVLink Fusion collaboration", "NVIDIA 平台与 NVLink Fusion 合作" ], [ "AWS / NVIDIA", "AWS / NVIDIA" ], [ "Blackwell / Fusion", "Blackwell / Fusion" ], [ "Ecosystem; GA verified separately", "生态；另行核对 GA" ], [ "E13 E16", "E13 E16" ] ], "sources": [ "E13", "E16" ] }, { "id": "ignite", "values": [ [ "Microsoft Ignite", "Microsoft Ignite" ], [ "2025", "2025" ], [ "Azure ND GB300 v6 GA", "Azure ND GB300 v6 GA" ], [ "Microsoft", "Microsoft" ], [ "GB300 NVL72", "GB300 NVL72" ], [ "Cloud GA", "云服务正式商用" ], [ "E15", "E15" ] ], "sources": [ "E15" ] }, { "id": "next", "values": [ [ "Google Cloud Next / update", "Google Cloud Next / update" ], [ "2025", "2025" ], [ "A4X / GB200", "A4X / GB200" ], [ "Google Cloud", "Google Cloud" ], [ "GB200", "GB200" ], [ "Cloud product; May GA update", "云产品；5 月 GA 更新" ], [ "E14", "E14" ] ], "sources": [ "E14" ] }, { "id": "mwc", "values": [ [ "MWC / AI-RAN", "MWC / AI-RAN" ], [ "2025", "2025" ], [ "Aerial AI-RAN architecture", "Aerial AI-RAN 架构" ], [ "NVIDIA / telecom partners", "NVIDIA / telecom partners" ], [ "Grace Hopper / Blackwell / BlueField", "Grace Hopper / Blackwell / BlueField" ], [ "Deployment architecture; not GPU core disclosure", "部署架构；非 GPU 核心披露" ], [ "E19", "E19" ] ], "sources": [ "E19" ] }, { "id": "infra", "values": [ [ "AI Infra Summit", "AI Infra Summit" ], [ "2026", "2026" ], [ "Vera Rubin / DSX efficiency", "Vera Rubin／DSX 能效" ], [ "NVIDIA", "NVIDIA" ], [ "Rubin", "Rubin" ], [ "System power and efficiency", "系统功耗与效率" ], [ "E11", "E11" ] ], "sources": [ "E11" ] } ], "panels": [ [ 0, 1, 2, 3 ], [ 0, 1, 4, 5, 6 ] ], "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources" }, "crosswalk": { "id": "crosswalk", "title": [ "Architecture, silicon and product names", "架构、芯片与产品名称" ], "headers": [ [ "Architecture / silicon", "架构／芯片" ], [ "Products", "产品" ], [ "Important distinction", "重要区别" ] ], "rows": [ { "id": "maxwell", "values": [ [ "Maxwell / GM200", "Maxwell / GM200" ], [ "M40", "M40" ], [ "No Tensor Cores", "无 Tensor Core" ] ], "sources": [ "P42" ] }, { "id": "pascal", "values": [ [ "Pascal / GP100", "Pascal / GP100" ], [ "P100", "P100" ], [ "GP100 differs from P4/P40 inference dies", "GP100 不同于 P4／P40 推理芯片" ] ], "sources": [ "P01", "E18" ] }, { "id": "volta", "values": [ [ "Volta / GV100", "Volta / GV100" ], [ "V100", "V100" ], [ "Turing T4 is a separate branch", "Turing T4 是另一分支" ] ], "sources": [ "P02", "P28" ] }, { "id": "ampere", "values": [ [ "Ampere / GA100", "Ampere / GA100" ], [ "A100", "A100" ], [ "GA100 differs from graphics Ampere", "GA100 不同于图形 Ampere" ] ], "sources": [ "P03" ] }, { "id": "hopper", "values": [ [ "Hopper / GH100", "Hopper / GH100" ], [ "H100 / H200", "H100 / H200" ], [ "GH200 names a Grace–Hopper combination", "GH200 表示 Grace–Hopper 组合" ] ], "sources": [ "P04", "P08", "P14" ] }, { "id": "blackwell", "values": [ [ "Datacenter Blackwell", "Datacenter Blackwell" ], [ "B200 / GB200", "B200 / GB200" ], [ "B200 GPU vs GB200 CPU–GPU construction", "B200 GPU 与 GB200 CPU–GPU 构造不同" ] ], "sources": [ "P05", "P16" ] }, { "id": "ultra", "values": [ [ "Blackwell Ultra", "Blackwell Ultra" ], [ "B300 / GB300", "B300 / GB300" ], [ "Not the same FP64 balance as B200", "FP64 配比不同于 B200" ] ], "sources": [ "P06", "P37" ] }, { "id": "rubin", "values": [ [ "Rubin + Vera", "Rubin + Vera" ], [ "Vera Rubin NVL72", "Vera Rubin NVL72" ], [ "Rubin GPU and Vera CPU are distinct chips", "Rubin GPU 与 Vera CPU 是不同芯片" ] ], "sources": [ "P11" ] }, { "id": "bf4", "values": [ [ "Grace-derived + ConnectX-9", "Grace-derived + ConnectX-9" ], [ "BlueField-4", "BlueField-4" ], [ "DPU CPU is not Vera", "DPU 的 CPU 不是 Vera" ] ], "sources": [ "P20" ] }, { "id": "lpx", "values": [ [ "LP30 / LPU", "LP30 / LPU" ], [ "Groq 3 LPX", "Groq 3 LPX" ], [ "Licensed inference technology; not a CUDA GPU", "获许可的推理技术；非 CUDA GPU" ] ], "sources": [ "P12", "E06" ] } ], "panels": [ [ 0, 1, 2 ] ], "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources" } }, "figures": { "fig.early": { "id": "fig.early", "title": [ "2016–2020: the GPU server becomes a fabric", "2016–2020：GPU 服务器形成互联域" ], "nodes": [ [ "cpu", [ "x86 host", "x86 主机" ], 0, 0 ], [ "gpus", [ "P100 / V100 / A100\nlocal HBM", "P100／V100／A100\n本地 HBM" ], 1, 0 ], [ "peer", [ "NVLink / NVSwitch\npeer GPU domain", "NVLink／NVSwitch\nGPU 对等域" ], 1, 1 ], [ "nic", [ "ConnectX NIC", "ConnectX 网卡" ], 0, 1 ], [ "net", [ "InfiniBand / Ethernet\ncluster fabric", "InfiniBand／以太网\n集群网络" ], 0, 2 ] ], "edges": [ [ "cpu", "gpus", [ "PCIe", "PCIe" ] ], [ "gpus", "peer", [ "scale-up", "纵向扩展" ] ], [ "gpus", "nic", [ "GPUDirect RDMA", "GPUDirect RDMA" ] ], [ "nic", "net", [ "scale-out", "横向扩展" ] ] ], "caption": [ "Logical connectivity, not a board wiring diagram. The GPU-local HBM and external network remain separate bandwidth domains.", "逻辑连接图，并非板级布线图。GPU 本地 HBM 与外部网络仍是不同带宽域。" ] }, "fig.hopper": { "id": "fig.hopper", "title": [ "2023–2024: coherent CPU–GPU memory", "2023–2024：一致性 CPU–GPU 内存" ], "nodes": [ [ "cpu", [ "Grace + LPDDR5X", "Grace＋LPDDR5X" ], 0, 0 ], [ "gpu", [ "Hopper + HBM", "Hopper＋HBM" ], 1, 0 ], [ "nv", [ "NVLink / NVSwitch\nGPU scale-up", "NVLink／NVSwitch\nGPU 纵向扩展" ], 1, 1 ], [ "nic", [ "ConnectX / SuperNIC", "ConnectX／SuperNIC" ], 1, 2 ], [ "dpu", [ "BlueField\ninfrastructure services", "BlueField\n基础设施服务" ], 0, 1 ], [ "net", [ "Quantum / Spectrum\nscale-out network", "Quantum／Spectrum\n横向扩展网络" ], 0, 2 ] ], "edges": [ [ "cpu", "gpu", [ "C2C 900 GB/s ↔", "C2C 900 GB/s ↔" ] ], [ "gpu", "nv", [ "NVLink", "NVLink" ] ], [ "gpu", "nic", [ "RDMA", "RDMA" ] ], [ "dpu", "net", [ "infrastructure", "基础设施" ] ], [ "nic", "net", [ "network", "网络" ] ] ], "caption": [ "C2C enables coherence; it does not make LPDDR latency or bandwidth equal to local HBM. Arrows show connectivity, not traffic direction.", "C2C 支持缓存一致性，但不会使 LPDDR 的延迟或带宽等同本地 HBM。箭头表示连接关系，而非流量方向。" ] }, "fig.blackwell": { "id": "fig.blackwell", "title": [ "2025: the NVL72 rack as a scale-up unit", "2025：NVL72 机架成为纵向扩展单元" ], "nodes": [ [ "cpu", [ "36 Grace CPUs", "36 颗 Grace CPU" ], 0, 0 ], [ "gpu", [ "72 Blackwell GPU packages\n2 compute dies each", "72 个 Blackwell GPU 封装\n每个含 2 颗计算裸片" ], 1, 0 ], [ "nv", [ "NVLink 5 / NVSwitch\n72-GPU domain", "NVLink 5／NVSwitch\n72 GPU 域" ], 1, 1 ], [ "dpu", [ "BlueField\nstorage / security", "BlueField\n存储／安全" ], 0, 1 ], [ "nic", [ "ConnectX / cloud NIC", "ConnectX／云厂商 NIC" ], 1, 2 ], [ "net", [ "Scale-out fabric\nSpectrum / Quantum / EFA", "横向扩展网络\nSpectrum／Quantum／EFA" ], 0, 2 ] ], "edges": [ [ "cpu", "gpu", [ "C2C", "C2C" ] ], [ "gpu", "nv", [ "1.8 TB/s ↔ per GPU", "每 GPU 双向 1.8 TB/s" ] ], [ "gpu", "nic", [ "RDMA", "RDMA" ] ], [ "nic", "net", [ "scale-out", "横向扩展" ] ], [ "dpu", "net", [ "services", "服务" ] ] ], "caption": [ "Cloud-specific networks are alternatives, not a claim that all three fabrics are installed together.", "云厂商网络表示可选实现，并非声称三种网络同时安装。" ] }, "fig.rubin": { "id": "fig.rubin", "title": [ "2026: heterogeneous serving and infrastructure", "2026：异构服务与基础设施" ], "nodes": [ [ "cpu", [ "Vera + SOCAMM2", "Vera＋SOCAMM2" ], 0, 0 ], [ "gpu", [ "Rubin + HBM4\nNVLink 6 / NVL72", "Rubin＋HBM4\nNVLink 6／NVL72" ], 1, 0 ], [ "dpu", [ "BlueField-4 / STX\ncontext storage", "BlueField-4／STX\n上下文存储" ], 0, 1 ], [ "nic", [ "ConnectX-9\nSpectrum-X / Quantum", "ConnectX-9\nSpectrum-X／Quantum" ], 1, 1 ], [ "lpu", [ "Groq 3 LPX\nSRAM-centric execution", "Groq 3 LPX\nSRAM 型执行" ], 1, 2 ], [ "sw", [ "Dynamo / serving scheduler\nplacement and data movement", "Dynamo／服务调度器\n放置与数据搬移" ], 0, 2 ] ], "edges": [ [ "cpu", "gpu", [ "C2C 1.8 TB/s ↔", "C2C 1.8 TB/s ↔" ] ], [ "gpu", "nic", [ "scale-out", "横向扩展" ] ], [ "dpu", "nic", [ "context traffic", "上下文流量" ] ], [ "lpu", "nic", [ "complementary tier", "互补执行层" ] ], [ "sw", "lpu", [ "schedule", "调度" ] ], [ "sw", "dpu", [ "placement", "放置" ] ] ], "caption": [ "Conceptual placement map; the LPX edge does not assert a direct NVLink or coherent memory connection to Rubin.", "概念性放置图；LPX 连线并不表示其与 Rubin 存在直接 NVLink 或一致性内存连接。" ] } }, "claims": { "headline.pascal.0": { "value": "2015–2016", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Era", "source": [ "P01", "P42" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "pascal" }, "headline.pascal.1": { "value": "M40 → P100", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Flagship", "source": [ "P01", "P42" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "pascal" }, "headline.pascal.2": { "value": "HBM2; NVLink 1", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Architectural change", "source": [ "P01", "P42" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "pascal" }, "headline.pascal.3": { "value": "Move beyond host-mediated PCIe data movement", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "System implication", "source": [ "P01", "P42" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "pascal" }, "headline.volta.0": { "value": "2017–2019", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Era", "source": [ "P02" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "volta" }, "headline.volta.1": { "value": "V100 / DGX-2", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Flagship", "source": [ "P02" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "volta" }, "headline.volta.2": { "value": "Tensor Cores; NVSwitch", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Architectural change", "source": [ "P02" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "volta" }, "headline.volta.3": { "value": "Matrix acceleration plus a switched GPU domain", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "System implication", "source": [ "P02" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "volta" }, "headline.ampere.0": { "value": "2020–2021", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Era", "source": [ "P03", "C08" ], "disclosure_date": "2020", "status": "historical shipping", "scope": "ampere" }, "headline.ampere.1": { "value": "A100", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Flagship", "source": [ "P03", "C08" ], "disclosure_date": "2020", "status": "historical shipping", "scope": "ampere" }, "headline.ampere.2": { "value": "BF16 / TF32 / FP64 Tensor Cores; MIG", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Architectural change", "source": [ "P03", "C08" ], "disclosure_date": "2020", "status": "historical shipping", "scope": "ampere" }, "headline.ampere.3": { "value": "One architecture serves AI, HPC and isolated instances", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "System implication", "source": [ "P03", "C08" ], "disclosure_date": "2020", "status": "historical shipping", "scope": "ampere" }, "headline.hopper.0": { "value": "2022–2024", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Era", "source": [ "P04", "P08", "P14" ], "disclosure_date": "2022–2024", "status": "shipping", "scope": "hopper" }, "headline.hopper.1": { "value": "H100 / H200 / GH200", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Flagship", "source": [ "P04", "P08", "P14" ], "disclosure_date": "2022–2024", "status": "shipping", "scope": "hopper" }, "headline.hopper.2": { "value": "FP8; TMA; clusters; coherent C2C", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Architectural change", "source": [ "P04", "P08", "P14" ], "disclosure_date": "2022–2024", "status": "shipping", "scope": "hopper" }, "headline.hopper.3": { "value": "Hide movement and extend the memory hierarchy", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "System implication", "source": [ "P04", "P08", "P14" ], "disclosure_date": "2022–2024", "status": "shipping", "scope": "hopper" }, "headline.blackwell.0": { "value": "2024–2025", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Era", "source": [ "P05", "P06", "P37" ], "disclosure_date": "2024–2025", "status": "shipping", "scope": "blackwell" }, "headline.blackwell.1": { "value": "B200 / B300 / GB200 / GB300", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Flagship", "source": [ "P05", "P06", "P37" ], "disclosure_date": "2024–2025", "status": "shipping", "scope": "blackwell" }, "headline.blackwell.2": { "value": "Two compute dies; FP4; NVL72", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Architectural change", "source": [ "P05", "P06", "P37" ], "disclosure_date": "2024–2025", "status": "shipping", "scope": "blackwell" }, "headline.blackwell.3": { "value": "Package and rack become coordinated design units", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "System implication", "source": [ "P05", "P06", "P37" ], "disclosure_date": "2024–2025", "status": "shipping", "scope": "blackwell" }, "headline.rubin.0": { "value": "2026", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Era", "source": [ "P07", "P10", "P11", "P12", "E08", "E09" ], "disclosure_date": "2026", "status": "production / preview; GA varies", "scope": "rubin" }, "headline.rubin.1": { "value": "Vera Rubin / BlueField-4 / LPX", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Flagship", "source": [ "P07", "P10", "P11", "P12", "E08", "E09" ], "disclosure_date": "2026", "status": "production / preview; GA varies", "scope": "rubin" }, "headline.rubin.2": { "value": "HBM4; Olympus; NVLink 6; inference specialization", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Architectural change", "source": [ "P07", "P10", "P11", "P12", "E08", "E09" ], "disclosure_date": "2026", "status": "production / preview; GA varies", "scope": "rubin" }, "headline.rubin.3": { "value": "Co-design across compute, fabric, storage and serving", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "System implication", "source": [ "P07", "P10", "P11", "P12", "E08", "E09" ], "disclosure_date": "2026", "status": "production / preview; GA varies", "scope": "rubin" }, "gpu.m40.0": { "value": "M40", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Generation", "source": [ "P42", "E18" ], "disclosure_date": "2015", "status": "historical shipping", "scope": "m40" }, "gpu.m40.1": { "value": "GM200 / Maxwell", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Codename / architecture", "source": [ "P42", "E18" ], "disclosure_date": "2015", "status": "historical shipping", "scope": "m40" }, "gpu.m40.2": { "value": "2015", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "GA / milestone", "source": [ "P42", "E18" ], "disclosure_date": "2015", "status": "historical shipping", "scope": "m40" }, "gpu.m40.3": { "value": "Historical shipping", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Status", "source": [ "P42", "E18" ], "disclosure_date": "2015", "status": "historical shipping", "scope": "m40" }, "gpu.m40.4": { "value": "28 nm", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Process", "source": [ "P42", "E18" ], "disclosure_date": "2015", "status": "historical shipping", "scope": "m40" }, "gpu.m40.5": { "value": "1 die; GDDR board", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dies and packaging", "source": [ "P42", "E18" ], "disclosure_date": "2015", "status": "historical shipping", "scope": "m40" }, "gpu.m40.6": { "value": "24 SM / 3072 CUDA", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Compute units", "source": [ "P42", "E18" ], "disclosure_date": "2015", "status": "historical shipping", "scope": "m40" }, "gpu.m40.7": { "value": "n/a", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dense BF16", "source": [ "P42", "E18" ], "disclosure_date": "2015", "status": "historical shipping", "scope": "m40" }, "gpu.m40.8": { "value": "n/a", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dense FP8", "source": [ "P42", "E18" ], "disclosure_date": "2015", "status": "historical shipping", "scope": "m40" }, "gpu.m40.9": { "value": "n/a", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dense FP6 / FP4", "source": [ "P42", "E18" ], "disclosure_date": "2015", "status": "historical shipping", "scope": "m40" }, "gpu.m40.10": { "value": "n/d / n/a", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "FP64 vector / matrix", "source": [ "P42", "E18" ], "disclosure_date": "2015", "status": "historical shipping", "scope": "m40" }, "gpu.m40.11": { "value": "n/a; GDDR5 24 GB; 0.288 TB/s", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "HBM: generation; stacks; GB; TB/s", "source": [ "P42", "E18" ], "disclosure_date": "2015", "status": "historical shipping", "scope": "m40" }, "gpu.m40.12": { "value": "3 MB", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Last-level cache", "source": [ "P42", "E18" ], "disclosure_date": "2015", "status": "historical shipping", "scope": "m40" }, "gpu.m40.13": { "value": "n/a", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Scale-up: links; GB/s one-way; domain", "source": [ "P42", "E18" ], "disclosure_date": "2015", "status": "historical shipping", "scope": "m40" }, "gpu.m40.14": { "value": "PCIe 3 x16", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Host link", "source": [ "P42", "E18" ], "disclosure_date": "2015", "status": "historical shipping", "scope": "m40" }, "gpu.m40.15": { "value": "250 W; air", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "TBP and cooling", "source": [ "P42", "E18" ], "disclosure_date": "2015", "status": "historical shipping", "scope": "m40" }, "gpu.m40.16": { "value": "PCIe", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Form factor", "source": [ "P42", "E18" ], "disclosure_date": "2015", "status": "historical shipping", "scope": "m40" }, "gpu.p100.0": { "value": "P100 SXM2", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Generation", "source": [ "P01", "P36" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "p100" }, "gpu.p100.1": { "value": "GP100 / Pascal", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Codename / architecture", "source": [ "P01", "P36" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "p100" }, "gpu.p100.2": { "value": "2016", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "GA / milestone", "source": [ "P01", "P36" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "p100" }, "gpu.p100.3": { "value": "Historical shipping", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Status", "source": [ "P01", "P36" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "p100" }, "gpu.p100.4": { "value": "16 nm", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Process", "source": [ "P01", "P36" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "p100" }, "gpu.p100.5": { "value": "1 die + HBM interposer", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dies and packaging", "source": [ "P01", "P36" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "p100" }, "gpu.p100.6": { "value": "56 SM / 3584 CUDA", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Compute units", "source": [ "P01", "P36" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "p100" }, "gpu.p100.7": { "value": "n/a", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dense BF16", "source": [ "P01", "P36" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "p100" }, "gpu.p100.8": { "value": "n/a", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dense FP8", "source": [ "P01", "P36" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "p100" }, "gpu.p100.9": { "value": "n/a", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dense FP6 / FP4", "source": [ "P01", "P36" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "p100" }, "gpu.p100.10": { "value": "5.3 TF / n/a", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "FP64 vector / matrix", "source": [ "P01", "P36" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "p100" }, "gpu.p100.11": { "value": "HBM2; 4; 16; 0.732", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "HBM: generation; stacks; GB; TB/s", "source": [ "P01", "P36" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "p100" }, "gpu.p100.12": { "value": "4 MB", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Last-level cache", "source": [ "P01", "P36" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "p100" }, "gpu.p100.13": { "value": "4; 80; server topology", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Scale-up: links; GB/s one-way; domain", "source": [ "P01", "P36" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "p100" }, "gpu.p100.14": { "value": "PCIe 3", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Host link", "source": [ "P01", "P36" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "p100" }, "gpu.p100.15": { "value": "300 W; platform-dependent", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "TBP and cooling", "source": [ "P01", "P36" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "p100" }, "gpu.p100.16": { "value": "SXM2", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Form factor", "source": [ "P01", "P36" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "p100" }, "gpu.v100.0": { "value": "V100 SXM2", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Generation", "source": [ "P02", "P35" ], "disclosure_date": "2017–2018", "status": "historical shipping", "scope": "v100" }, "gpu.v100.1": { "value": "GV100 / Volta", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Codename / architecture", "source": [ "P02", "P35" ], "disclosure_date": "2017–2018", "status": "historical shipping", "scope": "v100" }, "gpu.v100.2": { "value": "2017", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "GA / milestone", "source": [ "P02", "P35" ], "disclosure_date": "2017–2018", "status": "historical shipping", "scope": "v100" }, "gpu.v100.3": { "value": "Historical shipping", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Status", "source": [ "P02", "P35" ], "disclosure_date": "2017–2018", "status": "historical shipping", "scope": "v100" }, "gpu.v100.4": { "value": "12 nm", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Process", "source": [ "P02", "P35" ], "disclosure_date": "2017–2018", "status": "historical shipping", "scope": "v100" }, "gpu.v100.5": { "value": "1 die + HBM interposer", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dies and packaging", "source": [ "P02", "P35" ], "disclosure_date": "2017–2018", "status": "historical shipping", "scope": "v100" }, "gpu.v100.6": { "value": "80 SM / 640 TC", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Compute units", "source": [ "P02", "P35" ], "disclosure_date": "2017–2018", "status": "historical shipping", "scope": "v100" }, "gpu.v100.7": { "value": "n/a", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dense BF16", "source": [ "P02", "P35" ], "disclosure_date": "2017–2018", "status": "historical shipping", "scope": "v100" }, "gpu.v100.8": { "value": "n/a", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dense FP8", "source": [ "P02", "P35" ], "disclosure_date": "2017–2018", "status": "historical shipping", "scope": "v100" }, "gpu.v100.9": { "value": "n/a", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dense FP6 / FP4", "source": [ "P02", "P35" ], "disclosure_date": "2017–2018", "status": "historical shipping", "scope": "v100" }, "gpu.v100.10": { "value": "7.8 TF / n/a", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "FP64 vector / matrix", "source": [ "P02", "P35" ], "disclosure_date": "2017–2018", "status": "historical shipping", "scope": "v100" }, "gpu.v100.11": { "value": "HBM2; 4; 16/32; 0.900", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "HBM: generation; stacks; GB; TB/s", "source": [ "P02", "P35" ], "disclosure_date": "2017–2018", "status": "historical shipping", "scope": "v100" }, "gpu.v100.12": { "value": "6 MB", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Last-level cache", "source": [ "P02", "P35" ], "disclosure_date": "2017–2018", "status": "historical shipping", "scope": "v100" }, "gpu.v100.13": { "value": "6; 150; up to 16 via NVSwitch", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Scale-up: links; GB/s one-way; domain", "source": [ "P02", "P35" ], "disclosure_date": "2017–2018", "status": "historical shipping", "scope": "v100" }, "gpu.v100.14": { "value": "PCIe 3", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Host link", "source": [ "P02", "P35" ], "disclosure_date": "2017–2018", "status": "historical shipping", "scope": "v100" }, "gpu.v100.15": { "value": "300 W; platform-dependent", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "TBP and cooling", "source": [ "P02", "P35" ], "disclosure_date": "2017–2018", "status": "historical shipping", "scope": "v100" }, "gpu.v100.16": { "value": "SXM2", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Form factor", "source": [ "P02", "P35" ], "disclosure_date": "2017–2018", "status": "historical shipping", "scope": "v100" }, "gpu.a100.0": { "value": "A100 SXM 80 GB", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Generation", "source": [ "P03", "P15", "P34" ], "disclosure_date": "2020", "status": "historical shipping", "scope": "a100" }, "gpu.a100.1": { "value": "GA100 / Ampere", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Codename / architecture", "source": [ "P03", "P15", "P34" ], "disclosure_date": "2020", "status": "historical shipping", "scope": "a100" }, "gpu.a100.2": { "value": "2020", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "GA / milestone", "source": [ "P03", "P15", "P34" ], "disclosure_date": "2020", "status": "historical shipping", "scope": "a100" }, "gpu.a100.3": { "value": "Historical shipping", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Status", "source": [ "P03", "P15", "P34" ], "disclosure_date": "2020", "status": "historical shipping", "scope": "a100" }, "gpu.a100.4": { "value": "7 nm", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Process", "source": [ "P03", "P15", "P34" ], "disclosure_date": "2020", "status": "historical shipping", "scope": "a100" }, "gpu.a100.5": { "value": "1 die + HBM interposer", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dies and packaging", "source": [ "P03", "P15", "P34" ], "disclosure_date": "2020", "status": "historical shipping", "scope": "a100" }, "gpu.a100.6": { "value": "108 SM / 432 TC", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Compute units", "source": [ "P03", "P15", "P34" ], "disclosure_date": "2020", "status": "historical shipping", "scope": "a100" }, "gpu.a100.7": { "value": "312 TF", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dense BF16", "source": [ "P03", "P15", "P34" ], "disclosure_date": "2020", "status": "historical shipping", "scope": "a100" }, "gpu.a100.8": { "value": "n/a", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dense FP8", "source": [ "P03", "P15", "P34" ], "disclosure_date": "2020", "status": "historical shipping", "scope": "a100" }, "gpu.a100.9": { "value": "n/a", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dense FP6 / FP4", "source": [ "P03", "P15", "P34" ], "disclosure_date": "2020", "status": "historical shipping", "scope": "a100" }, "gpu.a100.10": { "value": "9.7 / 19.5 TF", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "FP64 vector / matrix", "source": [ "P03", "P15", "P34" ], "disclosure_date": "2020", "status": "historical shipping", "scope": "a100" }, "gpu.a100.11": { "value": "HBM2e; 5 active; 80; 2.039", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "HBM: generation; stacks; GB; TB/s", "source": [ "P03", "P15", "P34" ], "disclosure_date": "2020", "status": "historical shipping", "scope": "a100" }, "gpu.a100.12": { "value": "40 MB", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Last-level cache", "source": [ "P03", "P15", "P34" ], "disclosure_date": "2020", "status": "historical shipping", "scope": "a100" }, "gpu.a100.13": { "value": "12; 300; 8-GPU HGX", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Scale-up: links; GB/s one-way; domain", "source": [ "P03", "P15", "P34" ], "disclosure_date": "2020", "status": "historical shipping", "scope": "a100" }, "gpu.a100.14": { "value": "PCIe 4", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Host link", "source": [ "P03", "P15", "P34" ], "disclosure_date": "2020", "status": "historical shipping", "scope": "a100" }, "gpu.a100.15": { "value": "400 W; platform-dependent", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "TBP and cooling", "source": [ "P03", "P15", "P34" ], "disclosure_date": "2020", "status": "historical shipping", "scope": "a100" }, "gpu.a100.16": { "value": "SXM4", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Form factor", "source": [ "P03", "P15", "P34" ], "disclosure_date": "2020", "status": "historical shipping", "scope": "a100" }, "gpu.h100.0": { "value": "H100 SXM", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Generation", "source": [ "P04", "P13", "P33" ], "disclosure_date": "2022", "status": "shipping", "scope": "h100" }, "gpu.h100.1": { "value": "GH100 / Hopper", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Codename / architecture", "source": [ "P04", "P13", "P33" ], "disclosure_date": "2022", "status": "shipping", "scope": "h100" }, "gpu.h100.2": { "value": "2022", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "GA / milestone", "source": [ "P04", "P13", "P33" ], "disclosure_date": "2022", "status": "shipping", "scope": "h100" }, "gpu.h100.3": { "value": "Shipping", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Status", "source": [ "P04", "P13", "P33" ], "disclosure_date": "2022", "status": "shipping", "scope": "h100" }, "gpu.h100.4": { "value": "4N", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Process", "source": [ "P04", "P13", "P33" ], "disclosure_date": "2022", "status": "shipping", "scope": "h100" }, "gpu.h100.5": { "value": "1 die + HBM interposer", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dies and packaging", "source": [ "P04", "P13", "P33" ], "disclosure_date": "2022", "status": "shipping", "scope": "h100" }, "gpu.h100.6": { "value": "132 SM / 528 TC", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Compute units", "source": [ "P04", "P13", "P33" ], "disclosure_date": "2022", "status": "shipping", "scope": "h100" }, "gpu.h100.7": { "value": "989 TF", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dense BF16", "source": [ "P04", "P13", "P33" ], "disclosure_date": "2022", "status": "shipping", "scope": "h100" }, "gpu.h100.8": { "value": "1.979 PF", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dense FP8", "source": [ "P04", "P13", "P33" ], "disclosure_date": "2022", "status": "shipping", "scope": "h100" }, "gpu.h100.9": { "value": "n/a", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dense FP6 / FP4", "source": [ "P04", "P13", "P33" ], "disclosure_date": "2022", "status": "shipping", "scope": "h100" }, "gpu.h100.10": { "value": "34 / 67 TF", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "FP64 vector / matrix", "source": [ "P04", "P13", "P33" ], "disclosure_date": "2022", "status": "shipping", "scope": "h100" }, "gpu.h100.11": { "value": "HBM3; 5 active; 80; 3.35", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "HBM: generation; stacks; GB; TB/s", "source": [ "P04", "P13", "P33" ], "disclosure_date": "2022", "status": "shipping", "scope": "h100" }, "gpu.h100.12": { "value": "50 MB", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Last-level cache", "source": [ "P04", "P13", "P33" ], "disclosure_date": "2022", "status": "shipping", "scope": "h100" }, "gpu.h100.13": { "value": "18; 450; 8-GPU HGX", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Scale-up: links; GB/s one-way; domain", "source": [ "P04", "P13", "P33" ], "disclosure_date": "2022", "status": "shipping", "scope": "h100" }, "gpu.h100.14": { "value": "PCIe 5", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Host link", "source": [ "P04", "P13", "P33" ], "disclosure_date": "2022", "status": "shipping", "scope": "h100" }, "gpu.h100.15": { "value": "700 W; platform-dependent", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "TBP and cooling", "source": [ "P04", "P13", "P33" ], "disclosure_date": "2022", "status": "shipping", "scope": "h100" }, "gpu.h100.16": { "value": "SXM5", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Form factor", "source": [ "P04", "P13", "P33" ], "disclosure_date": "2022", "status": "shipping", "scope": "h100" }, "gpu.h200.0": { "value": "H200 SXM", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Generation", "source": [ "P14", "P33" ], "disclosure_date": "2024", "status": "shipping", "scope": "h200" }, "gpu.h200.1": { "value": "GH100 / Hopper", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Codename / architecture", "source": [ "P14", "P33" ], "disclosure_date": "2024", "status": "shipping", "scope": "h200" }, "gpu.h200.2": { "value": "2024", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "GA / milestone", "source": [ "P14", "P33" ], "disclosure_date": "2024", "status": "shipping", "scope": "h200" }, "gpu.h200.3": { "value": "Shipping", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Status", "source": [ "P14", "P33" ], "disclosure_date": "2024", "status": "shipping", "scope": "h200" }, "gpu.h200.4": { "value": "4N", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Process", "source": [ "P14", "P33" ], "disclosure_date": "2024", "status": "shipping", "scope": "h200" }, "gpu.h200.5": { "value": "Hopper + HBM3e", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dies and packaging", "source": [ "P14", "P33" ], "disclosure_date": "2024", "status": "shipping", "scope": "h200" }, "gpu.h200.6": { "value": "132 SM / 528 TC", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Compute units", "source": [ "P14", "P33" ], "disclosure_date": "2024", "status": "shipping", "scope": "h200" }, "gpu.h200.7": { "value": "989 TF", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dense BF16", "source": [ "P14", "P33" ], "disclosure_date": "2024", "status": "shipping", "scope": "h200" }, "gpu.h200.8": { "value": "1.979 PF", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dense FP8", "source": [ "P14", "P33" ], "disclosure_date": "2024", "status": "shipping", "scope": "h200" }, "gpu.h200.9": { "value": "n/a", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dense FP6 / FP4", "source": [ "P14", "P33" ], "disclosure_date": "2024", "status": "shipping", "scope": "h200" }, "gpu.h200.10": { "value": "34 / 67 TF", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "FP64 vector / matrix", "source": [ "P14", "P33" ], "disclosure_date": "2024", "status": "shipping", "scope": "h200" }, "gpu.h200.11": { "value": "HBM3e; n/d; 141; 4.8", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "HBM: generation; stacks; GB; TB/s", "source": [ "P14", "P33" ], "disclosure_date": "2024", "status": "shipping", "scope": "h200" }, "gpu.h200.12": { "value": "50 MB", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Last-level cache", "source": [ "P14", "P33" ], "disclosure_date": "2024", "status": "shipping", "scope": "h200" }, "gpu.h200.13": { "value": "18; 450; 8-GPU HGX", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Scale-up: links; GB/s one-way; domain", "source": [ "P14", "P33" ], "disclosure_date": "2024", "status": "shipping", "scope": "h200" }, "gpu.h200.14": { "value": "PCIe 5", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Host link", "source": [ "P14", "P33" ], "disclosure_date": "2024", "status": "shipping", "scope": "h200" }, "gpu.h200.15": { "value": "700 W; platform-dependent", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "TBP and cooling", "source": [ "P14", "P33" ], "disclosure_date": "2024", "status": "shipping", "scope": "h200" }, "gpu.h200.16": { "value": "SXM5", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Form factor", "source": [ "P14", "P33" ], "disclosure_date": "2024", "status": "shipping", "scope": "h200" }, "gpu.b200.0": { "value": "B200 / HGX basis", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Generation", "source": [ "P05", "P16", "P32", "P37" ], "disclosure_date": "2024–2025", "status": "shipping", "scope": "b200" }, "gpu.b200.1": { "value": "Blackwell", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Codename / architecture", "source": [ "P05", "P16", "P32", "P37" ], "disclosure_date": "2024–2025", "status": "shipping", "scope": "b200" }, "gpu.b200.2": { "value": "2024–2025", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "GA / milestone", "source": [ "P05", "P16", "P32", "P37" ], "disclosure_date": "2024–2025", "status": "shipping", "scope": "b200" }, "gpu.b200.3": { "value": "Shipping", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Status", "source": [ "P05", "P16", "P32", "P37" ], "disclosure_date": "2024–2025", "status": "shipping", "scope": "b200" }, "gpu.b200.4": { "value": "4NP", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Process", "source": [ "P05", "P16", "P32", "P37" ], "disclosure_date": "2024–2025", "status": "shipping", "scope": "b200" }, "gpu.b200.5": { "value": "2 compute dies; NV-HBI; HBM", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dies and packaging", "source": [ "P05", "P16", "P32", "P37" ], "disclosure_date": "2024–2025", "status": "shipping", "scope": "b200" }, "gpu.b200.6": { "value": "SKU-dependent", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Compute units", "source": [ "P05", "P16", "P32", "P37" ], "disclosure_date": "2024–2025", "status": "shipping", "scope": "b200" }, "gpu.b200.7": { "value": "2.25 PF", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dense BF16", "source": [ "P05", "P16", "P32", "P37" ], "disclosure_date": "2024–2025", "status": "shipping", "scope": "b200" }, "gpu.b200.8": { "value": "4.5 PF", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dense FP8", "source": [ "P05", "P16", "P32", "P37" ], "disclosure_date": "2024–2025", "status": "shipping", "scope": "b200" }, "gpu.b200.9": { "value": "4.5 / 9 PF", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dense FP6 / FP4", "source": [ "P05", "P16", "P32", "P37" ], "disclosure_date": "2024–2025", "status": "shipping", "scope": "b200" }, "gpu.b200.10": { "value": "37 TF published FP64; split n/d", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "FP64 vector / matrix", "source": [ "P05", "P16", "P32", "P37" ], "disclosure_date": "2024–2025", "status": "shipping", "scope": "b200" }, "gpu.b200.11": { "value": "HBM3e; 8; 180; 8", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "HBM: generation; stacks; GB; TB/s", "source": [ "P05", "P16", "P32", "P37" ], "disclosure_date": "2024–2025", "status": "shipping", "scope": "b200" }, "gpu.b200.12": { "value": "126 MB GB200 reference; SKU-specific", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Last-level cache", "source": [ "P05", "P16", "P32", "P37" ], "disclosure_date": "2024–2025", "status": "shipping", "scope": "b200" }, "gpu.b200.13": { "value": "18; 900; 8-GPU HGX", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Scale-up: links; GB/s one-way; domain", "source": [ "P05", "P16", "P32", "P37" ], "disclosure_date": "2024–2025", "status": "shipping", "scope": "b200" }, "gpu.b200.14": { "value": "PCIe 6", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Host link", "source": [ "P05", "P16", "P32", "P37" ], "disclosure_date": "2024–2025", "status": "shipping", "scope": "b200" }, "gpu.b200.15": { "value": "Up to 1000 W module; cooling by system", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "TBP and cooling", "source": [ "P05", "P16", "P32", "P37" ], "disclosure_date": "2024–2025", "status": "shipping", "scope": "b200" }, "gpu.b200.16": { "value": "SXM", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Form factor", "source": [ "P05", "P16", "P32", "P37" ], "disclosure_date": "2024–2025", "status": "shipping", "scope": "b200" }, "gpu.b300.0": { "value": "B300 / HGX basis", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Generation", "source": [ "P06", "P17", "P37" ], "disclosure_date": "2025", "status": "shipping", "scope": "b300" }, "gpu.b300.1": { "value": "Blackwell Ultra", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Codename / architecture", "source": [ "P06", "P17", "P37" ], "disclosure_date": "2025", "status": "shipping", "scope": "b300" }, "gpu.b300.2": { "value": "2025", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "GA / milestone", "source": [ "P06", "P17", "P37" ], "disclosure_date": "2025", "status": "shipping", "scope": "b300" }, "gpu.b300.3": { "value": "Shipping", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Status", "source": [ "P06", "P17", "P37" ], "disclosure_date": "2025", "status": "shipping", "scope": "b300" }, "gpu.b300.4": { "value": "4NP", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Process", "source": [ "P06", "P17", "P37" ], "disclosure_date": "2025", "status": "shipping", "scope": "b300" }, "gpu.b300.5": { "value": "2 compute dies; NV-HBI; HBM", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dies and packaging", "source": [ "P06", "P17", "P37" ], "disclosure_date": "2025", "status": "shipping", "scope": "b300" }, "gpu.b300.6": { "value": "Up to 160 SM / 640 TC; SKU-dependent", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Compute units", "source": [ "P06", "P17", "P37" ], "disclosure_date": "2025", "status": "shipping", "scope": "b300" }, "gpu.b300.7": { "value": "2.25 PF", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dense BF16", "source": [ "P06", "P17", "P37" ], "disclosure_date": "2025", "status": "shipping", "scope": "b300" }, "gpu.b300.8": { "value": "4.5 PF", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dense FP8", "source": [ "P06", "P17", "P37" ], "disclosure_date": "2025", "status": "shipping", "scope": "b300" }, "gpu.b300.9": { "value": "4.5 / 13.5 PF", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dense FP6 / FP4", "source": [ "P06", "P17", "P37" ], "disclosure_date": "2025", "status": "shipping", "scope": "b300" }, "gpu.b300.10": { "value": "1.25 TF published FP64; split n/d", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "FP64 vector / matrix", "source": [ "P06", "P17", "P37" ], "disclosure_date": "2025", "status": "shipping", "scope": "b300" }, "gpu.b300.11": { "value": "HBM3e; 8; up to 288; 8", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "HBM: generation; stacks; GB; TB/s", "source": [ "P06", "P17", "P37" ], "disclosure_date": "2025", "status": "shipping", "scope": "b300" }, "gpu.b300.12": { "value": "n/d", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Last-level cache", "source": [ "P06", "P17", "P37" ], "disclosure_date": "2025", "status": "shipping", "scope": "b300" }, "gpu.b300.13": { "value": "18; 900; 8-GPU HGX", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Scale-up: links; GB/s one-way; domain", "source": [ "P06", "P17", "P37" ], "disclosure_date": "2025", "status": "shipping", "scope": "b300" }, "gpu.b300.14": { "value": "PCIe 6", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Host link", "source": [ "P06", "P17", "P37" ], "disclosure_date": "2025", "status": "shipping", "scope": "b300" }, "gpu.b300.15": { "value": "n/d at uniform module basis", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "TBP and cooling", "source": [ "P06", "P17", "P37" ], "disclosure_date": "2025", "status": "shipping", "scope": "b300" }, "gpu.b300.16": { "value": "SXM", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Form factor", "source": [ "P06", "P17", "P37" ], "disclosure_date": "2025", "status": "shipping", "scope": "b300" }, "gpu.rubin.0": { "value": "Rubin / chip peak", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Generation", "source": [ "P07", "P11", "P37", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "rubin" }, "gpu.rubin.1": { "value": "Rubin", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Codename / architecture", "source": [ "P07", "P11", "P37", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "rubin" }, "gpu.rubin.2": { "value": "2026 preview; GA n/d", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "GA / milestone", "source": [ "P07", "P11", "P37", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "rubin" }, "gpu.rubin.3": { "value": "Production / preview", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Status", "source": [ "P07", "P11", "P37", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "rubin" }, "gpu.rubin.4": { "value": "n/d", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Process", "source": [ "P07", "P11", "P37", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "rubin" }, "gpu.rubin.5": { "value": "2 compute dies; NV-HBI; HBM4", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dies and packaging", "source": [ "P07", "P11", "P37", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "rubin" }, "gpu.rubin.6": { "value": "224 SM / 896 TC", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Compute units", "source": [ "P07", "P11", "P37", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "rubin" }, "gpu.rubin.7": { "value": "4 PF", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dense BF16", "source": [ "P07", "P11", "P37", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "rubin" }, "gpu.rubin.8": { "value": "17.5 PF training", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dense FP8", "source": [ "P07", "P11", "P37", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "rubin" }, "gpu.rubin.9": { "value": "17.5 / 35 PF training", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Dense FP6 / FP4", "source": [ "P07", "P11", "P37", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "rubin" }, "gpu.rubin.10": { "value": "33 TF native; 200 TF DGEMM emulated", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "FP64 vector / matrix", "source": [ "P07", "P11", "P37", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "rubin" }, "gpu.rubin.11": { "value": "HBM4; 8; 288; 22", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "HBM: generation; stacks; GB; TB/s", "source": [ "P07", "P11", "P37", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "rubin" }, "gpu.rubin.12": { "value": "n/d", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Last-level cache", "source": [ "P07", "P11", "P37", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "rubin" }, "gpu.rubin.13": { "value": "n/d; 1800 peak; NVL72", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Scale-up: links; GB/s one-way; domain", "source": [ "P07", "P11", "P37", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "rubin" }, "gpu.rubin.14": { "value": "PCIe 6", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Host link", "source": [ "P07", "P11", "P37", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "rubin" }, "gpu.rubin.15": { "value": "Configuration-dependent; liquid", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "TBP and cooling", "source": [ "P07", "P11", "P37", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "rubin" }, "gpu.rubin.16": { "value": "NVL / HGX", "basis": "Per GPU package; dense tensor rates unless labelled; FP64 split explicit; HBM bandwidth decimal TB/s; scale-up GB/s per direction", "field": "Form factor", "source": [ "P07", "P11", "P37", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "rubin" }, "cpu.grace.0": { "value": "Grace", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Generation", "source": [ "P08", "P09", "P11" ], "disclosure_date": "2022–2023", "status": "shipping", "scope": "grace" }, "cpu.grace.1": { "value": "Grace", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Codename", "source": [ "P08", "P09", "P11" ], "disclosure_date": "2022–2023", "status": "shipping", "scope": "grace" }, "cpu.grace.2": { "value": "2023", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "GA / milestone", "source": [ "P08", "P09", "P11" ], "disclosure_date": "2022–2023", "status": "shipping", "scope": "grace" }, "cpu.grace.3": { "value": "Shipping", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Status", "source": [ "P08", "P09", "P11" ], "disclosure_date": "2022–2023", "status": "shipping", "scope": "grace" }, "cpu.grace.4": { "value": "Arm Neoverse V2", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Core µarch", "source": [ "P08", "P09", "P11" ], "disclosure_date": "2022–2023", "status": "shipping", "scope": "grace" }, "cpu.grace.5": { "value": "72 / 72", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Max cores / threads", "source": [ "P08", "P09", "P11" ], "disclosure_date": "2022–2023", "status": "shipping", "scope": "grace" }, "cpu.grace.6": { "value": "4N", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Process per die", "source": [ "P08", "P09", "P11" ], "disclosure_date": "2022–2023", "status": "shipping", "scope": "grace" }, "cpu.grace.7": { "value": "CPU + LPDDR; dual CPU or CPU–GPU C2C", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Chiplets and packaging", "source": [ "P08", "P09", "P11" ], "disclosure_date": "2022–2023", "status": "shipping", "scope": "grace" }, "cpu.grace.8": { "value": "1 MB", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "L2 per core", "source": [ "P08", "P09", "P11" ], "disclosure_date": "2022–2023", "status": "shipping", "scope": "grace" }, "cpu.grace.9": { "value": "114 MB / chip", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "L3 total / domain", "source": [ "P08", "P09", "P11" ], "disclosure_date": "2022–2023", "status": "shipping", "scope": "grace" }, "cpu.grace.10": { "value": "LPDDR5X; up to 480 GB; 512 GB/s; channel/speed SKU-dependent", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Memory: type / channels / speed / GB/s", "source": [ "P08", "P09", "P11" ], "disclosure_date": "2022–2023", "status": "shipping", "scope": "grace" }, "cpu.grace.11": { "value": "1 or 2; C2C 900 GB/s bidirectional", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Sockets and socket links", "source": [ "P08", "P09", "P11" ], "disclosure_date": "2022–2023", "status": "shipping", "scope": "grace" }, "cpu.grace.12": { "value": "64 lanes PCIe 5; CXL n/d", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "PCIe / CXL", "source": [ "P08", "P09", "P11" ], "disclosure_date": "2022–2023", "status": "shipping", "scope": "grace" }, "cpu.grace.13": { "value": "500 W dual-CPU Superchip including memory; single-chip n/d", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Max TDP", "source": [ "P08", "P09", "P11" ], "disclosure_date": "2022–2023", "status": "shipping", "scope": "grace" }, "cpu.grace.14": { "value": "Armv9.0-A; 4 × 128-bit SVE2", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Matrix / vector ISA", "source": [ "P08", "P09", "P11" ], "disclosure_date": "2022–2023", "status": "shipping", "scope": "grace" }, "cpu.vera.0": { "value": "Vera", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Generation", "source": [ "P10", "P11", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "vera" }, "cpu.vera.1": { "value": "Olympus", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Codename", "source": [ "P10", "P11", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "vera" }, "cpu.vera.2": { "value": "2026 production / preview", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "GA / milestone", "source": [ "P10", "P11", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "vera" }, "cpu.vera.3": { "value": "GA n/d", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Status", "source": [ "P10", "P11", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "vera" }, "cpu.vera.4": { "value": "NVIDIA Olympus", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Core µarch", "source": [ "P10", "P11", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "vera" }, "cpu.vera.5": { "value": "88 / 176", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Max cores / threads", "source": [ "P10", "P11", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "vera" }, "cpu.vera.6": { "value": "n/d", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Process per die", "source": [ "P10", "P11", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "vera" }, "cpu.vera.7": { "value": "CPU + SOCAMM2; C2C platform", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Chiplets and packaging", "source": [ "P10", "P11", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "vera" }, "cpu.vera.8": { "value": "2 MB", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "L2 per core", "source": [ "P10", "P11", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "vera" }, "cpu.vera.9": { "value": "164 MB / chip", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "L3 total / domain", "source": [ "P10", "P11", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "vera" }, "cpu.vera.10": { "value": "LPDDR5X SOCAMM2; up to 1.5 TB; 1200 GB/s; channel/speed n/d", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Memory: type / channels / speed / GB/s", "source": [ "P10", "P11", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "vera" }, "cpu.vera.11": { "value": "1 or 2; C2C 1800 GB/s bidirectional", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Sockets and socket links", "source": [ "P10", "P11", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "vera" }, "cpu.vera.12": { "value": "PCIe 6 / CXL 3.1; lane count n/d", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "PCIe / CXL", "source": [ "P10", "P11", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "vera" }, "cpu.vera.13": { "value": "n/d", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Max TDP", "source": [ "P10", "P11", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "vera" }, "cpu.vera.14": { "value": "Armv9.2; 6 × 128-bit SVE2; FP8", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Matrix / vector ISA", "source": [ "P10", "P11", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "vera" }, "derivatives.p4p40.0": { "value": "P4 / P40", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Product", "source": [ "E18" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "p4p40" }, "derivatives.p4p40.1": { "value": "2016", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Era", "source": [ "E18" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "p4p40" }, "derivatives.p4p40.2": { "value": "GDDR5", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Memory", "source": [ "E18" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "p4p40" }, "derivatives.p4p40.3": { "value": "Pascal INT8 inference; not GP100 HBM/NVLink equivalence", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Deployment distinction", "source": [ "E18" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "p4p40" }, "derivatives.t4.0": { "value": "T4", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Product", "source": [ "P28" ], "disclosure_date": "2018", "status": "historical shipping", "scope": "t4" }, "derivatives.t4.1": { "value": "2018", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Era", "source": [ "P28" ], "disclosure_date": "2018", "status": "historical shipping", "scope": "t4" }, "derivatives.t4.2": { "value": "16 GB GDDR6; 320 GB/s", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Memory", "source": [ "P28" ], "disclosure_date": "2018", "status": "historical shipping", "scope": "t4" }, "derivatives.t4.3": { "value": "70 W PCIe; inference and video; no NVLink", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Deployment distinction", "source": [ "P28" ], "disclosure_date": "2018", "status": "historical shipping", "scope": "t4" }, "derivatives.l4.0": { "value": "L4", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Product", "source": [ "P29" ], "disclosure_date": "2023", "status": "shipping", "scope": "l4" }, "derivatives.l4.1": { "value": "2023", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Era", "source": [ "P29" ], "disclosure_date": "2023", "status": "shipping", "scope": "l4" }, "derivatives.l4.2": { "value": "24 GB GDDR6; 300 GB/s", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Memory", "source": [ "P29" ], "disclosure_date": "2023", "status": "shipping", "scope": "l4" }, "derivatives.l4.3": { "value": "72 W Ada inference/video; no NVLink", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Deployment distinction", "source": [ "P29" ], "disclosure_date": "2023", "status": "shipping", "scope": "l4" }, "derivatives.l40s.0": { "value": "L40S", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Product", "source": [ "P30" ], "disclosure_date": "2023", "status": "shipping", "scope": "l40s" }, "derivatives.l40s.1": { "value": "2023", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Era", "source": [ "P30" ], "disclosure_date": "2023", "status": "shipping", "scope": "l40s" }, "derivatives.l40s.2": { "value": "48 GB GDDR6; 864 GB/s", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Memory", "source": [ "P30" ], "disclosure_date": "2023", "status": "shipping", "scope": "l40s" }, "derivatives.l40s.3": { "value": "350 W; graphics plus AI; no NVLink", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Deployment distinction", "source": [ "P30" ], "disclosure_date": "2023", "status": "shipping", "scope": "l40s" }, "derivatives.rtxpro.0": { "value": "RTX PRO 6000 Blackwell Server Edition", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Product", "source": [ "P31" ], "disclosure_date": "2025", "status": "shipping", "scope": "rtxpro" }, "derivatives.rtxpro.1": { "value": "2025", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Era", "source": [ "P31" ], "disclosure_date": "2025", "status": "shipping", "scope": "rtxpro" }, "derivatives.rtxpro.2": { "value": "96 GB GDDR7; 1597 GB/s", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Memory", "source": [ "P31" ], "disclosure_date": "2025", "status": "shipping", "scope": "rtxpro" }, "derivatives.rtxpro.3": { "value": "Up to 600 W; graphics, AI and partitioned services", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Deployment distinction", "source": [ "P31" ], "disclosure_date": "2025", "status": "shipping", "scope": "rtxpro" }, "derivatives.gb10.0": { "value": "GB10 / DGX Spark", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Product", "source": [ "P46", "C10" ], "disclosure_date": "2025–2026", "status": "shipping", "scope": "gb10" }, "derivatives.gb10.1": { "value": "2025–2026", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Era", "source": [ "P46", "C10" ], "disclosure_date": "2025–2026", "status": "shipping", "scope": "gb10" }, "derivatives.gb10.2": { "value": "128 GB LPDDR5X; 273 GB/s", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Memory", "source": [ "P46", "C10" ], "disclosure_date": "2025–2026", "status": "shipping", "scope": "gb10" }, "derivatives.gb10.3": { "value": "20 Arm cores; coherent shared memory; desktop AI; 140 W SoC TDP", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Deployment distinction", "source": [ "P46", "C10" ], "disclosure_date": "2025–2026", "status": "shipping", "scope": "gb10" }, "derivatives.thor.0": { "value": "Jetson AGX Thor", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Product", "source": [ "E08" ], "disclosure_date": "2026", "status": "shipping", "scope": "thor" }, "derivatives.thor.1": { "value": "2025–2026", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Era", "source": [ "E08" ], "disclosure_date": "2026", "status": "shipping", "scope": "thor" }, "derivatives.thor.2": { "value": "Edge configuration; not server HBM equivalence", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Memory", "source": [ "E08" ], "disclosure_date": "2026", "status": "shipping", "scope": "thor" }, "derivatives.thor.3": { "value": "Blackwell-derived edge/robotics branch; benchmark scope differs", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Deployment distinction", "source": [ "E08" ], "disclosure_date": "2026", "status": "shipping", "scope": "thor" }, "interconnect.nv1.0": { "value": "NVLink 1", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Name / version", "source": [ "P01" ], "disclosure_date": "2016", "status": "shipping", "scope": "nv1" }, "interconnect.nv1.1": { "value": "2016", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Year", "source": [ "P01" ], "disclosure_date": "2016", "status": "shipping", "scope": "nv1" }, "interconnect.nv1.2": { "value": "20 Gb/s", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Lane rate", "source": [ "P01" ], "disclosure_date": "2016", "status": "shipping", "scope": "nv1" }, "interconnect.nv1.3": { "value": "8", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Lanes per link", "source": [ "P01" ], "disclosure_date": "2016", "status": "shipping", "scope": "nv1" }, "interconnect.nv1.4": { "value": "20", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "GB/s per link per direction", "source": [ "P01" ], "disclosure_date": "2016", "status": "shipping", "scope": "nv1" }, "interconnect.nv1.5": { "value": "4", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Links per device", "source": [ "P01" ], "disclosure_date": "2016", "status": "shipping", "scope": "nv1" }, "interconnect.nv1.6": { "value": "Direct peer links", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Topology", "source": [ "P01" ], "disclosure_date": "2016", "status": "shipping", "scope": "nv1" }, "interconnect.nv1.7": { "value": "Server wiring-dependent", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Max / reference domain", "source": [ "P01" ], "disclosure_date": "2016", "status": "shipping", "scope": "nv1" }, "interconnect.nv1.8": { "value": "GPU peer access; not uniform memory", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Coherence / memory semantics", "source": [ "P01" ], "disclosure_date": "2016", "status": "shipping", "scope": "nv1" }, "interconnect.nv2.0": { "value": "NVLink 2", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Name / version", "source": [ "P02", "P18" ], "disclosure_date": "2017–2018", "status": "shipping", "scope": "nv2" }, "interconnect.nv2.1": { "value": "2017–2018", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Year", "source": [ "P02", "P18" ], "disclosure_date": "2017–2018", "status": "shipping", "scope": "nv2" }, "interconnect.nv2.2": { "value": "25 Gb/s", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Lane rate", "source": [ "P02", "P18" ], "disclosure_date": "2017–2018", "status": "shipping", "scope": "nv2" }, "interconnect.nv2.3": { "value": "8", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Lanes per link", "source": [ "P02", "P18" ], "disclosure_date": "2017–2018", "status": "shipping", "scope": "nv2" }, "interconnect.nv2.4": { "value": "25", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "GB/s per link per direction", "source": [ "P02", "P18" ], "disclosure_date": "2017–2018", "status": "shipping", "scope": "nv2" }, "interconnect.nv2.5": { "value": "6", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Links per device", "source": [ "P02", "P18" ], "disclosure_date": "2017–2018", "status": "shipping", "scope": "nv2" }, "interconnect.nv2.6": { "value": "Direct + NVSwitch", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Topology", "source": [ "P02", "P18" ], "disclosure_date": "2017–2018", "status": "shipping", "scope": "nv2" }, "interconnect.nv2.7": { "value": "16 GPUs (DGX-2)", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Max / reference domain", "source": [ "P02", "P18" ], "disclosure_date": "2017–2018", "status": "shipping", "scope": "nv2" }, "interconnect.nv2.8": { "value": "Peer memory; platform-specific CPU coherence", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Coherence / memory semantics", "source": [ "P02", "P18" ], "disclosure_date": "2017–2018", "status": "shipping", "scope": "nv2" }, "interconnect.nv3.0": { "value": "NVLink 3", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Name / version", "source": [ "P03" ], "disclosure_date": "2020", "status": "shipping", "scope": "nv3" }, "interconnect.nv3.1": { "value": "2020", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Year", "source": [ "P03" ], "disclosure_date": "2020", "status": "shipping", "scope": "nv3" }, "interconnect.nv3.2": { "value": "50 Gb/s", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Lane rate", "source": [ "P03" ], "disclosure_date": "2020", "status": "shipping", "scope": "nv3" }, "interconnect.nv3.3": { "value": "4", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Lanes per link", "source": [ "P03" ], "disclosure_date": "2020", "status": "shipping", "scope": "nv3" }, "interconnect.nv3.4": { "value": "25", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "GB/s per link per direction", "source": [ "P03" ], "disclosure_date": "2020", "status": "shipping", "scope": "nv3" }, "interconnect.nv3.5": { "value": "12", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Links per device", "source": [ "P03" ], "disclosure_date": "2020", "status": "shipping", "scope": "nv3" }, "interconnect.nv3.6": { "value": "NVSwitch", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Topology", "source": [ "P03" ], "disclosure_date": "2020", "status": "shipping", "scope": "nv3" }, "interconnect.nv3.7": { "value": "8 GPUs (HGX)", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Max / reference domain", "source": [ "P03" ], "disclosure_date": "2020", "status": "shipping", "scope": "nv3" }, "interconnect.nv3.8": { "value": "GPU peer memory", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Coherence / memory semantics", "source": [ "P03" ], "disclosure_date": "2020", "status": "shipping", "scope": "nv3" }, "interconnect.nv4.0": { "value": "NVLink 4", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Name / version", "source": [ "P04", "P18" ], "disclosure_date": "2022", "status": "shipping", "scope": "nv4" }, "interconnect.nv4.1": { "value": "2022", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Year", "source": [ "P04", "P18" ], "disclosure_date": "2022", "status": "shipping", "scope": "nv4" }, "interconnect.nv4.2": { "value": "100 Gb/s", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Lane rate", "source": [ "P04", "P18" ], "disclosure_date": "2022", "status": "shipping", "scope": "nv4" }, "interconnect.nv4.3": { "value": "2", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Lanes per link", "source": [ "P04", "P18" ], "disclosure_date": "2022", "status": "shipping", "scope": "nv4" }, "interconnect.nv4.4": { "value": "25", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "GB/s per link per direction", "source": [ "P04", "P18" ], "disclosure_date": "2022", "status": "shipping", "scope": "nv4" }, "interconnect.nv4.5": { "value": "18", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Links per device", "source": [ "P04", "P18" ], "disclosure_date": "2022", "status": "shipping", "scope": "nv4" }, "interconnect.nv4.6": { "value": "NVSwitch", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Topology", "source": [ "P04", "P18" ], "disclosure_date": "2022", "status": "shipping", "scope": "nv4" }, "interconnect.nv4.7": { "value": "8 HGX; larger external switch systems", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Max / reference domain", "source": [ "P04", "P18" ], "disclosure_date": "2022", "status": "shipping", "scope": "nv4" }, "interconnect.nv4.8": { "value": "GPU peer memory / collectives", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Coherence / memory semantics", "source": [ "P04", "P18" ], "disclosure_date": "2022", "status": "shipping", "scope": "nv4" }, "interconnect.nv5.0": { "value": "NVLink 5", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Name / version", "source": [ "P18", "P05" ], "disclosure_date": "2024", "status": "shipping", "scope": "nv5" }, "interconnect.nv5.1": { "value": "2024–2025", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Year", "source": [ "P18", "P05" ], "disclosure_date": "2024", "status": "shipping", "scope": "nv5" }, "interconnect.nv5.2": { "value": "n/d", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Lane rate", "source": [ "P18", "P05" ], "disclosure_date": "2024", "status": "shipping", "scope": "nv5" }, "interconnect.nv5.3": { "value": "n/d", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Lanes per link", "source": [ "P18", "P05" ], "disclosure_date": "2024", "status": "shipping", "scope": "nv5" }, "interconnect.nv5.4": { "value": "50", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "GB/s per link per direction", "source": [ "P18", "P05" ], "disclosure_date": "2024", "status": "shipping", "scope": "nv5" }, "interconnect.nv5.5": { "value": "18", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Links per device", "source": [ "P18", "P05" ], "disclosure_date": "2024", "status": "shipping", "scope": "nv5" }, "interconnect.nv5.6": { "value": "NVSwitch", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Topology", "source": [ "P18", "P05" ], "disclosure_date": "2024", "status": "shipping", "scope": "nv5" }, "interconnect.nv5.7": { "value": "72 GPUs (NVL72)", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Max / reference domain", "source": [ "P18", "P05" ], "disclosure_date": "2024", "status": "shipping", "scope": "nv5" }, "interconnect.nv5.8": { "value": "Rack peer domain; not uniform latency", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Coherence / memory semantics", "source": [ "P18", "P05" ], "disclosure_date": "2024", "status": "shipping", "scope": "nv5" }, "interconnect.nv6.0": { "value": "NVLink 6", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Name / version", "source": [ "P11", "P18", "P38" ], "disclosure_date": "2026", "status": "production / preview", "scope": "nv6" }, "interconnect.nv6.1": { "value": "2026", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Year", "source": [ "P11", "P18", "P38" ], "disclosure_date": "2026", "status": "production / preview", "scope": "nv6" }, "interconnect.nv6.2": { "value": "n/d", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Lane rate", "source": [ "P11", "P18", "P38" ], "disclosure_date": "2026", "status": "production / preview", "scope": "nv6" }, "interconnect.nv6.3": { "value": "n/d", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Lanes per link", "source": [ "P11", "P18", "P38" ], "disclosure_date": "2026", "status": "production / preview", "scope": "nv6" }, "interconnect.nv6.4": { "value": "n/d", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "GB/s per link per direction", "source": [ "P11", "P18", "P38" ], "disclosure_date": "2026", "status": "production / preview", "scope": "nv6" }, "interconnect.nv6.5": { "value": "n/d", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Links per device", "source": [ "P11", "P18", "P38" ], "disclosure_date": "2026", "status": "production / preview", "scope": "nv6" }, "interconnect.nv6.6": { "value": "NVSwitch", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Topology", "source": [ "P11", "P18", "P38" ], "disclosure_date": "2026", "status": "production / preview", "scope": "nv6" }, "interconnect.nv6.7": { "value": "72 GPUs (NVL72)", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Max / reference domain", "source": [ "P11", "P18", "P38" ], "disclosure_date": "2026", "status": "production / preview", "scope": "nv6" }, "interconnect.nv6.8": { "value": "3600 GB/s bidirectional peak per GPU; configured 3000", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Coherence / memory semantics", "source": [ "P11", "P18", "P38" ], "disclosure_date": "2026", "status": "production / preview", "scope": "nv6" }, "interconnect.c2c1.0": { "value": "NVLink-C2C / Grace", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Name / version", "source": [ "C09", "P08" ], "disclosure_date": "2023", "status": "shipping", "scope": "c2c1" }, "interconnect.c2c1.1": { "value": "2023", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Year", "source": [ "C09", "P08" ], "disclosure_date": "2023", "status": "shipping", "scope": "c2c1" }, "interconnect.c2c1.2": { "value": "40 Gb/s/pin", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Lane rate", "source": [ "C09", "P08" ], "disclosure_date": "2023", "status": "shipping", "scope": "c2c1" }, "interconnect.c2c1.3": { "value": "n/d", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Lanes per link", "source": [ "C09", "P08" ], "disclosure_date": "2023", "status": "shipping", "scope": "c2c1" }, "interconnect.c2c1.4": { "value": "n/d", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "GB/s per link per direction", "source": [ "C09", "P08" ], "disclosure_date": "2023", "status": "shipping", "scope": "c2c1" }, "interconnect.c2c1.5": { "value": "10", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Links per device", "source": [ "C09", "P08" ], "disclosure_date": "2023", "status": "shipping", "scope": "c2c1" }, "interconnect.c2c1.6": { "value": "CPU–CPU / CPU–GPU", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Topology", "source": [ "C09", "P08" ], "disclosure_date": "2023", "status": "shipping", "scope": "c2c1" }, "interconnect.c2c1.7": { "value": "Coherent module", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Max / reference domain", "source": [ "C09", "P08" ], "disclosure_date": "2023", "status": "shipping", "scope": "c2c1" }, "interconnect.c2c1.8": { "value": "900 GB/s bidirectional; coherent access", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Coherence / memory semantics", "source": [ "C09", "P08" ], "disclosure_date": "2023", "status": "shipping", "scope": "c2c1" }, "interconnect.c2c2.0": { "value": "NVLink-C2C / Vera", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Name / version", "source": [ "P10", "P11" ], "disclosure_date": "2026", "status": "production / preview", "scope": "c2c2" }, "interconnect.c2c2.1": { "value": "2026", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Year", "source": [ "P10", "P11" ], "disclosure_date": "2026", "status": "production / preview", "scope": "c2c2" }, "interconnect.c2c2.2": { "value": "n/d", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Lane rate", "source": [ "P10", "P11" ], "disclosure_date": "2026", "status": "production / preview", "scope": "c2c2" }, "interconnect.c2c2.3": { "value": "n/d", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Lanes per link", "source": [ "P10", "P11" ], "disclosure_date": "2026", "status": "production / preview", "scope": "c2c2" }, "interconnect.c2c2.4": { "value": "n/d", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "GB/s per link per direction", "source": [ "P10", "P11" ], "disclosure_date": "2026", "status": "production / preview", "scope": "c2c2" }, "interconnect.c2c2.5": { "value": "n/d", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Links per device", "source": [ "P10", "P11" ], "disclosure_date": "2026", "status": "production / preview", "scope": "c2c2" }, "interconnect.c2c2.6": { "value": "CPU–GPU / CPU–CPU", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Topology", "source": [ "P10", "P11" ], "disclosure_date": "2026", "status": "production / preview", "scope": "c2c2" }, "interconnect.c2c2.7": { "value": "Coherent platform", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Max / reference domain", "source": [ "P10", "P11" ], "disclosure_date": "2026", "status": "production / preview", "scope": "c2c2" }, "interconnect.c2c2.8": { "value": "1800 GB/s bidirectional", "basis": "NVLink link payload rates as published; per-direction GB/s; C2C aggregate totals explicitly bidirectional", "field": "Coherence / memory semantics", "source": [ "P10", "P11" ], "disclosure_date": "2026", "status": "production / preview", "scope": "c2c2" }, "network.cx4lx.0": { "value": "ConnectX-4 Lx", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Product", "source": [ "P43" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "cx4lx" }, "network.cx4lx.1": { "value": "2015–2016 era", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "GA / milestone", "source": [ "P43" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "cx4lx" }, "network.cx4lx.2": { "value": "Historical shipping", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Status", "source": [ "P43" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "cx4lx" }, "network.cx4lx.3": { "value": "NIC", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Class", "source": [ "P43" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "cx4lx" }, "network.cx4lx.4": { "value": "25/50 GbE variants", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Ports × speed", "source": [ "P43" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "cx4lx" }, "network.cx4lx.5": { "value": "25G NRZ", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "SerDes", "source": [ "P43" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "cx4lx" }, "network.cx4lx.6": { "value": "PCIe 3 x8/x16", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Host interface", "source": [ "P43" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "cx4lx" }, "network.cx4lx.7": { "value": "eSwitch / steering", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Programmable engine", "source": [ "P43" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "cx4lx" }, "network.cx4lx.8": { "value": "n/a", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Embedded CPU", "source": [ "P43" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "cx4lx" }, "network.cx4lx.9": { "value": "Adapter buffers; capacity n/d", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "On-card memory", "source": [ "P43" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "cx4lx" }, "network.cx4lx.10": { "value": "Ethernet / RoCE", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Transport / RDMA", "source": [ "P43" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "cx4lx" }, "network.cx4lx.11": { "value": "ECN / PFC", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Congestion control", "source": [ "P43" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "cx4lx" }, "network.cx4lx.12": { "value": "Overlay, virtualization, RDMA", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Key offloads", "source": [ "P43" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "cx4lx" }, "network.cx4lx.13": { "value": "SKU-dependent", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Power", "source": [ "P43" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "cx4lx" }, "network.cx5.0": { "value": "ConnectX-5 / Ex", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Product", "source": [ "P49", "P48" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "cx5" }, "network.cx5.1": { "value": "2017 era", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "GA / milestone", "source": [ "P49", "P48" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "cx5" }, "network.cx5.2": { "value": "Historical shipping", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Status", "source": [ "P49", "P48" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "cx5" }, "network.cx5.3": { "value": "NIC", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Class", "source": [ "P49", "P48" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "cx5" }, "network.cx5.4": { "value": "up to 2 × 100 Gb/s", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Ports × speed", "source": [ "P49", "P48" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "cx5" }, "network.cx5.5": { "value": "25G NRZ", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "SerDes", "source": [ "P49", "P48" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "cx5" }, "network.cx5.6": { "value": "PCIe 3 x16; Ex PCIe 4", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Host interface", "source": [ "P49", "P48" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "cx5" }, "network.cx5.7": { "value": "eSwitch / steering", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Programmable engine", "source": [ "P49", "P48" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "cx5" }, "network.cx5.8": { "value": "n/a", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Embedded CPU", "source": [ "P49", "P48" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "cx5" }, "network.cx5.9": { "value": "n/d", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "On-card memory", "source": [ "P49", "P48" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "cx5" }, "network.cx5.10": { "value": "Ethernet / IB / RoCE", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Transport / RDMA", "source": [ "P49", "P48" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "cx5" }, "network.cx5.11": { "value": "ECN / PFC", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Congestion control", "source": [ "P49", "P48" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "cx5" }, "network.cx5.12": { "value": "GPUDirect RDMA; storage; switching", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Key offloads", "source": [ "P49", "P48" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "cx5" }, "network.cx5.13": { "value": "SKU-dependent", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Power", "source": [ "P49", "P48" ], "disclosure_date": "2017", "status": "historical shipping", "scope": "cx5" }, "network.cx6.0": { "value": "ConnectX-6", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Product", "source": [ "P26" ], "disclosure_date": "2019", "status": "historical shipping", "scope": "cx6" }, "network.cx6.1": { "value": "2019 era", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "GA / milestone", "source": [ "P26" ], "disclosure_date": "2019", "status": "historical shipping", "scope": "cx6" }, "network.cx6.2": { "value": "Historical shipping", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Status", "source": [ "P26" ], "disclosure_date": "2019", "status": "historical shipping", "scope": "cx6" }, "network.cx6.3": { "value": "NIC", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Class", "source": [ "P26" ], "disclosure_date": "2019", "status": "historical shipping", "scope": "cx6" }, "network.cx6.4": { "value": "up to 200 Gb/s", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Ports × speed", "source": [ "P26" ], "disclosure_date": "2019", "status": "historical shipping", "scope": "cx6" }, "network.cx6.5": { "value": "50G PAM4", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "SerDes", "source": [ "P26" ], "disclosure_date": "2019", "status": "historical shipping", "scope": "cx6" }, "network.cx6.6": { "value": "PCIe 4 x16", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Host interface", "source": [ "P26" ], "disclosure_date": "2019", "status": "historical shipping", "scope": "cx6" }, "network.cx6.7": { "value": "Transport / steering", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Programmable engine", "source": [ "P26" ], "disclosure_date": "2019", "status": "historical shipping", "scope": "cx6" }, "network.cx6.8": { "value": "n/a", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Embedded CPU", "source": [ "P26" ], "disclosure_date": "2019", "status": "historical shipping", "scope": "cx6" }, "network.cx6.9": { "value": "n/d", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "On-card memory", "source": [ "P26" ], "disclosure_date": "2019", "status": "historical shipping", "scope": "cx6" }, "network.cx6.10": { "value": "Ethernet / HDR IB / RoCE", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Transport / RDMA", "source": [ "P26" ], "disclosure_date": "2019", "status": "historical shipping", "scope": "cx6" }, "network.cx6.11": { "value": "ECN / PFC", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Congestion control", "source": [ "P26" ], "disclosure_date": "2019", "status": "historical shipping", "scope": "cx6" }, "network.cx6.12": { "value": "GPUDirect RDMA; variant-specific crypto", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Key offloads", "source": [ "P26" ], "disclosure_date": "2019", "status": "historical shipping", "scope": "cx6" }, "network.cx6.13": { "value": "SKU-dependent", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Power", "source": [ "P26" ], "disclosure_date": "2019", "status": "historical shipping", "scope": "cx6" }, "network.cx7.0": { "value": "ConnectX-7", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Product", "source": [ "P50", "P22" ], "disclosure_date": "2022", "status": "shipping", "scope": "cx7" }, "network.cx7.1": { "value": "2022 era", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "GA / milestone", "source": [ "P50", "P22" ], "disclosure_date": "2022", "status": "shipping", "scope": "cx7" }, "network.cx7.2": { "value": "Shipping", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Status", "source": [ "P50", "P22" ], "disclosure_date": "2022", "status": "shipping", "scope": "cx7" }, "network.cx7.3": { "value": "NIC / SuperNIC", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Class", "source": [ "P50", "P22" ], "disclosure_date": "2022", "status": "shipping", "scope": "cx7" }, "network.cx7.4": { "value": "1 × 400 / 2 × 200 Gb/s", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Ports × speed", "source": [ "P50", "P22" ], "disclosure_date": "2022", "status": "shipping", "scope": "cx7" }, "network.cx7.5": { "value": "100G PAM4", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "SerDes", "source": [ "P50", "P22" ], "disclosure_date": "2022", "status": "shipping", "scope": "cx7" }, "network.cx7.6": { "value": "PCIe 5 x16; Socket Direct", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Host interface", "source": [ "P50", "P22" ], "disclosure_date": "2022", "status": "shipping", "scope": "cx7" }, "network.cx7.7": { "value": "Transport / steering", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Programmable engine", "source": [ "P50", "P22" ], "disclosure_date": "2022", "status": "shipping", "scope": "cx7" }, "network.cx7.8": { "value": "n/a", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Embedded CPU", "source": [ "P50", "P22" ], "disclosure_date": "2022", "status": "shipping", "scope": "cx7" }, "network.cx7.9": { "value": "n/d", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "On-card memory", "source": [ "P50", "P22" ], "disclosure_date": "2022", "status": "shipping", "scope": "cx7" }, "network.cx7.10": { "value": "Ethernet / NDR IB / RoCE", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Transport / RDMA", "source": [ "P50", "P22" ], "disclosure_date": "2022", "status": "shipping", "scope": "cx7" }, "network.cx7.11": { "value": "Adaptive routing / ECN by fabric", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Congestion control", "source": [ "P50", "P22" ], "disclosure_date": "2022", "status": "shipping", "scope": "cx7" }, "network.cx7.12": { "value": "GPUDirect; virtualization; crypto", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Key offloads", "source": [ "P50", "P22" ], "disclosure_date": "2022", "status": "shipping", "scope": "cx7" }, "network.cx7.13": { "value": "SKU-dependent", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Power", "source": [ "P50", "P22" ], "disclosure_date": "2022", "status": "shipping", "scope": "cx7" }, "network.cx8.0": { "value": "ConnectX-8", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Product", "source": [ "P19", "P22", "C06" ], "disclosure_date": "2025", "status": "shipping", "scope": "cx8" }, "network.cx8.1": { "value": "2025", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "GA / milestone", "source": [ "P19", "P22", "C06" ], "disclosure_date": "2025", "status": "shipping", "scope": "cx8" }, "network.cx8.2": { "value": "Shipping platform generation", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Status", "source": [ "P19", "P22", "C06" ], "disclosure_date": "2025", "status": "shipping", "scope": "cx8" }, "network.cx8.3": { "value": "SuperNIC", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Class", "source": [ "P19", "P22", "C06" ], "disclosure_date": "2025", "status": "shipping", "scope": "cx8" }, "network.cx8.4": { "value": "800 Gb/s class", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Ports × speed", "source": [ "P19", "P22", "C06" ], "disclosure_date": "2025", "status": "shipping", "scope": "cx8" }, "network.cx8.5": { "value": "n/d", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "SerDes", "source": [ "P19", "P22", "C06" ], "disclosure_date": "2025", "status": "shipping", "scope": "cx8" }, "network.cx8.6": { "value": "PCIe 6 + integrated switch", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Host interface", "source": [ "P19", "P22", "C06" ], "disclosure_date": "2025", "status": "shipping", "scope": "cx8" }, "network.cx8.7": { "value": "Programmable transport / steering", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Programmable engine", "source": [ "P19", "P22", "C06" ], "disclosure_date": "2025", "status": "shipping", "scope": "cx8" }, "network.cx8.8": { "value": "n/a", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Embedded CPU", "source": [ "P19", "P22", "C06" ], "disclosure_date": "2025", "status": "shipping", "scope": "cx8" }, "network.cx8.9": { "value": "n/d", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "On-card memory", "source": [ "P19", "P22", "C06" ], "disclosure_date": "2025", "status": "shipping", "scope": "cx8" }, "network.cx8.10": { "value": "Ethernet / IB / RoCE", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Transport / RDMA", "source": [ "P19", "P22", "C06" ], "disclosure_date": "2025", "status": "shipping", "scope": "cx8" }, "network.cx8.11": { "value": "AI adaptive routing / congestion control", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Congestion control", "source": [ "P19", "P22", "C06" ], "disclosure_date": "2025", "status": "shipping", "scope": "cx8" }, "network.cx8.12": { "value": "GPU/NIC PCIe switching; GPUDirect", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Key offloads", "source": [ "P19", "P22", "C06" ], "disclosure_date": "2025", "status": "shipping", "scope": "cx8" }, "network.cx8.13": { "value": "SKU-dependent", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Power", "source": [ "P19", "P22", "C06" ], "disclosure_date": "2025", "status": "shipping", "scope": "cx8" }, "network.cx9.0": { "value": "ConnectX-9", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Product", "source": [ "P21", "P22", "P11", "E09" ], "disclosure_date": "2026", "status": "production", "scope": "cx9" }, "network.cx9.1": { "value": "2026", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "GA / milestone", "source": [ "P21", "P22", "P11", "E09" ], "disclosure_date": "2026", "status": "production", "scope": "cx9" }, "network.cx9.2": { "value": "Production; configuration-dependent", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Status", "source": [ "P21", "P22", "P11", "E09" ], "disclosure_date": "2026", "status": "production", "scope": "cx9" }, "network.cx9.3": { "value": "SuperNIC", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Class", "source": [ "P21", "P22", "P11", "E09" ], "disclosure_date": "2026", "status": "production", "scope": "cx9" }, "network.cx9.4": { "value": "800 Gb/s card; up to 1600 Gb/s per GPU platform", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Ports × speed", "source": [ "P21", "P22", "P11", "E09" ], "disclosure_date": "2026", "status": "production", "scope": "cx9" }, "network.cx9.5": { "value": "200G class", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "SerDes", "source": [ "P21", "P22", "P11", "E09" ], "disclosure_date": "2026", "status": "production", "scope": "cx9" }, "network.cx9.6": { "value": "PCIe 6 x16 / Socket Direct x32", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Host interface", "source": [ "P21", "P22", "P11", "E09" ], "disclosure_date": "2026", "status": "production", "scope": "cx9" }, "network.cx9.7": { "value": "AI transport / steering", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Programmable engine", "source": [ "P21", "P22", "P11", "E09" ], "disclosure_date": "2026", "status": "production", "scope": "cx9" }, "network.cx9.8": { "value": "n/a", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Embedded CPU", "source": [ "P21", "P22", "P11", "E09" ], "disclosure_date": "2026", "status": "production", "scope": "cx9" }, "network.cx9.9": { "value": "n/d", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "On-card memory", "source": [ "P21", "P22", "P11", "E09" ], "disclosure_date": "2026", "status": "production", "scope": "cx9" }, "network.cx9.10": { "value": "Ethernet / XDR IB / RoCE", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Transport / RDMA", "source": [ "P21", "P22", "P11", "E09" ], "disclosure_date": "2026", "status": "production", "scope": "cx9" }, "network.cx9.11": { "value": "Spectrum-X multiplane / adaptive routing", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Congestion control", "source": [ "P21", "P22", "P11", "E09" ], "disclosure_date": "2026", "status": "production", "scope": "cx9" }, "network.cx9.12": { "value": "GPUDirect; PCIe fabric; security", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Key offloads", "source": [ "P21", "P22", "P11", "E09" ], "disclosure_date": "2026", "status": "production", "scope": "cx9" }, "network.cx9.13": { "value": "SKU-dependent", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Power", "source": [ "P21", "P22", "P11", "E09" ], "disclosure_date": "2026", "status": "production", "scope": "cx9" }, "network.bf1.0": { "value": "BlueField", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Product", "source": [ "P48", "E05" ], "disclosure_date": "2020 brief", "status": "historical shipping", "scope": "bf1" }, "network.bf1.1": { "value": "Pre-2020; exact GA n/d", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "GA / milestone", "source": [ "P48", "E05" ], "disclosure_date": "2020 brief", "status": "historical shipping", "scope": "bf1" }, "network.bf1.2": { "value": "Historical shipping", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Status", "source": [ "P48", "E05" ], "disclosure_date": "2020 brief", "status": "historical shipping", "scope": "bf1" }, "network.bf1.3": { "value": "DPU", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Class", "source": [ "P48", "E05" ], "disclosure_date": "2020 brief", "status": "historical shipping", "scope": "bf1" }, "network.bf1.4": { "value": "up to 2 × 100 Gb/s", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Ports × speed", "source": [ "P48", "E05" ], "disclosure_date": "2020 brief", "status": "historical shipping", "scope": "bf1" }, "network.bf1.5": { "value": "25G class", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "SerDes", "source": [ "P48", "E05" ], "disclosure_date": "2020 brief", "status": "historical shipping", "scope": "bf1" }, "network.bf1.6": { "value": "up to 32 lanes PCIe 3/4", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Host interface", "source": [ "P48", "E05" ], "disclosure_date": "2020 brief", "status": "historical shipping", "scope": "bf1" }, "network.bf1.7": { "value": "ConnectX-5 eSwitch", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Programmable engine", "source": [ "P48", "E05" ], "disclosure_date": "2020 brief", "status": "historical shipping", "scope": "bf1" }, "network.bf1.8": { "value": "up to 16 Arm A72", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Embedded CPU", "source": [ "P48", "E05" ], "disclosure_date": "2020 brief", "status": "historical shipping", "scope": "bf1" }, "network.bf1.9": { "value": "DDR4; capacity SKU-dependent", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "On-card memory", "source": [ "P48", "E05" ], "disclosure_date": "2020 brief", "status": "historical shipping", "scope": "bf1" }, "network.bf1.10": { "value": "Ethernet / IB / RoCE", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Transport / RDMA", "source": [ "P48", "E05" ], "disclosure_date": "2020 brief", "status": "historical shipping", "scope": "bf1" }, "network.bf1.11": { "value": "ECN / PFC", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Congestion control", "source": [ "P48", "E05" ], "disclosure_date": "2020 brief", "status": "historical shipping", "scope": "bf1" }, "network.bf1.12": { "value": "NVMe-oF; switching; virtualization", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Key offloads", "source": [ "P48", "E05" ], "disclosure_date": "2020 brief", "status": "historical shipping", "scope": "bf1" }, "network.bf1.13": { "value": "SKU-dependent", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Power", "source": [ "P48", "E05" ], "disclosure_date": "2020 brief", "status": "historical shipping", "scope": "bf1" }, "network.bf2.0": { "value": "BlueField-2", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Product", "source": [ "P25" ], "disclosure_date": "2020–2021", "status": "shipping", "scope": "bf2" }, "network.bf2.1": { "value": "2020–2021 generation", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "GA / milestone", "source": [ "P25" ], "disclosure_date": "2020–2021", "status": "shipping", "scope": "bf2" }, "network.bf2.2": { "value": "Shipping", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Status", "source": [ "P25" ], "disclosure_date": "2020–2021", "status": "shipping", "scope": "bf2" }, "network.bf2.3": { "value": "DPU", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Class", "source": [ "P25" ], "disclosure_date": "2020–2021", "status": "shipping", "scope": "bf2" }, "network.bf2.4": { "value": "up to 200 Gb/s", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Ports × speed", "source": [ "P25" ], "disclosure_date": "2020–2021", "status": "shipping", "scope": "bf2" }, "network.bf2.5": { "value": "50G class", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "SerDes", "source": [ "P25" ], "disclosure_date": "2020–2021", "status": "shipping", "scope": "bf2" }, "network.bf2.6": { "value": "PCIe 4 x16", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Host interface", "source": [ "P25" ], "disclosure_date": "2020–2021", "status": "shipping", "scope": "bf2" }, "network.bf2.7": { "value": "ConnectX-6 Dx + Arm", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Programmable engine", "source": [ "P25" ], "disclosure_date": "2020–2021", "status": "shipping", "scope": "bf2" }, "network.bf2.8": { "value": "8 Arm A72", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Embedded CPU", "source": [ "P25" ], "disclosure_date": "2020–2021", "status": "shipping", "scope": "bf2" }, "network.bf2.9": { "value": "DDR4; SKU-dependent", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "On-card memory", "source": [ "P25" ], "disclosure_date": "2020–2021", "status": "shipping", "scope": "bf2" }, "network.bf2.10": { "value": "Ethernet / RoCE; variants", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Transport / RDMA", "source": [ "P25" ], "disclosure_date": "2020–2021", "status": "shipping", "scope": "bf2" }, "network.bf2.11": { "value": "ECN / PFC", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Congestion control", "source": [ "P25" ], "disclosure_date": "2020–2021", "status": "shipping", "scope": "bf2" }, "network.bf2.12": { "value": "DOCA; storage; crypto; virtual switch", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Key offloads", "source": [ "P25" ], "disclosure_date": "2020–2021", "status": "shipping", "scope": "bf2" }, "network.bf2.13": { "value": "SKU-dependent", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Power", "source": [ "P25" ], "disclosure_date": "2020–2021", "status": "shipping", "scope": "bf2" }, "network.bf3.0": { "value": "BlueField-3", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Product", "source": [ "P24", "P22" ], "disclosure_date": "2023", "status": "shipping", "scope": "bf3" }, "network.bf3.1": { "value": "2023 generation", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "GA / milestone", "source": [ "P24", "P22" ], "disclosure_date": "2023", "status": "shipping", "scope": "bf3" }, "network.bf3.2": { "value": "Shipping", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Status", "source": [ "P24", "P22" ], "disclosure_date": "2023", "status": "shipping", "scope": "bf3" }, "network.bf3.3": { "value": "DPU / SuperNIC", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Class", "source": [ "P24", "P22" ], "disclosure_date": "2023", "status": "shipping", "scope": "bf3" }, "network.bf3.4": { "value": "up to 400 Gb/s", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Ports × speed", "source": [ "P24", "P22" ], "disclosure_date": "2023", "status": "shipping", "scope": "bf3" }, "network.bf3.5": { "value": "100G class", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "SerDes", "source": [ "P24", "P22" ], "disclosure_date": "2023", "status": "shipping", "scope": "bf3" }, "network.bf3.6": { "value": "up to 32 lanes PCIe 5", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Host interface", "source": [ "P24", "P22" ], "disclosure_date": "2023", "status": "shipping", "scope": "bf3" }, "network.bf3.7": { "value": "ConnectX-7 + DPA + Arm", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Programmable engine", "source": [ "P24", "P22" ], "disclosure_date": "2023", "status": "shipping", "scope": "bf3" }, "network.bf3.8": { "value": "up to 16 Arm A78", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Embedded CPU", "source": [ "P24", "P22" ], "disclosure_date": "2023", "status": "shipping", "scope": "bf3" }, "network.bf3.9": { "value": "16/32 GB DDR5; SKU-dependent", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "On-card memory", "source": [ "P24", "P22" ], "disclosure_date": "2023", "status": "shipping", "scope": "bf3" }, "network.bf3.10": { "value": "Ethernet / NDR IB / RoCE", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Transport / RDMA", "source": [ "P24", "P22" ], "disclosure_date": "2023", "status": "shipping", "scope": "bf3" }, "network.bf3.11": { "value": "Spectrum-X / adaptive congestion control", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Congestion control", "source": [ "P24", "P22" ], "disclosure_date": "2023", "status": "shipping", "scope": "bf3" }, "network.bf3.12": { "value": "DOCA; storage/security; asynchronous offload", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Key offloads", "source": [ "P24", "P22" ], "disclosure_date": "2023", "status": "shipping", "scope": "bf3" }, "network.bf3.13": { "value": "SKU-dependent", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Power", "source": [ "P24", "P22" ], "disclosure_date": "2023", "status": "shipping", "scope": "bf3" }, "network.bf4.0": { "value": "BlueField-4", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Product", "source": [ "P20", "P11", "E01" ], "disclosure_date": "2026", "status": "production", "scope": "bf4" }, "network.bf4.1": { "value": "2026", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "GA / milestone", "source": [ "P20", "P11", "E01" ], "disclosure_date": "2026", "status": "production", "scope": "bf4" }, "network.bf4.2": { "value": "Production disclosure", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Status", "source": [ "P20", "P11", "E01" ], "disclosure_date": "2026", "status": "production", "scope": "bf4" }, "network.bf4.3": { "value": "DPU", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Class", "source": [ "P20", "P11", "E01" ], "disclosure_date": "2026", "status": "production", "scope": "bf4" }, "network.bf4.4": { "value": "800 Gb/s", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Ports × speed", "source": [ "P20", "P11", "E01" ], "disclosure_date": "2026", "status": "production", "scope": "bf4" }, "network.bf4.5": { "value": "200G class", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "SerDes", "source": [ "P20", "P11", "E01" ], "disclosure_date": "2026", "status": "production", "scope": "bf4" }, "network.bf4.6": { "value": "PCIe 6", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Host interface", "source": [ "P20", "P11", "E01" ], "disclosure_date": "2026", "status": "production", "scope": "bf4" }, "network.bf4.7": { "value": "ConnectX-9 + Grace", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Programmable engine", "source": [ "P20", "P11", "E01" ], "disclosure_date": "2026", "status": "production", "scope": "bf4" }, "network.bf4.8": { "value": "64 Neoverse V2", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Embedded CPU", "source": [ "P20", "P11", "E01" ], "disclosure_date": "2026", "status": "production", "scope": "bf4" }, "network.bf4.9": { "value": "LPDDR5X; 250 GB/s", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "On-card memory", "source": [ "P20", "P11", "E01" ], "disclosure_date": "2026", "status": "production", "scope": "bf4" }, "network.bf4.10": { "value": "Ethernet / RDMA", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Transport / RDMA", "source": [ "P20", "P11", "E01" ], "disclosure_date": "2026", "status": "production", "scope": "bf4" }, "network.bf4.11": { "value": "Platform-dependent", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Congestion control", "source": [ "P20", "P11", "E01" ], "disclosure_date": "2026", "status": "production", "scope": "bf4" }, "network.bf4.12": { "value": "Infrastructure OS; STX / context storage; security", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Key offloads", "source": [ "P20", "P11", "E01" ], "disclosure_date": "2026", "status": "production", "scope": "bf4" }, "network.bf4.13": { "value": "n/d", "basis": "Per adapter/DPU unless platform explicitly labelled; network Gb/s is one direction line rate, not GB/s; power SKU-dependent", "field": "Power", "source": [ "P20", "P11", "E01" ], "disclosure_date": "2026", "status": "production", "scope": "bf4" }, "switch.s1.0": { "value": "Spectrum-1", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Family", "source": [ "P47" ], "disclosure_date": "2015", "status": "historical shipping", "scope": "s1" }, "switch.s1.1": { "value": "2015 generation", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Milestone", "source": [ "P47" ], "disclosure_date": "2015", "status": "historical shipping", "scope": "s1" }, "switch.s1.2": { "value": "3.2 Tb/s", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Published capacity", "source": [ "P47" ], "disclosure_date": "2015", "status": "historical shipping", "scope": "s1" }, "switch.s1.3": { "value": "Ethernet switching baseline", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Architecture / deployment meaning", "source": [ "P47" ], "disclosure_date": "2015", "status": "historical shipping", "scope": "s1" }, "switch.s2.0": { "value": "Spectrum-2", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Family", "source": [ "P51" ], "disclosure_date": "2018–2019", "status": "historical shipping", "scope": "s2" }, "switch.s2.1": { "value": "2018–2019 generation", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Milestone", "source": [ "P51" ], "disclosure_date": "2018–2019", "status": "historical shipping", "scope": "s2" }, "switch.s2.2": { "value": "6.4 Tb/s", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Published capacity", "source": [ "P51" ], "disclosure_date": "2018–2019", "status": "historical shipping", "scope": "s2" }, "switch.s2.3": { "value": "50G-class lanes; 200GbE ports", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Architecture / deployment meaning", "source": [ "P51" ], "disclosure_date": "2018–2019", "status": "historical shipping", "scope": "s2" }, "switch.s3.0": { "value": "Spectrum-3", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Family", "source": [ "P47" ], "disclosure_date": "2020", "status": "shipping", "scope": "s3" }, "switch.s3.1": { "value": "2020 generation", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Milestone", "source": [ "P47" ], "disclosure_date": "2020", "status": "shipping", "scope": "s3" }, "switch.s3.2": { "value": "12.8 Tb/s", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Published capacity", "source": [ "P47" ], "disclosure_date": "2020", "status": "shipping", "scope": "s3" }, "switch.s3.3": { "value": "400GbE generation", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Architecture / deployment meaning", "source": [ "P47" ], "disclosure_date": "2020", "status": "shipping", "scope": "s3" }, "switch.s4.0": { "value": "Spectrum-4 / Spectrum-X", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Family", "source": [ "E02", "P39" ], "disclosure_date": "2022–2023", "status": "shipping", "scope": "s4" }, "switch.s4.1": { "value": "2022 chip; 2023 platform", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Milestone", "source": [ "E02", "P39" ], "disclosure_date": "2022–2023", "status": "shipping", "scope": "s4" }, "switch.s4.2": { "value": "51.2 Tb/s", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Published capacity", "source": [ "E02", "P39" ], "disclosure_date": "2022–2023", "status": "shipping", "scope": "s4" }, "switch.s4.3": { "value": "400/800GbE; switch + SuperNIC + software co-design", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Architecture / deployment meaning", "source": [ "E02", "P39" ], "disclosure_date": "2022–2023", "status": "shipping", "scope": "s4" }, "switch.s6.0": { "value": "Spectrum-6", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Family", "source": [ "E10", "E09", "P39" ], "disclosure_date": "2026", "status": "production / adoption", "scope": "s6" }, "switch.s6.1": { "value": "2026 production / adoption", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Milestone", "source": [ "E10", "E09", "P39" ], "disclosure_date": "2026", "status": "production / adoption", "scope": "s6" }, "switch.s6.2": { "value": "102.4 Tb/s ASIC", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Published capacity", "source": [ "E10", "E09", "P39" ], "disclosure_date": "2026", "status": "production / adoption", "scope": "s6" }, "switch.s6.3": { "value": "Multiplane AI Ethernet; Vera Rubin ecosystem", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Architecture / deployment meaning", "source": [ "E10", "E09", "P39" ], "disclosure_date": "2026", "status": "production / adoption", "scope": "s6" }, "switch.photonics.0": { "value": "Spectrum-X / Quantum-X photonics", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Family", "source": [ "P23" ], "disclosure_date": "2025–2026", "status": "announced / rollout", "scope": "photonics" }, "switch.photonics.1": { "value": "2025–2026 disclosures", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Milestone", "source": [ "P23" ], "disclosure_date": "2025–2026", "status": "announced / rollout", "scope": "photonics" }, "switch.photonics.2": { "value": "Up to 409.6 Tb/s Spectrum-X assembly; not one ASIC", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Published capacity", "source": [ "P23" ], "disclosure_date": "2025–2026", "status": "announced / rollout", "scope": "photonics" }, "switch.photonics.3": { "value": "Co-packaged optics; product configuration and rollout vary", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Architecture / deployment meaning", "source": [ "P23" ], "disclosure_date": "2025–2026", "status": "announced / rollout", "scope": "photonics" }, "switch.qx.0": { "value": "Quantum-X800 / Q3450-LD", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Family", "source": [ "P23" ], "disclosure_date": "2025–2026", "status": "announced / rollout", "scope": "qx" }, "switch.qx.1": { "value": "2025–2026 disclosures", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Milestone", "source": [ "P23" ], "disclosure_date": "2025–2026", "status": "announced / rollout", "scope": "qx" }, "switch.qx.2": { "value": "144 × 800 Gb/s", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Published capacity", "source": [ "P23" ], "disclosure_date": "2025–2026", "status": "announced / rollout", "scope": "qx" }, "switch.qx.3": { "value": "CPO-based InfiniBand switch; 200G SerDes; liquid cooling", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Architecture / deployment meaning", "source": [ "P23" ], "disclosure_date": "2025–2026", "status": "announced / rollout", "scope": "qx" }, "switch.q2.0": { "value": "Quantum-2", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Family", "source": [ "P40" ], "disclosure_date": "2021–2022", "status": "shipping", "scope": "q2" }, "switch.q2.1": { "value": "2021 announcement; 2022 generation", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Milestone", "source": [ "P40" ], "disclosure_date": "2021–2022", "status": "shipping", "scope": "q2" }, "switch.q2.2": { "value": "64 × 400 Gb/s = 25.6 Tb/s one-way", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Published capacity", "source": [ "P40" ], "disclosure_date": "2021–2022", "status": "shipping", "scope": "q2" }, "switch.q2.3": { "value": "NDR InfiniBand; adaptive routing; SHARP collectives", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Architecture / deployment meaning", "source": [ "P40" ], "disclosure_date": "2021–2022", "status": "shipping", "scope": "q2" }, "systems.dgx1.0": { "value": "DGX-1 / P100", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Platform", "source": [ "P01" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "dgx1" }, "systems.dgx1.1": { "value": "2016", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "P01" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "dgx1" }, "systems.dgx1.2": { "value": "x86 + 8 P100", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "CPUs / accelerators", "source": [ "P01" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "dgx1" }, "systems.dgx1.3": { "value": "8 GPUs; nonuniform direct topology", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Scale-up domain", "source": [ "P01" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "dgx1" }, "systems.dgx1.4": { "value": "configuration-dependent", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Scale-out per accelerator", "source": [ "P01" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "dgx1" }, "systems.dgx1.5": { "value": "n/d", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Rack / system power", "source": [ "P01" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "dgx1" }, "systems.dgx1.6": { "value": "Air", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Cooling", "source": [ "P01" ], "disclosure_date": "2016", "status": "historical shipping", "scope": "dgx1" }, "systems.dgx2.0": { "value": "DGX-2 / V100", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Platform", "source": [ "P02", "P18" ], "disclosure_date": "2018", "status": "historical shipping", "scope": "dgx2" }, "systems.dgx2.1": { "value": "2018", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "P02", "P18" ], "disclosure_date": "2018", "status": "historical shipping", "scope": "dgx2" }, "systems.dgx2.2": { "value": "x86 + 16 V100", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "CPUs / accelerators", "source": [ "P02", "P18" ], "disclosure_date": "2018", "status": "historical shipping", "scope": "dgx2" }, "systems.dgx2.3": { "value": "16 GPUs / NVSwitch", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Scale-up domain", "source": [ "P02", "P18" ], "disclosure_date": "2018", "status": "historical shipping", "scope": "dgx2" }, "systems.dgx2.4": { "value": "configuration-dependent", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Scale-out per accelerator", "source": [ "P02", "P18" ], "disclosure_date": "2018", "status": "historical shipping", "scope": "dgx2" }, "systems.dgx2.5": { "value": "n/d", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Rack / system power", "source": [ "P02", "P18" ], "disclosure_date": "2018", "status": "historical shipping", "scope": "dgx2" }, "systems.dgx2.6": { "value": "Air", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Cooling", "source": [ "P02", "P18" ], "disclosure_date": "2018", "status": "historical shipping", "scope": "dgx2" }, "systems.hgxa.0": { "value": "HGX / DGX A100", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Platform", "source": [ "P03" ], "disclosure_date": "2020", "status": "historical shipping", "scope": "hgxa" }, "systems.hgxa.1": { "value": "2020", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "P03" ], "disclosure_date": "2020", "status": "historical shipping", "scope": "hgxa" }, "systems.hgxa.2": { "value": "x86 + 8 A100", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "CPUs / accelerators", "source": [ "P03" ], "disclosure_date": "2020", "status": "historical shipping", "scope": "hgxa" }, "systems.hgxa.3": { "value": "8 GPUs / NVSwitch", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Scale-up domain", "source": [ "P03" ], "disclosure_date": "2020", "status": "historical shipping", "scope": "hgxa" }, "systems.hgxa.4": { "value": "configuration-dependent", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Scale-out per accelerator", "source": [ "P03" ], "disclosure_date": "2020", "status": "historical shipping", "scope": "hgxa" }, "systems.hgxa.5": { "value": "n/d", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Rack / system power", "source": [ "P03" ], "disclosure_date": "2020", "status": "historical shipping", "scope": "hgxa" }, "systems.hgxa.6": { "value": "Platform-dependent", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Cooling", "source": [ "P03" ], "disclosure_date": "2020", "status": "historical shipping", "scope": "hgxa" }, "systems.hgxh.0": { "value": "HGX H100 / H200", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Platform", "source": [ "P13", "P14" ], "disclosure_date": "2022–2024", "status": "shipping", "scope": "hgxh" }, "systems.hgxh.1": { "value": "2022–2024", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "P13", "P14" ], "disclosure_date": "2022–2024", "status": "shipping", "scope": "hgxh" }, "systems.hgxh.2": { "value": "x86 + 8 GPUs", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "CPUs / accelerators", "source": [ "P13", "P14" ], "disclosure_date": "2022–2024", "status": "shipping", "scope": "hgxh" }, "systems.hgxh.3": { "value": "8 GPUs / NVSwitch", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Scale-up domain", "source": [ "P13", "P14" ], "disclosure_date": "2022–2024", "status": "shipping", "scope": "hgxh" }, "systems.hgxh.4": { "value": "configuration-dependent", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Scale-out per accelerator", "source": [ "P13", "P14" ], "disclosure_date": "2022–2024", "status": "shipping", "scope": "hgxh" }, "systems.hgxh.5": { "value": "n/d", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Rack / system power", "source": [ "P13", "P14" ], "disclosure_date": "2022–2024", "status": "shipping", "scope": "hgxh" }, "systems.hgxh.6": { "value": "Air / liquid by system", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Cooling", "source": [ "P13", "P14" ], "disclosure_date": "2022–2024", "status": "shipping", "scope": "hgxh" }, "systems.gh.0": { "value": "GH200 systems", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Platform", "source": [ "P08" ], "disclosure_date": "2023–2024", "status": "shipping", "scope": "gh" }, "systems.gh.1": { "value": "2023–2024", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "P08" ], "disclosure_date": "2023–2024", "status": "shipping", "scope": "gh" }, "systems.gh.2": { "value": "Grace + Hopper", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "CPUs / accelerators", "source": [ "P08" ], "disclosure_date": "2023–2024", "status": "shipping", "scope": "gh" }, "systems.gh.3": { "value": "Coherent module; wider topology by system", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Scale-up domain", "source": [ "P08" ], "disclosure_date": "2023–2024", "status": "shipping", "scope": "gh" }, "systems.gh.4": { "value": "configuration-dependent", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Scale-out per accelerator", "source": [ "P08" ], "disclosure_date": "2023–2024", "status": "shipping", "scope": "gh" }, "systems.gh.5": { "value": "n/d", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Rack / system power", "source": [ "P08" ], "disclosure_date": "2023–2024", "status": "shipping", "scope": "gh" }, "systems.gh.6": { "value": "Platform-dependent", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Cooling", "source": [ "P08" ], "disclosure_date": "2023–2024", "status": "shipping", "scope": "gh" }, "systems.gb200.0": { "value": "GB200 NVL72", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Platform", "source": [ "E16", "P27" ], "disclosure_date": "2025", "status": "shipping", "scope": "gb200" }, "systems.gb200.1": { "value": "2025", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "E16", "P27" ], "disclosure_date": "2025", "status": "shipping", "scope": "gb200" }, "systems.gb200.2": { "value": "36 Grace + 72 Blackwell", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "CPUs / accelerators", "source": [ "E16", "P27" ], "disclosure_date": "2025", "status": "shipping", "scope": "gb200" }, "systems.gb200.3": { "value": "72 GPU packages", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Scale-up domain", "source": [ "E16", "P27" ], "disclosure_date": "2025", "status": "shipping", "scope": "gb200" }, "systems.gb200.4": { "value": "Reference / cloud-specific; AWS 400 Gb/s EFA per GPU", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Scale-out per accelerator", "source": [ "E16", "P27" ], "disclosure_date": "2025", "status": "shipping", "scope": "gb200" }, "systems.gb200.5": { "value": "configuration-dependent", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Rack / system power", "source": [ "E16", "P27" ], "disclosure_date": "2025", "status": "shipping", "scope": "gb200" }, "systems.gb200.6": { "value": "Liquid", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Cooling", "source": [ "E16", "P27" ], "disclosure_date": "2025", "status": "shipping", "scope": "gb200" }, "systems.gb300.0": { "value": "GB300 NVL72", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Platform", "source": [ "P06", "E15" ], "disclosure_date": "2025", "status": "shipping", "scope": "gb300" }, "systems.gb300.1": { "value": "2025", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "P06", "E15" ], "disclosure_date": "2025", "status": "shipping", "scope": "gb300" }, "systems.gb300.2": { "value": "36 Grace + 72 Blackwell Ultra", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "CPUs / accelerators", "source": [ "P06", "E15" ], "disclosure_date": "2025", "status": "shipping", "scope": "gb300" }, "systems.gb300.3": { "value": "72 GPU packages", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Scale-up domain", "source": [ "P06", "E15" ], "disclosure_date": "2025", "status": "shipping", "scope": "gb300" }, "systems.gb300.4": { "value": "configuration-dependent", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Scale-out per accelerator", "source": [ "P06", "E15" ], "disclosure_date": "2025", "status": "shipping", "scope": "gb300" }, "systems.gb300.5": { "value": "configuration-dependent", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Rack / system power", "source": [ "P06", "E15" ], "disclosure_date": "2025", "status": "shipping", "scope": "gb300" }, "systems.gb300.6": { "value": "Liquid", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Cooling", "source": [ "P06", "E15" ], "disclosure_date": "2025", "status": "shipping", "scope": "gb300" }, "systems.rubin.0": { "value": "Vera Rubin NVL72", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Platform", "source": [ "P11", "P38", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "rubin" }, "systems.rubin.1": { "value": "2026", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "P11", "P38", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "rubin" }, "systems.rubin.2": { "value": "36 Vera + 72 Rubin", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "CPUs / accelerators", "source": [ "P11", "P38", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "rubin" }, "systems.rubin.3": { "value": "72 GPU packages", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Scale-up domain", "source": [ "P11", "P38", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "rubin" }, "systems.rubin.4": { "value": "200 GB/s one-way reference; 225 GB/s MaxLPS page", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Scale-out per accelerator", "source": [ "P11", "P38", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "rubin" }, "systems.rubin.5": { "value": "configuration-dependent", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Rack / system power", "source": [ "P11", "P38", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "rubin" }, "systems.rubin.6": { "value": "Liquid", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Cooling", "source": [ "P11", "P38", "E08" ], "disclosure_date": "2026", "status": "production / preview", "scope": "rubin" }, "systems.lpx.0": { "value": "Groq 3 LPX", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Platform", "source": [ "P12", "E09" ], "disclosure_date": "2026", "status": "production", "scope": "lpx" }, "systems.lpx.1": { "value": "2026", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "P12", "E09" ], "disclosure_date": "2026", "status": "production", "scope": "lpx" }, "systems.lpx.2": { "value": "256 LPUs; 32 trays", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "CPUs / accelerators", "source": [ "P12", "E09" ], "disclosure_date": "2026", "status": "production", "scope": "lpx" }, "systems.lpx.3": { "value": "LPU fabric; not NVLink GPU domain", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Scale-up domain", "source": [ "P12", "E09" ], "disclosure_date": "2026", "status": "production", "scope": "lpx" }, "systems.lpx.4": { "value": "n/d", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Scale-out per accelerator", "source": [ "P12", "E09" ], "disclosure_date": "2026", "status": "production", "scope": "lpx" }, "systems.lpx.5": { "value": "n/d", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Rack / system power", "source": [ "P12", "E09" ], "disclosure_date": "2026", "status": "production", "scope": "lpx" }, "systems.lpx.6": { "value": "Liquid", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Cooling", "source": [ "P12", "E09" ], "disclosure_date": "2026", "status": "production", "scope": "lpx" }, "ratios.h200cap.0": { "value": "H200 / H100 capacity", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Comparison", "source": [ "P13", "P14" ], "disclosure_date": "2024", "status": "derived", "scope": "h200cap" }, "ratios.h200cap.1": { "value": "141 / 80 = 1.76×", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Calculation", "source": [ "P13", "P14" ], "disclosure_date": "2024", "status": "derived", "scope": "h200cap" }, "ratios.h200cap.2": { "value": "More model / KV capacity without a new SM generation", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Interpretation", "source": [ "P13", "P14" ], "disclosure_date": "2024", "status": "derived", "scope": "h200cap" }, "ratios.h200bw.0": { "value": "H200 / H100 HBM bandwidth", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Comparison", "source": [ "P13", "P14" ], "disclosure_date": "2024", "status": "derived", "scope": "h200bw" }, "ratios.h200bw.1": { "value": "4.8 / 3.35 = 1.43×", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Calculation", "source": [ "P13", "P14" ], "disclosure_date": "2024", "status": "derived", "scope": "h200bw" }, "ratios.h200bw.2": { "value": "Bandwidth gain differs from capacity gain", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Interpretation", "source": [ "P13", "P14" ], "disclosure_date": "2024", "status": "derived", "scope": "h200bw" }, "ratios.gracecore.0": { "value": "Grace peak memory per core", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Comparison", "source": [ "P09", "P11" ], "disclosure_date": "2026 comparison", "status": "derived", "scope": "gracecore" }, "ratios.gracecore.1": { "value": "512 / 72 = 7.11 GB/s", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Calculation", "source": [ "P09", "P11" ], "disclosure_date": "2026 comparison", "status": "derived", "scope": "gracecore" }, "ratios.gracecore.2": { "value": "Aggregate divided by cores; not a guarantee per core", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Interpretation", "source": [ "P09", "P11" ], "disclosure_date": "2026 comparison", "status": "derived", "scope": "gracecore" }, "ratios.veracore.0": { "value": "Vera peak memory per core", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Comparison", "source": [ "P10", "P11" ], "disclosure_date": "2026", "status": "derived", "scope": "veracore" }, "ratios.veracore.1": { "value": "1200 / 88 = 13.64 GB/s", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Calculation", "source": [ "P10", "P11" ], "disclosure_date": "2026", "status": "derived", "scope": "veracore" }, "ratios.veracore.2": { "value": "1.92× Grace on this basis", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Interpretation", "source": [ "P10", "P11" ], "disclosure_date": "2026", "status": "derived", "scope": "veracore" }, "ratios.rubinbw.0": { "value": "Rubin HBM / NVLink, MaxLPS", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Comparison", "source": [ "P38" ], "disclosure_date": "2026", "status": "derived", "scope": "rubinbw" }, "ratios.rubinbw.1": { "value": "19.2 / (3 / 2) = 12.8×", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Calculation", "source": [ "P38" ], "disclosure_date": "2026", "status": "derived", "scope": "rubinbw" }, "ratios.rubinbw.2": { "value": "Local HBM bandwidth exceeds one-way peer injection", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Interpretation", "source": [ "P38" ], "disclosure_date": "2026", "status": "derived", "scope": "rubinbw" }, "ratios.rubinnet.0": { "value": "Rubin NVLink / scale-out, MaxLPS", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Comparison", "source": [ "P38" ], "disclosure_date": "2026", "status": "derived", "scope": "rubinnet" }, "ratios.rubinnet.1": { "value": "(3 / 2) / (0.45 / 2) = 6.67×", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Calculation", "source": [ "P38" ], "disclosure_date": "2026", "status": "derived", "scope": "rubinnet" }, "ratios.rubinnet.2": { "value": "Rack-local placement can avoid a slower network tier", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Interpretation", "source": [ "P38" ], "disclosure_date": "2026", "status": "derived", "scope": "rubinnet" }, "ratios.cx.0": { "value": "800 Gb/s network conversion", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Comparison", "source": [ "P19", "P21" ], "disclosure_date": "2025–2026", "status": "derived", "scope": "cx" }, "ratios.cx.1": { "value": "800 / 8 = 100 GB/s", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Calculation", "source": [ "P19", "P21" ], "disclosure_date": "2025–2026", "status": "derived", "scope": "cx" }, "ratios.cx.2": { "value": "Line rate before protocol and PCIe overheads", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Interpretation", "source": [ "P19", "P21" ], "disclosure_date": "2025–2026", "status": "derived", "scope": "cx" }, "software.cuda8.0": { "value": "CUDA / Pascal", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Release / family", "source": [ "P01", "P36" ], "disclosure_date": "2016", "status": "released", "scope": "cuda8" }, "software.cuda8.1": { "value": "2016", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Date / era", "source": [ "P01", "P36" ], "disclosure_date": "2016", "status": "released", "scope": "cuda8" }, "software.cuda8.2": { "value": "P100", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Hardware enabled", "source": [ "P01", "P36" ], "disclosure_date": "2016", "status": "released", "scope": "cuda8" }, "software.cuda8.3": { "value": "Unified memory evolution; Pascal programming", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Key features", "source": [ "P01", "P36" ], "disclosure_date": "2016", "status": "released", "scope": "cuda8" }, "software.cuda9.0": { "value": "CUDA / Volta", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Release / family", "source": [ "P02", "P35" ], "disclosure_date": "2017", "status": "released", "scope": "cuda9" }, "software.cuda9.1": { "value": "2017", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Date / era", "source": [ "P02", "P35" ], "disclosure_date": "2017", "status": "released", "scope": "cuda9" }, "software.cuda9.2": { "value": "V100", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Hardware enabled", "source": [ "P02", "P35" ], "disclosure_date": "2017", "status": "released", "scope": "cuda9" }, "software.cuda9.3": { "value": "Tensor programming; independent scheduling", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Key features", "source": [ "P02", "P35" ], "disclosure_date": "2017", "status": "released", "scope": "cuda9" }, "software.ampere.0": { "value": "Ampere software generation", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Release / family", "source": [ "P03", "P34" ], "disclosure_date": "2020", "status": "released", "scope": "ampere" }, "software.ampere.1": { "value": "2020", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Date / era", "source": [ "P03", "P34" ], "disclosure_date": "2020", "status": "released", "scope": "ampere" }, "software.ampere.2": { "value": "A100", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Hardware enabled", "source": [ "P03", "P34" ], "disclosure_date": "2020", "status": "released", "scope": "ampere" }, "software.ampere.3": { "value": "TF32 / BF16 libraries; MIG; sparsity support", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Key features", "source": [ "P03", "P34" ], "disclosure_date": "2020", "status": "released", "scope": "ampere" }, "software.hopper.0": { "value": "Hopper software generation", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Release / family", "source": [ "P04", "P33" ], "disclosure_date": "2022–2024", "status": "released", "scope": "hopper" }, "software.hopper.1": { "value": "2022–2024", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Date / era", "source": [ "P04", "P33" ], "disclosure_date": "2022–2024", "status": "released", "scope": "hopper" }, "software.hopper.2": { "value": "H100 / H200 / GH200", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Hardware enabled", "source": [ "P04", "P33" ], "disclosure_date": "2022–2024", "status": "released", "scope": "hopper" }, "software.hopper.3": { "value": "Transformer Engine; TMA; clusters; FP8", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Key features", "source": [ "P04", "P33" ], "disclosure_date": "2022–2024", "status": "released", "scope": "hopper" }, "software.blackwell.0": { "value": "Blackwell software generation", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Release / family", "source": [ "P06", "P32" ], "disclosure_date": "2024–2026", "status": "released", "scope": "blackwell" }, "software.blackwell.1": { "value": "2024–2026", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Date / era", "source": [ "P06", "P32" ], "disclosure_date": "2024–2026", "status": "released", "scope": "blackwell" }, "software.blackwell.2": { "value": "B200 / B300 / GB200 / GB300", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Hardware enabled", "source": [ "P06", "P32" ], "disclosure_date": "2024–2026", "status": "released", "scope": "blackwell" }, "software.blackwell.3": { "value": "FP4 / FP6; Tensor Memory; revised kernels", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Key features", "source": [ "P06", "P32" ], "disclosure_date": "2024–2026", "status": "released", "scope": "blackwell" }, "software.nccl.0": { "value": "NCCL / NVSHMEM ecosystem", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Release / family", "source": [ "P44", "P39" ], "disclosure_date": "ongoing", "status": "released", "scope": "nccl" }, "software.nccl.1": { "value": "Cross-generation", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Date / era", "source": [ "P44", "P39" ], "disclosure_date": "ongoing", "status": "released", "scope": "nccl" }, "software.nccl.2": { "value": "GPU fabrics", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Hardware enabled", "source": [ "P44", "P39" ], "disclosure_date": "ongoing", "status": "released", "scope": "nccl" }, "software.nccl.3": { "value": "Collective communication and GPU-oriented communication; topology-aware algorithms", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Key features", "source": [ "P44", "P39" ], "disclosure_date": "ongoing", "status": "released", "scope": "nccl" }, "software.doca.0": { "value": "DOCA", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Release / family", "source": [ "P20", "P24", "P25" ], "disclosure_date": "ongoing", "status": "released", "scope": "doca" }, "software.doca.1": { "value": "BlueField era", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Date / era", "source": [ "P20", "P24", "P25" ], "disclosure_date": "ongoing", "status": "released", "scope": "doca" }, "software.doca.2": { "value": "BlueField / ConnectX", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Hardware enabled", "source": [ "P20", "P24", "P25" ], "disclosure_date": "ongoing", "status": "released", "scope": "doca" }, "software.doca.3": { "value": "Infrastructure offload APIs and services", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Key features", "source": [ "P20", "P24", "P25" ], "disclosure_date": "ongoing", "status": "released", "scope": "doca" }, "software.dynamo.0": { "value": "Dynamo", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Release / family", "source": [ "E17", "E08" ], "disclosure_date": "2025–2026", "status": "released", "scope": "dynamo" }, "software.dynamo.1": { "value": "2025 onward", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Date / era", "source": [ "E17", "E08" ], "disclosure_date": "2025–2026", "status": "released", "scope": "dynamo" }, "software.dynamo.2": { "value": "Distributed inference", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Hardware enabled", "source": [ "E17", "E08" ], "disclosure_date": "2025–2026", "status": "released", "scope": "dynamo" }, "software.dynamo.3": { "value": "Disaggregated serving; scheduling and data movement", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Key features", "source": [ "E17", "E08" ], "disclosure_date": "2025–2026", "status": "released", "scope": "dynamo" }, "venues.hc16.0": { "value": "Hot Chips", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Venue", "source": [ "C01" ], "disclosure_date": "2016", "status": "disclosed", "scope": "hc16" }, "venues.hc16.1": { "value": "2016", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "C01" ], "disclosure_date": "2016", "status": "disclosed", "scope": "hc16" }, "venues.hc16.2": { "value": "Ultra-Performance Pascal GPU and NVLink Interconnect", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Paper / talk", "source": [ "C01" ], "disclosure_date": "2016", "status": "disclosed", "scope": "hc16" }, "venues.hc16.3": { "value": "Denis Foley", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Presenters / authors", "source": [ "C01" ], "disclosure_date": "2016", "status": "disclosed", "scope": "hc16" }, "venues.hc16.4": { "value": "P100 / NVLink 1", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Product / generation", "source": [ "C01" ], "disclosure_date": "2016", "status": "disclosed", "scope": "hc16" }, "venues.hc16.5": { "value": "Product architecture", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Disclosure type", "source": [ "C01" ], "disclosure_date": "2016", "status": "disclosed", "scope": "hc16" }, "venues.hc16.6": { "value": "C01", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Source / link ID", "source": [ "C01" ], "disclosure_date": "2016", "status": "disclosed", "scope": "hc16" }, "venues.hc17.0": { "value": "Hot Chips", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Venue", "source": [ "C02" ], "disclosure_date": "2017", "status": "disclosed", "scope": "hc17" }, "venues.hc17.1": { "value": "2017", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "C02" ], "disclosure_date": "2017", "status": "disclosed", "scope": "hc17" }, "venues.hc17.2": { "value": "NVIDIA’s Volta GPU: Programmability and Performance for GPU Computing", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Paper / talk", "source": [ "C02" ], "disclosure_date": "2017", "status": "disclosed", "scope": "hc17" }, "venues.hc17.3": { "value": "Jack Choquette", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Presenters / authors", "source": [ "C02" ], "disclosure_date": "2017", "status": "disclosed", "scope": "hc17" }, "venues.hc17.4": { "value": "V100", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Product / generation", "source": [ "C02" ], "disclosure_date": "2017", "status": "disclosed", "scope": "hc17" }, "venues.hc17.5": { "value": "Product architecture", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Disclosure type", "source": [ "C02" ], "disclosure_date": "2017", "status": "disclosed", "scope": "hc17" }, "venues.hc17.6": { "value": "C02", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Source / link ID", "source": [ "C02" ], "disclosure_date": "2017", "status": "disclosed", "scope": "hc17" }, "venues.hc20.0": { "value": "Hot Chips", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Venue", "source": [ "C03" ], "disclosure_date": "2020", "status": "disclosed", "scope": "hc20" }, "venues.hc20.1": { "value": "2020", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "C03" ], "disclosure_date": "2020", "status": "disclosed", "scope": "hc20" }, "venues.hc20.2": { "value": "A100 / Ampere architecture", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Paper / talk", "source": [ "C03" ], "disclosure_date": "2020", "status": "disclosed", "scope": "hc20" }, "venues.hc20.3": { "value": "NVIDIA", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Presenters / authors", "source": [ "C03" ], "disclosure_date": "2020", "status": "disclosed", "scope": "hc20" }, "venues.hc20.4": { "value": "A100", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Product / generation", "source": [ "C03" ], "disclosure_date": "2020", "status": "disclosed", "scope": "hc20" }, "venues.hc20.5": { "value": "Product architecture", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Disclosure type", "source": [ "C03" ], "disclosure_date": "2020", "status": "disclosed", "scope": "hc20" }, "venues.hc20.6": { "value": "C03", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Source / link ID", "source": [ "C03" ], "disclosure_date": "2020", "status": "disclosed", "scope": "hc20" }, "venues.hc22h.0": { "value": "Hot Chips", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Venue", "source": [ "C04" ], "disclosure_date": "2022", "status": "disclosed", "scope": "hc22h" }, "venues.hc22h.1": { "value": "2022", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "C04" ], "disclosure_date": "2022", "status": "disclosed", "scope": "hc22h" }, "venues.hc22h.2": { "value": "NVIDIA’s Hopper GPU: Scaling Performance", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Paper / talk", "source": [ "C04" ], "disclosure_date": "2022", "status": "disclosed", "scope": "hc22h" }, "venues.hc22h.3": { "value": "Jack Choquette", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Presenters / authors", "source": [ "C04" ], "disclosure_date": "2022", "status": "disclosed", "scope": "hc22h" }, "venues.hc22h.4": { "value": "H100", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Product / generation", "source": [ "C04" ], "disclosure_date": "2022", "status": "disclosed", "scope": "hc22h" }, "venues.hc22h.5": { "value": "Product architecture", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Disclosure type", "source": [ "C04" ], "disclosure_date": "2022", "status": "disclosed", "scope": "hc22h" }, "venues.hc22h.6": { "value": "C04", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Source / link ID", "source": [ "C04" ], "disclosure_date": "2022", "status": "disclosed", "scope": "hc22h" }, "venues.hc22g.0": { "value": "Hot Chips", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Venue", "source": [ "C04" ], "disclosure_date": "2022", "status": "disclosed", "scope": "hc22g" }, "venues.hc22g.1": { "value": "2022", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "C04" ], "disclosure_date": "2022", "status": "disclosed", "scope": "hc22g" }, "venues.hc22g.2": { "value": "NVIDIA’s Grace CPU", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Paper / talk", "source": [ "C04" ], "disclosure_date": "2022", "status": "disclosed", "scope": "hc22g" }, "venues.hc22g.3": { "value": "NVIDIA", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Presenters / authors", "source": [ "C04" ], "disclosure_date": "2022", "status": "disclosed", "scope": "hc22g" }, "venues.hc22g.4": { "value": "Grace", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Product / generation", "source": [ "C04" ], "disclosure_date": "2022", "status": "disclosed", "scope": "hc22g" }, "venues.hc22g.5": { "value": "CPU / memory system", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Disclosure type", "source": [ "C04" ], "disclosure_date": "2022", "status": "disclosed", "scope": "hc22g" }, "venues.hc22g.6": { "value": "C04", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Source / link ID", "source": [ "C04" ], "disclosure_date": "2022", "status": "disclosed", "scope": "hc22g" }, "venues.hc22n.0": { "value": "Hot Chips", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Venue", "source": [ "C04" ], "disclosure_date": "2022", "status": "disclosed", "scope": "hc22n" }, "venues.hc22n.1": { "value": "2022", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "C04" ], "disclosure_date": "2022", "status": "disclosed", "scope": "hc22n" }, "venues.hc22n.2": { "value": "NVLink-Network Switch", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Paper / talk", "source": [ "C04" ], "disclosure_date": "2022", "status": "disclosed", "scope": "hc22n" }, "venues.hc22n.3": { "value": "NVIDIA", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Presenters / authors", "source": [ "C04" ], "disclosure_date": "2022", "status": "disclosed", "scope": "hc22n" }, "venues.hc22n.4": { "value": "NVLink switch", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Product / generation", "source": [ "C04" ], "disclosure_date": "2022", "status": "disclosed", "scope": "hc22n" }, "venues.hc22n.5": { "value": "Scale-up architecture", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Disclosure type", "source": [ "C04" ], "disclosure_date": "2022", "status": "disclosed", "scope": "hc22n" }, "venues.hc22n.6": { "value": "C04", "basis": "As labelled; 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peak unless specified; n/d means not established by reviewed sources", "field": "Source / link ID", "source": [ "R07" ], "disclosure_date": "2018", "status": "disclosed", "scope": "iss18" }, "venues.iss21.0": { "value": "ISSCC", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Venue", "source": [ "C08" ], "disclosure_date": "2021", "status": "disclosed", "scope": "iss21" }, "venues.iss21.1": { "value": "2021", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "C08" ], "disclosure_date": "2021", "status": "disclosed", "scope": "iss21" }, "venues.iss21.2": { "value": "3.2 The A100 Datacenter GPU and Ampere Architecture", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Paper / talk", "source": [ "C08" ], "disclosure_date": "2021", "status": "disclosed", "scope": "iss21" }, "venues.iss21.3": { "value": "Jack Choquette et al.", "basis": "As labelled; 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peak unless specified; n/d means not established by reviewed sources", "field": "Product / generation", "source": [ "C09" ], "disclosure_date": "2023", "status": "disclosed", "scope": "iss23" }, "venues.iss23.5": { "value": "Official press kit; PHY implementation", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Disclosure type", "source": [ "C09" ], "disclosure_date": "2023", "status": "disclosed", "scope": "iss23" }, "venues.iss23.6": { "value": "C09", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Source / link ID", "source": [ "C09" ], "disclosure_date": "2023", "status": "disclosed", "scope": "iss23" }, "venues.iss26.0": { "value": "ISSCC", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Venue", "source": [ "C10" ], "disclosure_date": "2026", "status": "disclosed", "scope": "iss26" }, "venues.iss26.1": { "value": "2026", "basis": "As labelled; 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Rosseel; N. Pinckney", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Presenters / authors", "source": [ "C10" ], "disclosure_date": "2026", "status": "disclosed", "scope": "iss26" }, "venues.iss26.4": { "value": "GB10", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Product / generation", "source": [ "C10" ], "disclosure_date": "2026", "status": "disclosed", "scope": "iss26" }, "venues.iss26.5": { "value": "Official program; full paper not inspected", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Disclosure type", "source": [ "C10" ], "disclosure_date": "2026", "status": "disclosed", "scope": "iss26" }, "venues.iss26.6": { "value": "C10", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Source / link ID", "source": [ "C10" ], "disclosure_date": "2026", "status": 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"status": "disclosed", "scope": "micro17b" }, "venues.micro17b.1": { "value": "2017", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "R03" ], "disclosure_date": "2017", "status": "disclosed", "scope": "micro17b" }, "venues.micro17b.2": { "value": "Fine-Grained DRAM: Energy-Efficient DRAM for Extreme Bandwidth Systems", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Paper / talk", "source": [ "R03" ], "disclosure_date": "2017", "status": "disclosed", "scope": "micro17b" }, "venues.micro17b.3": { "value": "Mike O’Connor et al.", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Presenters / authors", "source": [ "R03" ], "disclosure_date": "2017", "status": "disclosed", "scope": "micro17b" }, "venues.micro17b.4": { "value": "Memory research", "basis": "As labelled; peak unless specified; n/d means not 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unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "R10" ], "disclosure_date": "2019", "status": "disclosed", "scope": "micro19" }, "venues.micro19.2": { "value": "Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Paper / talk", "source": [ "R10" ], "disclosure_date": "2019", "status": "disclosed", "scope": "micro19" }, "venues.micro19.3": { "value": "Yakun Sophia Shao et al.", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Presenters / authors", "source": [ "R10" ], "disclosure_date": "2019", "status": "disclosed", "scope": "micro19" }, "venues.micro19.4": { "value": "Simba", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Product / generation", "source": [ "R10" ], "disclosure_date": "2019", "status": "disclosed", "scope": "micro19" }, "venues.micro19.5": { "value": "Research accelerator", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Disclosure type", "source": [ "R10" ], "disclosure_date": "2019", "status": "disclosed", "scope": "micro19" }, "venues.micro19.6": { "value": "R10", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Source / link ID", "source": [ "R10" ], "disclosure_date": "2019", "status": "disclosed", "scope": "micro19" }, "venues.hpca15.0": { "value": "HPCA", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Venue", "source": [ "R04" ], "disclosure_date": "2015", "status": "disclosed", "scope": "hpca15" }, "venues.hpca15.1": { "value": "2015", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "R04" ], "disclosure_date": "2015", "status": "disclosed", "scope": "hpca15" }, "venues.hpca15.2": { "value": "Unlocking Bandwidth for GPUs in CC-NUMA Systems", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Paper / talk", "source": [ "R04" ], "disclosure_date": "2015", "status": "disclosed", "scope": "hpca15" }, "venues.hpca15.3": { "value": "Neha Agarwal et al.", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Presenters / authors", "source": [ "R04" ], "disclosure_date": "2015", "status": "disclosed", "scope": "hpca15" }, "venues.hpca15.4": { "value": "Coherent-memory placement", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Product / generation", "source": [ "R04" ], "disclosure_date": "2015", "status": "disclosed", "scope": "hpca15" }, "venues.hpca15.5": { "value": "Research; not Grace specification", "basis": "As labelled; peak unless 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], "disclosure_date": "2015", "status": "disclosed", "scope": "asplos15" }, "venues.asplos15.6": { "value": "R05", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Source / link ID", "source": [ "R05" ], "disclosure_date": "2015", "status": "disclosed", "scope": "asplos15" }, "venues.taco21.0": { "value": "ACM TACO", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Venue", "source": [ "R06" ], "disclosure_date": "2021", "status": "disclosed", "scope": "taco21" }, "venues.taco21.1": { "value": "2021", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "R06" ], "disclosure_date": "2021", "status": "disclosed", "scope": "taco21" }, "venues.taco21.2": { "value": "GPU Domain Specialization via Composable On-Package Architecture", "basis": "As labelled; peak unless specified; n/d means not established by reviewed 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}, "venues.dac21.3": { "value": "NVIDIA research team", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Presenters / authors", "source": [ "P41" ], "disclosure_date": "2021–2022", "status": "disclosed", "scope": "dac21" }, "venues.dac21.4": { "value": "Hopper design flow", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Product / generation", "source": [ "P41" ], "disclosure_date": "2021–2022", "status": "disclosed", "scope": "dac21" }, "venues.dac21.5": { "value": "Explicit product adoption in follow-up", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Disclosure type", "source": [ "P41" ], "disclosure_date": "2021–2022", "status": "disclosed", "scope": "dac21" }, "venues.dac21.6": { "value": "P41", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Source / link ID", "source": [ "P41" ], "disclosure_date": "2021–2022", "status": "disclosed", "scope": "dac21" }, "venues.gtc.0": { "value": "GTC", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Venue", "source": [ "P01", "P02", "P03", "P04", "E03", "E07" ], "disclosure_date": "2016–2026", "status": "disclosed", "scope": "gtc" }, "venues.gtc.1": { "value": "2016–2026", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "P01", "P02", "P03", "P04", "E03", "E07" ], "disclosure_date": "2016–2026", "status": "disclosed", "scope": "gtc" }, "venues.gtc.2": { "value": "P100 → Volta → Ampere → Hopper → Blackwell → Rubin", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Paper / talk", "source": [ "P01", "P02", "P03", "P04", "E03", "E07" ], "disclosure_date": "2016–2026", "status": "disclosed", "scope": "gtc" }, "venues.gtc.3": { "value": "NVIDIA", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Presenters / authors", "source": [ "P01", "P02", "P03", "P04", "E03", "E07" ], "disclosure_date": "2016–2026", "status": "disclosed", "scope": "gtc" }, "venues.gtc.4": { "value": "Full platform", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Product / generation", "source": [ "P01", "P02", "P03", "P04", "E03", "E07" ], "disclosure_date": "2016–2026", "status": "disclosed", "scope": "gtc" }, "venues.gtc.5": { "value": "Launch, architecture, software, roadmap", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Disclosure type", "source": [ "P01", "P02", "P03", "P04", "E03", "E07" ], "disclosure_date": "2016–2026", "status": "disclosed", "scope": "gtc" }, "venues.gtc.6": { "value": "P01 P02 P03 P04 E03 E07", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Source / link ID", "source": [ "P01", "P02", "P03", "P04", "E03", "E07" ], "disclosure_date": "2016–2026", "status": "disclosed", "scope": "gtc" }, "venues.computex.0": { "value": "Computex", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Venue", "source": [ "P19", "P27" ], "disclosure_date": "2025", "status": "disclosed", "scope": "computex" }, "venues.computex.1": { "value": "2025", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "P19", "P27" ], "disclosure_date": "2025", "status": "disclosed", "scope": "computex" }, "venues.computex.2": { "value": "ConnectX-8 and NVLink Fusion", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Paper / talk", "source": [ "P19", "P27" ], "disclosure_date": "2025", "status": "disclosed", "scope": "computex" }, "venues.computex.3": { "value": "NVIDIA", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Presenters / authors", "source": [ "P19", "P27" ], "disclosure_date": "2025", "status": "disclosed", "scope": "computex" }, "venues.computex.4": { "value": "Network and ecosystem", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Product / generation", "source": [ "P19", "P27" ], "disclosure_date": "2025", "status": "disclosed", "scope": "computex" }, "venues.computex.5": { "value": "Product / ecosystem", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Disclosure type", "source": [ "P19", "P27" ], "disclosure_date": "2025", "status": "disclosed", "scope": "computex" }, "venues.computex.6": { "value": "P19 P27", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Source / link ID", "source": [ "P19", "P27" ], "disclosure_date": "2025", "status": "disclosed", "scope": "computex" }, "venues.sc20.0": { "value": "SC20", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Venue", "source": [ "E20", "P15" ], "disclosure_date": "2020", "status": "disclosed", "scope": "sc20" }, "venues.sc20.1": { "value": "2020", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "E20", "P15" ], "disclosure_date": "2020", "status": "disclosed", "scope": "sc20" }, "venues.sc20.2": { "value": "A100 80 GB", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Paper / talk", "source": [ "E20", "P15" ], "disclosure_date": "2020", "status": "disclosed", "scope": "sc20" }, "venues.sc20.3": { "value": "NVIDIA", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Presenters / authors", "source": [ "E20", "P15" ], "disclosure_date": "2020", "status": "disclosed", "scope": "sc20" }, "venues.sc20.4": { "value": "A100 / HGX", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Product / generation", "source": [ "E20", "P15" ], "disclosure_date": "2020", "status": "disclosed", "scope": "sc20" }, "venues.sc20.5": { "value": "Memory refresh announcement", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Disclosure type", "source": [ "E20", "P15" ], "disclosure_date": "2020", "status": "disclosed", "scope": "sc20" }, "venues.sc20.6": { "value": "E20 P15", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Source / link ID", "source": [ "E20", "P15" ], "disclosure_date": "2020", "status": "disclosed", "scope": "sc20" }, "venues.ocp.0": { "value": "OCP Global Summit", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Venue", "source": [ "E12" ], "disclosure_date": "2025", "status": "disclosed", "scope": "ocp" }, "venues.ocp.1": { "value": "2025", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "E12" ], "disclosure_date": "2025", "status": "disclosed", "scope": "ocp" }, "venues.ocp.2": { "value": "MGX, power delivery and AI-factory infrastructure", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Paper / talk", "source": [ "E12" ], "disclosure_date": "2025", "status": "disclosed", "scope": "ocp" }, "venues.ocp.3": { "value": "NVIDIA / partners", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Presenters / authors", "source": [ "E12" ], "disclosure_date": "2025", "status": "disclosed", "scope": "ocp" }, "venues.ocp.4": { "value": "Rack ecosystem; future power designs", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Product / generation", "source": [ "E12" ], "disclosure_date": "2025", "status": "disclosed", "scope": "ocp" }, "venues.ocp.5": { "value": "System integration / roadmap", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Disclosure type", "source": [ "E12" ], "disclosure_date": "2025", "status": "disclosed", "scope": "ocp" }, "venues.ocp.6": { "value": "E12", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Source / link ID", "source": [ "E12" ], "disclosure_date": "2025", "status": "disclosed", "scope": "ocp" }, "venues.aws.0": { "value": "AWS re:Invent", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Venue", "source": [ "E13", "E16" ], "disclosure_date": "2025", "status": "disclosed", "scope": "aws" }, "venues.aws.1": { "value": "2025", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "E13", "E16" ], "disclosure_date": "2025", "status": "disclosed", "scope": "aws" }, "venues.aws.2": { "value": "NVIDIA platforms and NVLink Fusion collaboration", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Paper / talk", "source": [ "E13", "E16" ], "disclosure_date": "2025", "status": "disclosed", "scope": "aws" }, "venues.aws.3": { "value": "AWS / NVIDIA", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Presenters / authors", "source": [ "E13", "E16" ], "disclosure_date": "2025", "status": "disclosed", "scope": "aws" }, "venues.aws.4": { "value": "Blackwell / Fusion", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Product / generation", "source": [ "E13", "E16" ], "disclosure_date": "2025", "status": "disclosed", "scope": "aws" }, "venues.aws.5": { "value": "Ecosystem; GA verified separately", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Disclosure type", "source": [ "E13", "E16" ], "disclosure_date": "2025", "status": "disclosed", "scope": "aws" }, "venues.aws.6": { "value": "E13 E16", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Source / link ID", "source": [ "E13", "E16" ], "disclosure_date": "2025", "status": "disclosed", "scope": "aws" }, "venues.ignite.0": { "value": "Microsoft Ignite", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Venue", "source": [ "E15" ], "disclosure_date": "2025", "status": "disclosed", "scope": "ignite" }, "venues.ignite.1": { "value": "2025", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "E15" ], "disclosure_date": "2025", "status": "disclosed", "scope": "ignite" }, "venues.ignite.2": { "value": "Azure ND GB300 v6 GA", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Paper / talk", "source": [ "E15" ], "disclosure_date": "2025", "status": "disclosed", "scope": "ignite" }, "venues.ignite.3": { "value": "Microsoft", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Presenters / authors", "source": [ "E15" ], "disclosure_date": "2025", "status": "disclosed", "scope": "ignite" }, "venues.ignite.4": { "value": "GB300 NVL72", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Product / generation", "source": [ "E15" ], "disclosure_date": "2025", "status": "disclosed", "scope": "ignite" }, "venues.ignite.5": { "value": "Cloud GA", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Disclosure type", "source": [ "E15" ], "disclosure_date": "2025", "status": "disclosed", "scope": "ignite" }, "venues.ignite.6": { "value": "E15", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Source / link ID", "source": [ "E15" ], "disclosure_date": "2025", "status": "disclosed", "scope": "ignite" }, "venues.next.0": { "value": "Google Cloud Next / update", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Venue", "source": [ "E14" ], "disclosure_date": "2025", "status": "disclosed", "scope": "next" }, "venues.next.1": { "value": "2025", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "E14" ], "disclosure_date": "2025", "status": "disclosed", "scope": "next" }, "venues.next.2": { "value": "A4X / GB200", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Paper / talk", "source": [ "E14" ], "disclosure_date": "2025", "status": "disclosed", "scope": "next" }, "venues.next.3": { "value": "Google Cloud", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Presenters / authors", "source": [ "E14" ], "disclosure_date": "2025", "status": "disclosed", "scope": "next" }, "venues.next.4": { "value": "GB200", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Product / generation", "source": [ "E14" ], "disclosure_date": "2025", "status": "disclosed", "scope": "next" }, "venues.next.5": { "value": "Cloud product; May GA update", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Disclosure type", "source": [ "E14" ], "disclosure_date": "2025", "status": "disclosed", "scope": "next" }, "venues.next.6": { "value": "E14", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Source / link ID", "source": [ "E14" ], "disclosure_date": "2025", "status": "disclosed", "scope": "next" }, "venues.mwc.0": { "value": "MWC / AI-RAN", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Venue", "source": [ "E19" ], "disclosure_date": "2025", "status": "disclosed", "scope": "mwc" }, "venues.mwc.1": { "value": "2025", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "E19" ], "disclosure_date": "2025", "status": "disclosed", "scope": "mwc" }, "venues.mwc.2": { "value": "Aerial AI-RAN architecture", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Paper / talk", "source": [ "E19" ], "disclosure_date": "2025", "status": "disclosed", "scope": "mwc" }, "venues.mwc.3": { "value": "NVIDIA / telecom partners", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Presenters / authors", "source": [ "E19" ], "disclosure_date": "2025", "status": "disclosed", "scope": "mwc" }, "venues.mwc.4": { "value": "Grace Hopper / Blackwell / BlueField", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Product / generation", "source": [ "E19" ], "disclosure_date": "2025", "status": "disclosed", "scope": "mwc" }, "venues.mwc.5": { "value": "Deployment architecture; not GPU core disclosure", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Disclosure type", "source": [ "E19" ], "disclosure_date": "2025", "status": "disclosed", "scope": "mwc" }, "venues.mwc.6": { "value": "E19", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Source / link ID", "source": [ "E19" ], "disclosure_date": "2025", "status": "disclosed", "scope": "mwc" }, "venues.infra.0": { "value": "AI Infra Summit", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Venue", "source": [ "E11" ], "disclosure_date": "2026", "status": "disclosed", "scope": "infra" }, "venues.infra.1": { "value": "2026", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Year", "source": [ "E11" ], "disclosure_date": "2026", "status": "disclosed", "scope": "infra" }, "venues.infra.2": { "value": "Vera Rubin / DSX efficiency", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Paper / talk", "source": [ "E11" ], "disclosure_date": "2026", "status": "disclosed", "scope": "infra" }, "venues.infra.3": { "value": "NVIDIA", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Presenters / authors", "source": [ "E11" ], "disclosure_date": "2026", "status": "disclosed", "scope": "infra" }, "venues.infra.4": { "value": "Rubin", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Product / generation", "source": [ "E11" ], "disclosure_date": "2026", "status": "disclosed", "scope": "infra" }, "venues.infra.5": { "value": "System power and efficiency", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Disclosure type", "source": [ "E11" ], "disclosure_date": "2026", "status": "disclosed", "scope": "infra" }, "venues.infra.6": { "value": "E11", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Source / link ID", "source": [ "E11" ], "disclosure_date": "2026", "status": "disclosed", "scope": "infra" }, "crosswalk.maxwell.0": { "value": "Maxwell / GM200", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Architecture / silicon", "source": [ "P42" ], "disclosure_date": "2015", "status": "historical", "scope": "maxwell" }, "crosswalk.maxwell.1": { "value": "M40", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Products", "source": [ "P42" ], "disclosure_date": "2015", "status": "historical", "scope": "maxwell" }, "crosswalk.maxwell.2": { "value": "No Tensor Cores", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Important distinction", "source": [ "P42" ], "disclosure_date": "2015", "status": "historical", "scope": "maxwell" }, "crosswalk.pascal.0": { "value": "Pascal / GP100", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Architecture / silicon", "source": [ "P01", "E18" ], "disclosure_date": "2016", "status": "historical", "scope": "pascal" }, "crosswalk.pascal.1": { "value": "P100", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Products", "source": [ "P01", "E18" ], "disclosure_date": "2016", "status": "historical", "scope": "pascal" }, "crosswalk.pascal.2": { "value": "GP100 differs from P4/P40 inference dies", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Important distinction", "source": [ "P01", "E18" ], "disclosure_date": "2016", "status": "historical", "scope": "pascal" }, "crosswalk.volta.0": { "value": "Volta / GV100", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Architecture / silicon", "source": [ "P02", "P28" ], "disclosure_date": "2017", "status": "historical", "scope": "volta" }, "crosswalk.volta.1": { "value": "V100", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Products", "source": [ "P02", "P28" ], "disclosure_date": "2017", "status": "historical", "scope": "volta" }, "crosswalk.volta.2": { "value": "Turing T4 is a separate branch", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Important distinction", "source": [ "P02", "P28" ], "disclosure_date": "2017", "status": "historical", "scope": "volta" }, "crosswalk.ampere.0": { "value": "Ampere / GA100", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Architecture / silicon", "source": [ "P03" ], "disclosure_date": "2020", "status": "historical", "scope": "ampere" }, "crosswalk.ampere.1": { "value": "A100", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Products", "source": [ "P03" ], "disclosure_date": "2020", "status": "historical", "scope": "ampere" }, "crosswalk.ampere.2": { "value": "GA100 differs from graphics Ampere", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Important distinction", "source": [ "P03" ], "disclosure_date": "2020", "status": "historical", "scope": "ampere" }, "crosswalk.hopper.0": { "value": "Hopper / GH100", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Architecture / silicon", "source": [ "P04", "P08", "P14" ], "disclosure_date": "2022–2024", "status": "shipping", "scope": "hopper" }, "crosswalk.hopper.1": { "value": "H100 / H200", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Products", "source": [ "P04", "P08", "P14" ], "disclosure_date": "2022–2024", "status": "shipping", "scope": "hopper" }, "crosswalk.hopper.2": { "value": "GH200 names a Grace–Hopper combination", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Important distinction", "source": [ "P04", "P08", "P14" ], "disclosure_date": "2022–2024", "status": "shipping", "scope": "hopper" }, "crosswalk.blackwell.0": { "value": "Datacenter Blackwell", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Architecture / silicon", "source": [ "P05", "P16" ], "disclosure_date": "2024–2025", "status": "shipping", "scope": "blackwell" }, "crosswalk.blackwell.1": { "value": "B200 / GB200", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Products", "source": [ "P05", "P16" ], "disclosure_date": "2024–2025", "status": "shipping", "scope": "blackwell" }, "crosswalk.blackwell.2": { "value": "B200 GPU vs GB200 CPU–GPU construction", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Important distinction", "source": [ "P05", "P16" ], "disclosure_date": "2024–2025", "status": "shipping", "scope": "blackwell" }, "crosswalk.ultra.0": { "value": "Blackwell Ultra", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Architecture / silicon", "source": [ "P06", "P37" ], "disclosure_date": "2025", "status": "shipping", "scope": "ultra" }, "crosswalk.ultra.1": { "value": "B300 / GB300", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Products", "source": [ "P06", "P37" ], "disclosure_date": "2025", "status": "shipping", "scope": "ultra" }, "crosswalk.ultra.2": { "value": "Not the same FP64 balance as B200", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Important distinction", "source": [ "P06", "P37" ], "disclosure_date": "2025", "status": "shipping", "scope": "ultra" }, "crosswalk.rubin.0": { "value": "Rubin + Vera", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Architecture / silicon", "source": [ "P11" ], "disclosure_date": "2026", "status": "production / preview", "scope": "rubin" }, "crosswalk.rubin.1": { "value": "Vera Rubin NVL72", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Products", "source": [ "P11" ], "disclosure_date": "2026", "status": "production / preview", "scope": "rubin" }, "crosswalk.rubin.2": { "value": "Rubin GPU and Vera CPU are distinct chips", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Important distinction", "source": [ "P11" ], "disclosure_date": "2026", "status": "production / preview", "scope": "rubin" }, "crosswalk.bf4.0": { "value": "Grace-derived + ConnectX-9", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Architecture / silicon", "source": [ "P20" ], "disclosure_date": "2026", "status": "production", "scope": "bf4" }, "crosswalk.bf4.1": { "value": "BlueField-4", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Products", "source": [ "P20" ], "disclosure_date": "2026", "status": "production", "scope": "bf4" }, "crosswalk.bf4.2": { "value": "DPU CPU is not Vera", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Important distinction", "source": [ "P20" ], "disclosure_date": "2026", "status": "production", "scope": "bf4" }, "crosswalk.lpx.0": { "value": "LP30 / LPU", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Architecture / silicon", "source": [ "P12", "E06" ], "disclosure_date": "2026", "status": "production", "scope": "lpx" }, "crosswalk.lpx.1": { "value": "Groq 3 LPX", "basis": "As labelled; peak unless specified; n/d means not established by reviewed sources", "field": "Products", "source": [ "P12", "E06" ], "disclosure_date": "2026", "status": "production", "scope": "lpx" }, "crosswalk.lpx.2": { "value": "Licensed inference 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