{
  "vendor": "Meta",
  "cutoff": "2026-09-28",
  "sections": [
    {
      "id": "01",
      "title": [
        "Scope and executive synthesis",
        "范围与核心判断"
      ],
      "blocks": [
        {
          "id": "01.scope",
          "type": "prose",
          "text": [
            "This report covers Meta’s AI infrastructure from 2015 to 28 September 2026: MTIA accelerators, their integrated AI networking, system packaging and software, plus the related MSVP video-processing branch. Merchant CPUs, GPUs and switch ASICs are distinguished from Meta-designed silicon. Earlier years establish infrastructure context rather than an invented annual sequence of custom chips.",
            "本报告覆盖 Meta 在 2015 年至 2026 年 9 月 28 日的 AI 基础设施：MTIA 加速器、集成 AI 网络、系统封装与软件，以及相关 MSVP 视频处理分支。商用 CPU、GPU 和交换 ASIC 与 Meta 设计芯片分别处理。早期年份用于建立基础设施背景，不虚构逐年自研芯片序列。"
          ],
          "sources": [
            "E03",
            "E01",
            "E04"
          ]
        },
        {
          "id": "01.thesis",
          "type": "prose",
          "text": [
            "MTIA evolves from low-power recommendation inference into an HBM-based training platform and then an inference-oriented generative-AI roadmap. The decisive transition is not merely more arithmetic: it adds network chiplets, near-memory reduction and rack-scale communication while preserving a PyTorch-facing software contract. Meta’s workload ownership allows narrower optimization than a merchant GPU, but portability, reliability and model evolution remain constraints.",
            "MTIA 从低功耗推荐推理，演进到基于 HBM 的训练平台，再延伸至面向生成式 AI 推理的路线图。决定性转变不只是增加算术能力，还增加网络小芯片、近存归约与机架级通信，同时保持面向 PyTorch 的软件契约。Meta 掌握自身负载，可以比通用商用 GPU 更有针对性地优化，但可移植性、可靠性与模型变化仍是约束。"
          ],
          "sources": [
            "P03",
            "P04",
            "C01",
            "E01"
          ]
        }
      ]
    },
    {
      "id": "02",
      "title": [
        "MTIA100 and MTIA200: recommendation inference",
        "MTIA100 与 MTIA200：推荐推理"
      ],
      "blocks": [
        {
          "id": "02.g1",
          "type": "prose",
          "text": [
            "MTIA100, originally MTIA v1, was designed around recommendation inference and disclosed at ISCA 2023. Its 7 nm implementation combines an 8×8 processing-element grid, local memories and a larger shared SRAM tier with LPDDR5. The key architectural balance is enough arithmetic for dense portions of the model without sacrificing the storage and access behavior needed by sparse features. This is a different objective from maximizing large-batch transformer training FLOPS.",
            "MTIA100 原名 MTIA v1，围绕推荐推理设计，于 ISCA 2023 披露。其 7 nm 实现结合 8×8 处理单元阵列、本地存储、较大共享 SRAM 层及 LPDDR5。核心平衡是为模型的稠密部分提供足够算术能力，同时保留稀疏特征需要的存储与访问能力。这与最大化大批量 Transformer 训练 FLOPS 的目标不同。"
          ],
          "sources": [
            "P03",
            "C02"
          ]
        },
        {
          "id": "02.g2",
          "type": "prose",
          "text": [
            "MTIA200, originally MTIA2i, retains the 64-PE organization while moving to 5 nm, higher frequency, more local storage and 256 MB shared SRAM. Dense FP16/BF16 rises from 51.2 to 177 TFLOP/s, while LPDDR5 bandwidth increases only from 176 to 204.8 GB/s. The design therefore relies increasingly on on-chip reuse and sparse-workload scheduling. The 2024 platform fits 72 accelerators in a rack, but this is not the same as the 72-device dedicated scale-up domain introduced with MTIA400.",
            "MTIA200 原名 MTIA2i，保留 64 个处理单元的组织，转向 5 nm、更高频率、更大本地存储及 256 MB 共享 SRAM。稠密 FP16／BF16 从 51.2 提高到 177 TFLOP/s，而 LPDDR5 带宽仅从 176 提高到 204.8 GB/s。因此设计更依赖片上复用与稀疏负载调度。2024 年平台可在机架中容纳 72 个加速器，但这不同于 MTIA400 引入的 72 设备专用纵向扩展域。"
          ],
          "sources": [
            "P04",
            "C03"
          ]
        }
      ]
    },
    {
      "id": "03",
      "title": [
        "MTIA300: training changes the data path",
        "MTIA300：训练改变数据路径"
      ],
      "blocks": [
        {
          "id": "03.chip",
          "type": "prose",
          "text": [
            "The ISCA 2026 paper describes one compute chiplet, two network chiplets and six HBM3e stacks. A 12×6 active PE array combines RISC-V vector control, dot-product, special-function, reduction and DMA engines. The memory system provides 216 GB and 6.1 TB/s. Redundant PE resources address yield and faults. Moving from LPDDR to HBM changes both packaging and the balance between dense layers, embeddings and collective traffic.",
            "ISCA 2026 论文描述一个计算小芯片、两个网络小芯片及六堆栈 HBM3e。12×6 启用处理单元阵列结合 RISC-V 向量控制、点积、特殊函数、归约与 DMA 引擎。存储系统提供 216 GB 和 6.1 TB/s，冗余处理单元用于良率与故障处理。从 LPDDR 转向 HBM，同时改变封装以及稠密层、嵌入表与集合通信之间的平衡。"
          ],
          "sources": [
            "C01"
          ]
        },
        {
          "id": "03.network",
          "type": "prose",
          "text": [
            "Each network chiplet integrates six 800 Gb/s RDMA controllers. The aggregate endpoint rate is 1.2 TB/s in each direction. Message engines and near-memory reduction let collectives progress without occupying the principal compute engines or passing the payload through the host PCIe link. The paper’s deployed scale-up configuration uses 800 GB/s, with support up to 1,000 GB/s; scale-out is 200 GB/s. The marketing table uses the supported maximum. Both configurations are retained rather than silently merged.",
            "每个网络小芯片集成六个 800 Gb/s RDMA 控制器，总端点速率为每方向 1.2 TB/s。消息引擎与近存归约使集合通信无需占用主要计算引擎，也不必把载荷送过主机 PCIe 链路。论文部署配置采用 800 GB/s 纵向带宽，支持最高 1,000 GB/s；横向扩展为 200 GB/s。产品表采用支持上限，因此本报告保留两种配置，不将其静默合并。"
          ],
          "sources": [
            "C01",
            "P01",
            "E01"
          ]
        },
        {
          "id": "03.host",
          "type": "prose",
          "text": [
            "A one-to-one host-CPU/accelerator relationship supports optimizer offload. Large HBM capacity can permit larger local batches and fewer communicating trainers, but the benefit depends on optimizer state, precision and convergence constraints. HCCL can fuse communication and computation; the reported collective results are workload- and topology-specific. Integrated NICs reduce one bottleneck, not every synchronization or network bottleneck.",
            "一对一主机 CPU／加速器关系支持优化器卸载。更大 HBM 容量可能允许更大本地批量并减少参与通信的训练设备，但收益取决于优化器状态、精度及收敛约束。HCCL 可融合通信与计算，公布的集合通信结果依赖具体负载与拓扑。集成 NIC 减少一种瓶颈，不会消除所有同步或网络瓶颈。"
          ],
          "sources": [
            "C01",
            "C04"
          ]
        }
      ]
    },
    {
      "id": "04",
      "title": [
        "MTIA400, 450 and 500: the inference roadmap",
        "MTIA400、450 与 500：推理路线图"
      ],
      "blocks": [
        {
          "id": "04.road",
          "type": "prose",
          "text": [
            "The March 2026 roadmap identifies MTIA300 as in production, MTIA400 as laboratory-tested and moving toward deployment, and MTIA450/500 as planned for 2027. MTIA400 uses two compute chiplets and a 72-device scale-up system. MTIA450 prioritizes memory bandwidth and low-precision inference. MTIA500 moves to four compute chiplets plus separate network and host-I/O functions. These are disclosure statuses, not assumed public-cloud or merchant availability.",
            "2026 年 3 月路线图将 MTIA300 列为已生产部署，MTIA400 列为已完成实验室测试、正在推进部署，MTIA450／500 列为计划于 2027 年部署。MTIA400 使用两个计算小芯片及 72 设备纵向扩展系统；MTIA450 优先提升内存带宽和低精度推理；MTIA500 转向四个计算小芯片，并分离网络与主机 I/O 功能。以上是披露状态，不推定公共云或商用芯片可获取性。"
          ],
          "sources": [
            "E01"
          ]
        },
        {
          "id": "04.mechanism",
          "type": "prose",
          "text": [
            "Architectural interpretation: reusing chassis and network infrastructure can shorten deployment cycles, but it fixes parts of the system bandwidth budget while compute and HBM continue to grow. From 400 to 500, scale-up remains 1.2 TB/s and scale-out 100 GB/s per device, while HBM bandwidth triples. The compiler must consequently preserve more locality or change parallelization. A 25× comparison from MTIA300 MX8 to MTIA500 MX4 crosses numerical formats and is not a like-for-like arithmetic speedup.",
            "架构解读：复用机箱与网络基础设施可以缩短部署周期，但当算力和 HBM 持续增长时，部分系统带宽预算被固定。从 400 到 500，每设备纵向扩展仍为 1.2 TB/s、横向扩展仍为 100 GB/s，而 HBM 带宽增加至三倍。因此编译器必须保留更多局部性或改变并行方式。MTIA300 MX8 至 MTIA500 MX4 的 25 倍比较跨越数值格式，不是同口径算术加速比。"
          ],
          "sources": [
            "E01"
          ]
        }
      ]
    },
    {
      "id": "05",
      "title": [
        "Generation specifications and disclosure reconciliation",
        "代际规格与披露差异"
      ],
      "blocks": [
        {
          "id": "gpu",
          "type": "table",
          "table": "gpu"
        },
        {
          "id": "05.reconcile",
          "type": "prose",
          "text": [
            "The March roadmap lists MTIA300 at 0.6 PFLOP/s BF16, 1.2 PFLOP/s FP8/MX8 and 800 W module TDP. The ISCA paper lists 560/1,120 TFLOP/s and 912 W TDP with 667 W typical power. These represent different published configurations or measurement bases; no undocumented reconciliation is imposed. For derived ratios, the paper’s matched values are used. Likewise, MTIA200’s launch states 90 W while the later comparison table states 85 W. Sparse peaks are kept separate from dense values.",
            "3 月路线图将 MTIA300 列为 BF16 0.6 PFLOP/s、FP8／MX8 1.2 PFLOP/s、模块 TDP 800 W；ISCA 论文则列出 560／1,120 TFLOP/s、TDP 912 W、典型功耗 667 W。它们代表不同公开配置或测量口径，不强行作无依据统一。推导指标使用论文中相匹配的数值。同样，MTIA200 发布时写 90 W，后续比较表写 85 W。稀疏峰值与稠密数值分别处理。"
          ],
          "sources": [
            "E01",
            "C01",
            "P04"
          ]
        },
        {
          "id": "cpu",
          "type": "table",
          "table": "cpu"
        }
      ]
    },
    {
      "id": "06",
      "title": [
        "Integrated NICs, networking and MSVP",
        "集成 NIC、网络与 MSVP"
      ],
      "blocks": [
        {
          "id": "nic",
          "type": "table",
          "table": "nic"
        },
        {
          "id": "06.video",
          "type": "prose",
          "text": [
            "MSVP is a dedicated video-transcoding ASIC disclosed in 2023. It belongs in the infrastructure portfolio because video processing consumes substantial fleet resources, but it is not an MTIA generation or a general neural-network accelerator. Likewise, Meta’s OCP server and networking designs, including switch software and rack standards, should not be confused with ownership of every merchant ASIC they contain.",
            "MSVP 是 2023 年披露的专用视频转码 ASIC。视频处理消耗大量集群资源，因此应纳入基础设施组合，但它不是 MTIA 的一代，也不是通用神经网络加速器。同样，Meta 的 OCP 服务器及网络设计，包括交换软件与机架标准，不等于 Meta 自研其中全部商用 ASIC。"
          ],
          "sources": [
            "E04",
            "E03"
          ]
        },
        {
          "id": "links",
          "type": "table",
          "table": "links"
        }
      ]
    },
    {
      "id": "07",
      "title": [
        "Rack architecture and software",
        "机架架构与软件"
      ],
      "blocks": [
        {
          "id": "early",
          "type": "figure",
          "figure": "early"
        },
        {
          "id": "late",
          "type": "figure",
          "figure": "late"
        },
        {
          "id": "system",
          "type": "table",
          "table": "system"
        },
        {
          "id": "software",
          "type": "table",
          "table": "software"
        }
      ]
    },
    {
      "id": "08",
      "title": [
        "Normalized trends and engineering tradeoffs",
        "归一化趋势与工程取舍"
      ],
      "blocks": [
        {
          "id": "ratios",
          "type": "table",
          "table": "ratios"
        },
        {
          "id": "08.trade",
          "type": "prose",
          "text": [
            "The large increase in bytes per BF16 FLOP at MTIA300 reflects a workload choice: recommendation training needs embedding capacity and traffic handling. Subsequent inference products raise both HBM and low-precision compute but retain a fixed rack network budget. Their success depends on model placement, expert routing, KV-cache behavior and compiler utilization. Compare at matched precision, quality, batch size and service-level latency, with module and rack power kept separate.",
            "MTIA300 每 BF16 FLOP 对应字节的大幅提高，反映负载选择：推荐训练需要嵌入表容量与流量处理能力。后续推理产品同时提高 HBM 与低精度算力，但保持固定机架网络预算。其成功取决于模型放置、专家路由、KV 缓存行为及编译器利用率。比较时应匹配精度、质量、批量及服务延迟，并区分模块和机架功耗。"
          ],
          "sources": [
            "C01",
            "E01"
          ]
        }
      ]
    },
    {
      "id": "09",
      "title": [
        "Conference and product crosswalk",
        "会议与产品对照"
      ],
      "blocks": [
        {
          "id": "conference",
          "type": "table",
          "table": "conference"
        },
        {
          "id": "09.gaps",
          "type": "prose",
          "text": [
            "No product-specific ISSCC, HPCA, MICRO or ASPLOS circuit/architecture chain is established here for MTIA. ISCA provides the strongest direct product evidence. The public roadmap is broader than the available implementation papers: process, die details and dense/sparse arithmetic basis remain incomplete for 400/450/500. The report retains those gaps in the tables rather than extrapolating earlier silicon details.",
            "本版未建立 MTIA 对应的产品级 ISSCC、HPCA、MICRO 或 ASPLOS 电路／架构论文链。ISCA 提供最强的直接产品证据。公开路线图比可获取实现论文更广：400／450／500 的工艺、裸片细节与稠密／稀疏算术口径仍不完整。表中保留这些缺口，不从早期芯片外推。"
          ],
          "sources": [
            "C01",
            "C02",
            "C03",
            "E01"
          ]
        },
        {
          "id": "cross",
          "type": "table",
          "table": "cross"
        },
        {
          "id": "isscc_context",
          "type": "table",
          "table": "isscc_context"
        }
      ]
    }
  ],
  "tables": {
    "gpu": {
      "id": "gpu",
      "title": [
        "MTIA reference specifications",
        "MTIA 参考规格"
      ],
      "headers": [
        [
          "Product",
          "产品"
        ],
        [
          "Architecture",
          "架构"
        ],
        [
          "GA / milestone",
          "商用／里程碑"
        ],
        [
          "Status",
          "状态"
        ],
        [
          "Process",
          "工艺"
        ],
        [
          "Dies / packaging",
          "裸片／封装"
        ],
        [
          "Compute units",
          "计算单元"
        ],
        [
          "Dense BF16",
          "稠密 BF16"
        ],
        [
          "Dense FP8",
          "稠密 FP8"
        ],
        [
          "Dense FP6 / FP4",
          "稠密 FP6／FP4"
        ],
        [
          "FP64 vector / matrix",
          "FP64 向量／矩阵"
        ],
        [
          "Memory: type; stacks; GB; TB/s",
          "内存：类型；堆栈；GB；TB/s"
        ],
        [
          "LLC / SRAM",
          "末级缓存／SRAM"
        ],
        [
          "Scale-up: links; GB/s per direction; domain",
          "纵向扩展：链路；单向 GB/s；域"
        ],
        [
          "Host link",
          "主机连接"
        ],
        [
          "Power / cooling",
          "功耗／散热"
        ],
        [
          "Form factor",
          "形态"
        ]
      ],
      "rows": [
        {
          "id": "100",
          "values": [
            [
              "MTIA100 / v1",
              "MTIA100 / v1"
            ],
            [
              "Recommendation inference",
              "Recommendation inference"
            ],
            [
              "2023 disclosure",
              "2023 disclosure"
            ],
            [
              "Historical shipping",
              "历史已商用"
            ],
            [
              "7 nm",
              "7 nm"
            ],
            [
              "1 logic die",
              "1 logic die"
            ],
            [
              "64 PEs",
              "64 PEs"
            ],
            [
              "51.2 TFLOP/s",
              "51.2 TFLOP/s"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "LPDDR5; 64 GB; 0.176 TB/s",
              "LPDDR5; 64 GB; 0.176 TB/s"
            ],
            [
              "128 MB; 128 KB/PE",
              "128 MB; 128 KB/PE"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "PCIe4 ×8",
              "PCIe4 ×8"
            ],
            [
              "25 W",
              "25 W"
            ],
            [
              "Accelerator board",
              "加速板卡"
            ]
          ],
          "sources": [
            "P03",
            "P04"
          ]
        },
        {
          "id": "200",
          "values": [
            [
              "MTIA200 / 2i",
              "MTIA200 / 2i"
            ],
            [
              "Recommendation inference",
              "Recommendation inference"
            ],
            [
              "2024 deployment",
              "2024 deployment"
            ],
            [
              "Shipping / available",
              "已商用／可获取"
            ],
            [
              "5 nm",
              "5 nm"
            ],
            [
              "1 logic die",
              "1 logic die"
            ],
            [
              "64 PEs",
              "64 PEs"
            ],
            [
              "177 TFLOP/s",
              "177 TFLOP/s"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "LPDDR5; 64-128 GB; 0.2048 TB/s",
              "LPDDR5; 64-128 GB; 0.2048 TB/s"
            ],
            [
              "256 MB; 384 KB/PE",
              "256 MB; 384 KB/PE"
            ],
            [
              "PCIe fabric; not dedicated scale-up",
              "PCIe fabric; not dedicated scale-up"
            ],
            [
              "PCIe5 ×8",
              "PCIe5 ×8"
            ],
            [
              "90 W launch; 85 W paper",
              "90 W launch; 85 W paper"
            ],
            [
              "Accelerator board",
              "加速板卡"
            ]
          ],
          "sources": [
            "P04",
            "C01"
          ]
        },
        {
          "id": "300",
          "values": [
            [
              "MTIA300",
              "MTIA300"
            ],
            [
              "R&R training",
              "R&R training"
            ],
            [
              "2026 production",
              "2026 production"
            ],
            [
              "Shipping / available",
              "已商用／可获取"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "1 compute + 2 network; interposer",
              "1 compute + 2 network; interposer"
            ],
            [
              "72 active PEs",
              "72 active PEs"
            ],
            [
              "560 TFLOP/s (paper)",
              "560 TFLOP/s (paper)"
            ],
            [
              "1120 TFLOP/s (paper)",
              "1120 TFLOP/s (paper)"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "HBM3e; 6; 216 GB; 6.1 TB/s",
              "HBM3e; 6; 216 GB; 6.1 TB/s"
            ],
            [
              "192 MB; 512 KB/PE",
              "192 MB; 512 KB/PE"
            ],
            [
              "800-1000 GB/s one-way; 16 devices",
              "800-1000 GB/s one-way; 16 devices"
            ],
            [
              "PCIe5 ×16",
              "PCIe5 ×16"
            ],
            [
              "912 W TDP / 667 W typical (paper)",
              "912 W TDP / 667 W typical (paper)"
            ],
            [
              "Liquid-cooled module",
              "液冷模块"
            ]
          ],
          "sources": [
            "C01"
          ]
        },
        {
          "id": "400",
          "values": [
            [
              "MTIA400",
              "MTIA400"
            ],
            [
              "GenAI / inference",
              "生成式 AI／推理"
            ],
            [
              "2026 deployment path",
              "2026 deployment path"
            ],
            [
              "Announced; GA n/d",
              "已公布；GA n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "2 compute chiplets",
              "2 compute chiplets"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "3 PFLOP/s advertised; dense basis n/d",
              "3 PFLOP/s advertised; dense basis n/d"
            ],
            [
              "6 PFLOP/s FP8/MX8; dense basis n/d",
              "6 PFLOP/s FP8/MX8; dense basis n/d"
            ],
            [
              "12 PFLOP/s MX4; dense basis n/d",
              "12 PFLOP/s MX4; dense basis n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "HBM; stacks n/d; 288 GB; 9.2 TB/s",
              "HBM; stacks n/d; 288 GB; 9.2 TB/s"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "1200 GB/s one-way; 72 devices",
              "1200 GB/s one-way; 72 devices"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "1200 W module; liquid/AALC",
              "1200 W module; liquid/AALC"
            ],
            [
              "Rack module",
              "机架模块"
            ]
          ],
          "sources": [
            "E01"
          ]
        },
        {
          "id": "450",
          "values": [
            [
              "MTIA450",
              "MTIA450"
            ],
            [
              "GenAI / inference",
              "生成式 AI／推理"
            ],
            [
              "early 2027 target",
              "early 2027 target"
            ],
            [
              "Roadmap",
              "路线图"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "3.5 PFLOP/s advertised; dense basis n/d",
              "3.5 PFLOP/s advertised; dense basis n/d"
            ],
            [
              "7 PFLOP/s FP8/MX8; dense basis n/d",
              "7 PFLOP/s FP8/MX8; dense basis n/d"
            ],
            [
              "21 PFLOP/s MX4; dense basis n/d",
              "21 PFLOP/s MX4; dense basis n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "HBM; stacks n/d; 288 GB; 18.4 TB/s",
              "HBM; stacks n/d; 288 GB; 18.4 TB/s"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "1200 GB/s one-way; 72 devices",
              "1200 GB/s one-way; 72 devices"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "1400 W module; liquid/AALC",
              "1400 W module; liquid/AALC"
            ],
            [
              "Rack module",
              "机架模块"
            ]
          ],
          "sources": [
            "E01"
          ]
        },
        {
          "id": "500",
          "values": [
            [
              "MTIA500",
              "MTIA500"
            ],
            [
              "GenAI / inference",
              "生成式 AI／推理"
            ],
            [
              "2027 target",
              "2027 target"
            ],
            [
              "Roadmap",
              "路线图"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "4 compute + 2 network + SoC",
              "4 compute + 2 network + SoC"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "5 PFLOP/s advertised; dense basis n/d",
              "5 PFLOP/s advertised; dense basis n/d"
            ],
            [
              "10 PFLOP/s FP8/MX8; dense basis n/d",
              "10 PFLOP/s FP8/MX8; dense basis n/d"
            ],
            [
              "30 PFLOP/s MX4; dense basis n/d",
              "30 PFLOP/s MX4; dense basis n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "HBM; stacks n/d; 384-512 GB; 27.6 TB/s",
              "HBM; stacks n/d; 384-512 GB; 27.6 TB/s"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "1200 GB/s one-way; 72 devices",
              "1200 GB/s one-way; 72 devices"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "1700 W module; liquid/AALC",
              "1700 W module; liquid/AALC"
            ],
            [
              "Rack module",
              "机架模块"
            ]
          ],
          "sources": [
            "E01"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3,
          4,
          5
        ],
        [
          0,
          6,
          7,
          8,
          9,
          10
        ],
        [
          0,
          11,
          12
        ],
        [
          0,
          13,
          14,
          15,
          16
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "cpu": {
      "id": "cpu",
      "title": [
        "Host CPU boundary",
        "主机 CPU 边界"
      ],
      "headers": [
        [
          "Generation / reference SKU",
          "代际／参考 SKU"
        ],
        [
          "Codename",
          "代号"
        ],
        [
          "GA",
          "正式商用"
        ],
        [
          "Status",
          "状态"
        ],
        [
          "Core µarch",
          "核心微架构"
        ],
        [
          "Cores / threads",
          "核心／线程"
        ],
        [
          "Process per die",
          "各裸片工艺"
        ],
        [
          "Dies / packaging",
          "裸片／封装"
        ],
        [
          "L2 per core",
          "每核 L2"
        ],
        [
          "L3 / domain",
          "L3／共享域"
        ],
        [
          "Memory: channels; rate; GB/s",
          "内存：通道；速率；GB/s"
        ],
        [
          "Sockets / links",
          "插槽／互联"
        ],
        [
          "PCIe / CXL",
          "PCIe／CXL"
        ],
        [
          "TDP",
          "TDP"
        ],
        [
          "Vector / matrix ISA",
          "向量／矩阵 ISA"
        ]
      ],
      "rows": [
        {
          "id": "host",
          "values": [
            [
              "External host CPUs",
              "外部主机 CPU"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "Supplier products",
              "供应商产品"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ]
          ],
          "sources": [
            "C01",
            "E03"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3,
          4,
          5
        ],
        [
          0,
          6,
          7,
          8,
          9
        ],
        [
          0,
          10,
          11,
          12,
          13,
          14
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "nic": {
      "id": "nic",
      "title": [
        "MTIA network chiplets",
        "MTIA 网络小芯片"
      ],
      "headers": [
        [
          "Product",
          "产品"
        ],
        [
          "GA / milestone",
          "商用／里程碑"
        ],
        [
          "Status",
          "状态"
        ],
        [
          "Class",
          "类别"
        ],
        [
          "Ports × speed",
          "端口×速率"
        ],
        [
          "SerDes",
          "SerDes"
        ],
        [
          "Host interface",
          "主机接口"
        ],
        [
          "Programmable engine",
          "可编程引擎"
        ],
        [
          "Embedded CPU",
          "嵌入式 CPU"
        ],
        [
          "On-card memory",
          "板载内存"
        ],
        [
          "Transport / RDMA",
          "传输／RDMA"
        ],
        [
          "Congestion control",
          "拥塞控制"
        ],
        [
          "Key offloads",
          "主要卸载"
        ],
        [
          "Power",
          "功耗"
        ]
      ],
      "rows": [
        {
          "id": "n",
          "values": [
            [
              "MTIA300 network chiplets",
              "MTIA300 network chiplets"
            ],
            [
              "2026",
              "2026"
            ],
            [
              "Shipping / available",
              "已商用／可获取"
            ],
            [
              "Integrated AI NIC",
              "Integrated AI NIC"
            ],
            [
              "2×6×800 Gb/s",
              "2×6×800 Gb/s"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Die-to-die",
              "Die-to-die"
            ],
            [
              "Message engines / near-memory reduction",
              "Message engines / near-memory reduction"
            ],
            [
              "RISC-V control",
              "RISC-V control"
            ],
            [
              "Shared accelerator memory",
              "Shared accelerator memory"
            ],
            [
              "RDMA",
              "RDMA"
            ],
            [
              "Credit-based fabric mechanisms",
              "Credit-based fabric mechanisms"
            ],
            [
              "Collectives; reductions; direct data path",
              "Collectives; reductions; direct data path"
            ],
            [
              "Within module",
              "Within module"
            ]
          ],
          "sources": [
            "C01",
            "P01"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3
        ],
        [
          0,
          4,
          5,
          6,
          7
        ],
        [
          0,
          8,
          9,
          10,
          11
        ],
        [
          0,
          12,
          13
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "links": {
      "id": "links",
      "title": [
        "Interconnect evolution",
        "互联演进"
      ],
      "headers": [
        [
          "Interconnect",
          "互联"
        ],
        [
          "Year / generation",
          "年份／代际"
        ],
        [
          "Lane rate",
          "通道速率"
        ],
        [
          "Lanes / link",
          "每链路通道"
        ],
        [
          "GB/s per link per direction",
          "每链路单向 GB/s"
        ],
        [
          "Links / device",
          "每设备链路"
        ],
        [
          "Topology",
          "拓扑"
        ],
        [
          "Domain limit",
          "域规模"
        ],
        [
          "Coherence / semantics",
          "一致性／语义"
        ]
      ],
      "rows": [
        {
          "id": "a",
          "values": [
            [
              "MTIA200 host fabric",
              "MTIA200 host fabric"
            ],
            [
              "2024",
              "2024"
            ],
            [
              "PCIe5 32 GT/s",
              "PCIe5 32 GT/s"
            ],
            [
              "8",
              "8"
            ],
            [
              "~31.5 before packet overhead",
              "~31.5 before packet overhead"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "PCIe switching",
              "PCIe switching"
            ],
            [
              "72/rack is packaging count",
              "72/rack is packaging count"
            ],
            [
              "PCIe",
              "PCIe"
            ]
          ],
          "sources": [
            "P04"
          ]
        },
        {
          "id": "b",
          "values": [
            [
              "MTIA300 scale-up",
              "MTIA300 scale-up"
            ],
            [
              "2026",
              "2026"
            ],
            [
              "800 Gb/s port",
              "800 Gb/s port"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "100",
              "100"
            ],
            [
              "Configuration-specific",
              "Configuration-specific"
            ],
            [
              "Rack fabric",
              "Rack fabric"
            ],
            [
              "16",
              "16"
            ],
            [
              "RDMA; explicit collectives",
              "RDMA; explicit collectives"
            ]
          ],
          "sources": [
            "C01"
          ]
        },
        {
          "id": "c",
          "values": [
            [
              "MTIA400/450/500 scale-up",
              "MTIA400/450/500 scale-up"
            ],
            [
              "2026 roadmap",
              "2026 roadmap"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "1200 aggregate/device",
              "1200 aggregate/device"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Switched backplane",
              "Switched backplane"
            ],
            [
              "72",
              "72"
            ],
            [
              "Explicit communication",
              "Explicit communication"
            ]
          ],
          "sources": [
            "E01"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3,
          4
        ],
        [
          0,
          5,
          6,
          7,
          8
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "system": {
      "id": "system",
      "title": [
        "System generations",
        "系统代际"
      ],
      "headers": [
        [
          "Platform",
          "平台"
        ],
        [
          "Year / milestone",
          "年份／里程碑"
        ],
        [
          "CPU / accelerator count",
          "CPU／加速器数量"
        ],
        [
          "Scale-up domain",
          "纵向扩展域"
        ],
        [
          "Scale-out per accelerator",
          "每加速器横向带宽"
        ],
        [
          "Rack power",
          "机架功耗"
        ],
        [
          "Cooling",
          "散热"
        ]
      ],
      "rows": [
        {
          "id": "a",
          "values": [
            [
              "MTIA200 rack",
              "MTIA200 rack"
            ],
            [
              "2024",
              "2024"
            ],
            [
              "72 accelerators; 3 chassis",
              "72 accelerators; 3 chassis"
            ],
            [
              "PCIe topology",
              "PCIe topology"
            ],
            [
              "Optional external RDMA NIC",
              "Optional external RDMA NIC"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Air",
              "Air"
            ]
          ],
          "sources": [
            "P04"
          ]
        },
        {
          "id": "b",
          "values": [
            [
              "MTIA300 rack",
              "MTIA300 rack"
            ],
            [
              "2026",
              "2026"
            ],
            [
              "16 accelerators; 1 CPU/accelerator",
              "16 accelerators; 1 CPU/accelerator"
            ],
            [
              "16",
              "16"
            ],
            [
              "200 GB/s nominal one-way",
              "200 GB/s nominal one-way"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Liquid",
              "Liquid"
            ]
          ],
          "sources": [
            "C01"
          ]
        },
        {
          "id": "c",
          "values": [
            [
              "MTIA400/450/500 rack",
              "MTIA400/450/500 rack"
            ],
            [
              "2026-2027 targets",
              "2026-2027 targets"
            ],
            [
              "72 accelerators",
              "72 accelerators"
            ],
            [
              "72",
              "72"
            ],
            [
              "100 GB/s nominal one-way",
              "100 GB/s nominal one-way"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "AALC / facility liquid",
              "AALC / facility liquid"
            ]
          ],
          "sources": [
            "E01"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3
        ],
        [
          0,
          4,
          5,
          6
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "software": {
      "id": "software",
      "title": [
        "Software stack",
        "软件栈"
      ],
      "headers": [
        [
          "Layer",
          "层"
        ],
        [
          "Component",
          "组件"
        ],
        [
          "Function",
          "功能"
        ],
        [
          "Architectural implication",
          "架构含义"
        ]
      ],
      "rows": [
        {
          "id": "a",
          "values": [
            [
              "Frontend",
              "前端"
            ],
            [
              "PyTorch / torch.compile / export",
              "PyTorch / torch.compile / export"
            ],
            [
              "Model capture",
              "模型捕获"
            ],
            [
              "Shared framework interface",
              "共享框架接口"
            ]
          ],
          "sources": [
            "E01",
            "P04"
          ]
        },
        {
          "id": "b",
          "values": [
            [
              "Compiler",
              "编译器"
            ],
            [
              "TorchInductor / Triton / MLIR / LLVM",
              "TorchInductor / Triton / MLIR / LLVM"
            ],
            [
              "Graph and kernel lowering",
              "图与算子编译"
            ],
            [
              "Schedule local memories and engines",
              "调度本地存储与引擎"
            ]
          ],
          "sources": [
            "E01"
          ]
        },
        {
          "id": "c",
          "values": [
            [
              "Communication",
              "通信"
            ],
            [
              "Hoot Collective Communications Library",
              "Hoot Collective Communications Library"
            ],
            [
              "Collectives and reduction offload",
              "集合通信与归约卸载"
            ],
            [
              "HCCL here is Meta Hoot",
              "本文 HCCL 为 Meta Hoot"
            ]
          ],
          "sources": [
            "C04",
            "P01"
          ]
        },
        {
          "id": "d",
          "values": [
            [
              "Runtime",
              "运行时"
            ],
            [
              "Rust user-space driver / firmware",
              "Rust user-space driver / firmware"
            ],
            [
              "Memory, execution, observability",
              "存储、执行、可观测性"
            ],
            [
              "Host and device coordination",
              "主机与设备协同"
            ]
          ],
          "sources": [
            "E01"
          ]
        },
        {
          "id": "e",
          "values": [
            [
              "Serving",
              "服务"
            ],
            [
              "vLLM plugin",
              "vLLM plugin"
            ],
            [
              "Serving integration",
              "推理服务集成"
            ],
            [
              "Backend-specific optimized kernels",
              "后端专用优化算子"
            ]
          ],
          "sources": [
            "E01"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "ratios": {
      "id": "ratios",
      "title": [
        "Memory and communication balance",
        "存储与通信平衡"
      ],
      "headers": [
        [
          "Product / metric",
          "产品／指标"
        ],
        [
          "Calculation",
          "计算"
        ],
        [
          "Interpretation",
          "解读"
        ]
      ],
      "rows": [
        {
          "id": "a",
          "values": [
            [
              "MTIA100 DRAM/BF16",
              "MTIA100 DRAM/BF16"
            ],
            [
              "176e9/51.2e12 = 0.00344 B/FLOP",
              "176e9/51.2e12 = 0.00344 B/FLOP"
            ],
            [
              "Dense peak",
              "稠密峰值"
            ]
          ],
          "sources": [
            "P04"
          ]
        },
        {
          "id": "b",
          "values": [
            [
              "MTIA200 DRAM/BF16",
              "MTIA200 DRAM/BF16"
            ],
            [
              "204.8e9/177e12 = 0.00116 B/FLOP",
              "204.8e9/177e12 = 0.00116 B/FLOP"
            ],
            [
              "More reuse required than MTIA100",
              "比 MTIA100 更需要复用"
            ]
          ],
          "sources": [
            "P04"
          ]
        },
        {
          "id": "c",
          "values": [
            [
              "MTIA300 HBM/BF16",
              "MTIA300 HBM/BF16"
            ],
            [
              "6.1e12/560e12 = 0.0109 B/FLOP",
              "6.1e12/560e12 = 0.0109 B/FLOP"
            ],
            [
              "Paper configuration",
              "论文配置"
            ]
          ],
          "sources": [
            "C01"
          ]
        },
        {
          "id": "d",
          "values": [
            [
              "MTIA300 capacity/BF16",
              "MTIA300 capacity/BF16"
            ],
            [
              "216e9/560e12 = 3.86e-4 B·s/FLOP",
              "216e9/560e12 = 3.86e-4 B·s/FLOP"
            ],
            [
              "Per accelerator",
              "每加速器"
            ]
          ],
          "sources": [
            "C01"
          ]
        },
        {
          "id": "e",
          "values": [
            [
              "MTIA300 scale-up/HBM",
              "MTIA300 scale-up/HBM"
            ],
            [
              "0.8/6.1 = 0.131",
              "0.8/6.1 = 0.131"
            ],
            [
              "Deployed paper configuration",
              "论文部署配置"
            ]
          ],
          "sources": [
            "C01"
          ]
        },
        {
          "id": "f",
          "values": [
            [
              "MTIA400→500 scale-up/HBM",
              "MTIA400→500 scale-up/HBM"
            ],
            [
              "1.2/9.2=0.130 → 1.2/27.6=0.0435",
              "1.2/9.2=0.130 → 1.2/27.6=0.0435"
            ],
            [
              "Network grows slower than HBM",
              "网络增长慢于 HBM"
            ]
          ],
          "sources": [
            "E01"
          ]
        },
        {
          "id": "g",
          "values": [
            [
              "MTIA300 BF16/TDP",
              "MTIA300 BF16/TDP"
            ],
            [
              "560/912 = 0.614 TFLOP/s/W",
              "560/912 = 0.614 TFLOP/s/W"
            ],
            [
              "Peak/TDP; not application efficiency",
              "峰值／TDP；非应用效率"
            ]
          ],
          "sources": [
            "C01"
          ]
        },
        {
          "id": "h",
          "values": [
            [
              "Host DDR/core and L3/core",
              "主机 DDR／核与 L3／核"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "No Meta host-CPU SKU asserted",
              "不声称 Meta 主机 CPU SKU"
            ]
          ],
          "sources": [
            "C01"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "conference": {
      "id": "conference",
      "title": [
        "Disclosure map",
        "披露映射"
      ],
      "headers": [
        [
          "Venue",
          "会议／活动"
        ],
        [
          "Year",
          "年份"
        ],
        [
          "Paper / talk / disclosure",
          "论文／演讲／披露"
        ],
        [
          "Presenter / authors",
          "报告人／作者"
        ],
        [
          "Product",
          "产品"
        ],
        [
          "Evidence type",
          "证据类型"
        ],
        [
          "Source",
          "来源"
        ]
      ],
      "rows": [
        {
          "id": "a",
          "values": [
            [
              "ISCA",
              "ISCA"
            ],
            [
              "2023",
              "2023"
            ],
            [
              "MTIA v1",
              "MTIA v1"
            ],
            [
              "Meta authors",
              "Meta authors"
            ],
            [
              "MTIA100",
              "MTIA100"
            ],
            [
              "Architecture paper; official companion",
              "架构论文；官方配套材料"
            ],
            [
              "C02 P03",
              "C02 P03"
            ]
          ],
          "sources": [
            "C02",
            "P03"
          ]
        },
        {
          "id": "b",
          "values": [
            [
              "ISCA",
              "ISCA"
            ],
            [
              "2025",
              "2025"
            ],
            [
              "Second-generation MTIA",
              "Second-generation MTIA"
            ],
            [
              "Meta authors",
              "Meta authors"
            ],
            [
              "MTIA200 / 2i",
              "MTIA200 / 2i"
            ],
            [
              "Paper record; official architecture",
              "论文记录；官方架构"
            ],
            [
              "C03 P04",
              "C03 P04"
            ]
          ],
          "sources": [
            "C03",
            "P04"
          ]
        },
        {
          "id": "c",
          "values": [
            [
              "ISCA",
              "ISCA"
            ],
            [
              "2026",
              "2026"
            ],
            [
              "MTIA300 built-in NICs",
              "MTIA300 built-in NICs"
            ],
            [
              "Meta authors",
              "Meta authors"
            ],
            [
              "MTIA300",
              "MTIA300"
            ],
            [
              "Full paper",
              "完整论文"
            ],
            [
              "C01",
              "C01"
            ]
          ],
          "sources": [
            "C01"
          ]
        },
        {
          "id": "d",
          "values": [
            [
              "AI Infra @Scale",
              "AI Infra @Scale"
            ],
            [
              "2024",
              "2024"
            ],
            [
              "Hardware and co-design of MTIA",
              "Hardware and co-design of MTIA"
            ],
            [
              "Colburn; Lan; Montgomery",
              "Colburn; Lan; Montgomery"
            ],
            [
              "MTIA200",
              "MTIA200"
            ],
            [
              "Engineering presentation",
              "工程演讲"
            ],
            [
              "P02",
              "P02"
            ]
          ],
          "sources": [
            "P02"
          ]
        },
        {
          "id": "e",
          "values": [
            [
              "SC",
              "SC"
            ],
            [
              "2026",
              "2026"
            ],
            [
              "HCCL",
              "HCCL"
            ],
            [
              "Meta authors",
              "Meta authors"
            ],
            [
              "MTIA communication",
              "MTIA communication"
            ],
            [
              "Preprint; November event still future",
              "预印本；11 月会议尚未举行"
            ],
            [
              "C04",
              "C04"
            ]
          ],
          "sources": [
            "C04"
          ]
        },
        {
          "id": "f",
          "values": [
            [
              "Company technical disclosure",
              "Company technical disclosure"
            ],
            [
              "2026",
              "2026"
            ],
            [
              "Four MTIA chips in two years",
              "Four MTIA chips in two years"
            ],
            [
              "Meta",
              "Meta"
            ],
            [
              "300 / 400 / 450 / 500",
              "300 / 400 / 450 / 500"
            ],
            [
              "Product and roadmap",
              "产品与路线图"
            ],
            [
              "E01",
              "E01"
            ]
          ],
          "sources": [
            "E01"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2
        ],
        [
          0,
          3,
          4,
          5,
          6
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "cross": {
      "id": "cross",
      "title": [
        "Naming and ownership",
        "命名与归属"
      ],
      "headers": [
        [
          "Name",
          "名称"
        ],
        [
          "Alias / role",
          "别名／角色"
        ],
        [
          "Boundary",
          "边界"
        ]
      ],
      "rows": [
        {
          "id": "a",
          "values": [
            [
              "MTIA100",
              "MTIA100"
            ],
            [
              "MTIA v1",
              "MTIA v1"
            ],
            [
              "Inference ASIC",
              "推理 ASIC"
            ]
          ],
          "sources": [
            "E01"
          ]
        },
        {
          "id": "b",
          "values": [
            [
              "MTIA200",
              "MTIA200"
            ],
            [
              "MTIA2i",
              "MTIA2i"
            ],
            [
              "Not MTIA300 training chip",
              "不同于 MTIA300 训练芯片"
            ]
          ],
          "sources": [
            "E01"
          ]
        },
        {
          "id": "c",
          "values": [
            [
              "HCCL",
              "HCCL"
            ],
            [
              "Hoot",
              "Hoot"
            ],
            [
              "Not Huawei HCCL",
              "不同于华为 HCCL"
            ]
          ],
          "sources": [
            "C04"
          ]
        },
        {
          "id": "d",
          "values": [
            [
              "MSVP",
              "MSVP"
            ],
            [
              "Video transcoding",
              "视频转码"
            ],
            [
              "Separate ASIC branch",
              "独立 ASIC 分支"
            ]
          ],
          "sources": [
            "E04"
          ]
        },
        {
          "id": "e",
          "values": [
            [
              "Broadcom",
              "Broadcom"
            ],
            [
              "MTIA development partner",
              "MTIA 开发伙伴"
            ],
            [
              "Not a merchant MTIA SKU",
              "不是商用 MTIA SKU"
            ]
          ],
          "sources": [
            "E01"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "isscc_context": {
      "id": "isscc_context",
      "title": [
        "ISSCC background",
        "ISSCC 背景"
      ],
      "headers": [
        [
          "Venue",
          "会议／活动"
        ],
        [
          "Year",
          "年份"
        ],
        [
          "Paper / talk / disclosure",
          "论文／演讲／披露"
        ],
        [
          "Presenter / authors",
          "报告人／作者"
        ],
        [
          "Product",
          "产品"
        ],
        [
          "Evidence type",
          "证据类型"
        ],
        [
          "Source",
          "来源"
        ]
      ],
      "rows": [
        {
          "id": "l",
          "values": [
            [
              "ISSCC plenary",
              "ISSCC plenary"
            ],
            [
              "2019",
              "2019"
            ],
            [
              "Deep Learning Hardware: Past, Present, & Future",
              "Deep Learning Hardware: Past, Present, & Future"
            ],
            [
              "Yann LeCun",
              "Yann LeCun"
            ],
            [
              "Research context; not MTIA implementation",
              "Research context; not MTIA implementation"
            ],
            [
              "Official plenary record",
              "官方主旨报告记录"
            ],
            [
              "C05",
              "C05"
            ]
          ],
          "sources": [
            "C05"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2
        ],
        [
          0,
          3,
          4,
          5,
          6
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    }
  },
  "figures": {
    "early": {
      "id": "early",
      "title": [
        "2023-2024 stack",
        "2023-2024 技术栈"
      ],
      "nodes": [
        [
          "cpu",
          [
            "External host CPU",
            "外部主机 CPU"
          ],
          0,
          0
        ],
        [
          "gpu",
          [
            "MTIA PE array",
            "MTIA 处理单元阵列"
          ],
          0,
          1
        ],
        [
          "mem",
          [
            "LPDDR5 / SRAM",
            "LPDDR5 / SRAM"
          ],
          0,
          2
        ],
        [
          "sw",
          [
            "PyTorch / compiler / HCCL",
            "PyTorch / compiler / HCCL"
          ],
          1,
          0
        ],
        [
          "net",
          [
            "PCIe fabric / optional RDMA",
            "PCIe fabric / optional RDMA"
          ],
          1,
          1
        ],
        [
          "rack",
          [
            "Rack / cooling / operations",
            "机架／散热／运维"
          ],
          1,
          2
        ]
      ],
      "edges": [
        [
          "cpu",
          "gpu",
          [
            "PCIe",
            "PCIe"
          ]
        ],
        [
          "gpu",
          "mem",
          [
            "memory",
            "存储"
          ]
        ],
        [
          "gpu",
          "net",
          [
            "data",
            "数据"
          ]
        ],
        [
          "net",
          "rack",
          [
            "integration",
            "集成"
          ]
        ]
      ],
      "caption": [
        "Later diagram includes announced products; silicon and rack availability are tracked separately.",
        "后期图包含已公布产品；芯片与机架可用性分别记录。"
      ]
    },
    "late": {
      "id": "late",
      "title": [
        "2026 roadmap stack",
        "2026 roadmap 技术栈"
      ],
      "nodes": [
        [
          "cpu",
          [
            "External host CPU",
            "外部主机 CPU"
          ],
          0,
          0
        ],
        [
          "gpu",
          [
            "MTIA PE array",
            "MTIA 处理单元阵列"
          ],
          0,
          1
        ],
        [
          "mem",
          [
            "HBM3e / SRAM",
            "HBM3e / SRAM"
          ],
          0,
          2
        ],
        [
          "sw",
          [
            "PyTorch / compiler / HCCL",
            "PyTorch / compiler / HCCL"
          ],
          1,
          0
        ],
        [
          "net",
          [
            "Integrated NICs / backplane",
            "Integrated NICs / backplane"
          ],
          1,
          1
        ],
        [
          "rack",
          [
            "Rack / cooling / operations",
            "机架／散热／运维"
          ],
          1,
          2
        ]
      ],
      "edges": [
        [
          "cpu",
          "gpu",
          [
            "PCIe",
            "PCIe"
          ]
        ],
        [
          "gpu",
          "mem",
          [
            "memory",
            "存储"
          ]
        ],
        [
          "gpu",
          "net",
          [
            "data",
            "数据"
          ]
        ],
        [
          "net",
          "rack",
          [
            "integration",
            "集成"
          ]
        ]
      ],
      "caption": [
        "Later diagram includes announced products; silicon and rack availability are tracked separately.",
        "后期图包含已公布产品；芯片与机架可用性分别记录。"
      ]
    }
  },
  "claims": {
    "gpu.100.0": {
      "value": "MTIA100 / v1",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P04"
      ],
      "disclosure_date": "2023",
      "status": "historical",
      "scope": "100"
    },
    "gpu.100.1": {
      "value": "Recommendation inference",
      "field": "Architecture",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P04"
      ],
      "disclosure_date": "2023",
      "status": "historical",
      "scope": "100"
    },
    "gpu.100.2": {
      "value": "2023 disclosure",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P04"
      ],
      "disclosure_date": "2023",
      "status": "historical",
      "scope": "100"
    },
    "gpu.100.3": {
      "value": "Historical shipping",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P04"
      ],
      "disclosure_date": "2023",
      "status": "historical",
      "scope": "100"
    },
    "gpu.100.4": {
      "value": "7 nm",
      "field": "Process",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P04"
      ],
      "disclosure_date": "2023",
      "status": "historical",
      "scope": "100"
    },
    "gpu.100.5": {
      "value": "1 logic die",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P04"
      ],
      "disclosure_date": "2023",
      "status": "historical",
      "scope": "100"
    },
    "gpu.100.6": {
      "value": "64 PEs",
      "field": "Compute units",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P04"
      ],
      "disclosure_date": "2023",
      "status": "historical",
      "scope": "100"
    },
    "gpu.100.7": {
      "value": "51.2 TFLOP/s",
      "field": "Dense BF16",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P04"
      ],
      "disclosure_date": "2023",
      "status": "historical",
      "scope": "100"
    },
    "gpu.100.8": {
      "value": "n/a",
      "field": "Dense FP8",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P04"
      ],
      "disclosure_date": "2023",
      "status": "historical",
      "scope": "100"
    },
    "gpu.100.9": {
      "value": "n/a",
      "field": "Dense FP6 / FP4",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P04"
      ],
      "disclosure_date": "2023",
      "status": "historical",
      "scope": "100"
    },
    "gpu.100.10": {
      "value": "n/d",
      "field": "FP64 vector / matrix",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P04"
      ],
      "disclosure_date": "2023",
      "status": "historical",
      "scope": "100"
    },
    "gpu.100.11": {
      "value": "LPDDR5; 64 GB; 0.176 TB/s",
      "field": "Memory: type; stacks; GB; TB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P04"
      ],
      "disclosure_date": "2023",
      "status": "historical",
      "scope": "100"
    },
    "gpu.100.12": {
      "value": "128 MB; 128 KB/PE",
      "field": "LLC / SRAM",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P04"
      ],
      "disclosure_date": "2023",
      "status": "historical",
      "scope": "100"
    },
    "gpu.100.13": {
      "value": "n/a",
      "field": "Scale-up: links; GB/s per direction; domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P04"
      ],
      "disclosure_date": "2023",
      "status": "historical",
      "scope": "100"
    },
    "gpu.100.14": {
      "value": "PCIe4 ×8",
      "field": "Host link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P04"
      ],
      "disclosure_date": "2023",
      "status": "historical",
      "scope": "100"
    },
    "gpu.100.15": {
      "value": "25 W",
      "field": "Power / cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P04"
      ],
      "disclosure_date": "2023",
      "status": "historical",
      "scope": "100"
    },
    "gpu.100.16": {
      "value": "Accelerator board",
      "field": "Form factor",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P04"
      ],
      "disclosure_date": "2023",
      "status": "historical",
      "scope": "100"
    },
    "gpu.200.0": {
      "value": "MTIA200 / 2i",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "C01"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "200"
    },
    "gpu.200.1": {
      "value": "Recommendation inference",
      "field": "Architecture",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "C01"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "200"
    },
    "gpu.200.2": {
      "value": "2024 deployment",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "C01"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "200"
    },
    "gpu.200.3": {
      "value": "Shipping / available",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "C01"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "200"
    },
    "gpu.200.4": {
      "value": "5 nm",
      "field": "Process",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "C01"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "200"
    },
    "gpu.200.5": {
      "value": "1 logic die",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "C01"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "200"
    },
    "gpu.200.6": {
      "value": "64 PEs",
      "field": "Compute units",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "C01"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "200"
    },
    "gpu.200.7": {
      "value": "177 TFLOP/s",
      "field": "Dense BF16",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "C01"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "200"
    },
    "gpu.200.8": {
      "value": "n/a",
      "field": "Dense FP8",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "C01"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "200"
    },
    "gpu.200.9": {
      "value": "n/a",
      "field": "Dense FP6 / FP4",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "C01"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "200"
    },
    "gpu.200.10": {
      "value": "n/d",
      "field": "FP64 vector / matrix",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "C01"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "200"
    },
    "gpu.200.11": {
      "value": "LPDDR5; 64-128 GB; 0.2048 TB/s",
      "field": "Memory: type; stacks; GB; TB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "C01"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "200"
    },
    "gpu.200.12": {
      "value": "256 MB; 384 KB/PE",
      "field": "LLC / SRAM",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "C01"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "200"
    },
    "gpu.200.13": {
      "value": "PCIe fabric; not dedicated scale-up",
      "field": "Scale-up: links; GB/s per direction; domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "C01"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "200"
    },
    "gpu.200.14": {
      "value": "PCIe5 ×8",
      "field": "Host link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "C01"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "200"
    },
    "gpu.200.15": {
      "value": "90 W launch; 85 W paper",
      "field": "Power / cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "C01"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "200"
    },
    "gpu.200.16": {
      "value": "Accelerator board",
      "field": "Form factor",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "C01"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "200"
    },
    "gpu.300.0": {
      "value": "MTIA300",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "300"
    },
    "gpu.300.1": {
      "value": "R&R training",
      "field": "Architecture",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "300"
    },
    "gpu.300.2": {
      "value": "2026 production",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "300"
    },
    "gpu.300.3": {
      "value": "Shipping / available",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "300"
    },
    "gpu.300.4": {
      "value": "n/d",
      "field": "Process",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "300"
    },
    "gpu.300.5": {
      "value": "1 compute + 2 network; interposer",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "300"
    },
    "gpu.300.6": {
      "value": "72 active PEs",
      "field": "Compute units",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "300"
    },
    "gpu.300.7": {
      "value": "560 TFLOP/s (paper)",
      "field": "Dense BF16",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "300"
    },
    "gpu.300.8": {
      "value": "1120 TFLOP/s (paper)",
      "field": "Dense FP8",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "300"
    },
    "gpu.300.9": {
      "value": "n/d",
      "field": "Dense FP6 / FP4",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "300"
    },
    "gpu.300.10": {
      "value": "n/d",
      "field": "FP64 vector / matrix",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "300"
    },
    "gpu.300.11": {
      "value": "HBM3e; 6; 216 GB; 6.1 TB/s",
      "field": "Memory: type; stacks; GB; TB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "300"
    },
    "gpu.300.12": {
      "value": "192 MB; 512 KB/PE",
      "field": "LLC / SRAM",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "300"
    },
    "gpu.300.13": {
      "value": "800-1000 GB/s one-way; 16 devices",
      "field": "Scale-up: links; GB/s per direction; domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "300"
    },
    "gpu.300.14": {
      "value": "PCIe5 ×16",
      "field": "Host link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "300"
    },
    "gpu.300.15": {
      "value": "912 W TDP / 667 W typical (paper)",
      "field": "Power / cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "300"
    },
    "gpu.300.16": {
      "value": "Liquid-cooled module",
      "field": "Form factor",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "300"
    },
    "gpu.400.0": {
      "value": "MTIA400",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "400"
    },
    "gpu.400.1": {
      "value": "GenAI / inference",
      "field": "Architecture",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "400"
    },
    "gpu.400.2": {
      "value": "2026 deployment path",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "400"
    },
    "gpu.400.3": {
      "value": "Announced; GA n/d",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "400"
    },
    "gpu.400.4": {
      "value": "n/d",
      "field": "Process",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "400"
    },
    "gpu.400.5": {
      "value": "2 compute chiplets",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "400"
    },
    "gpu.400.6": {
      "value": "n/d",
      "field": "Compute units",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "400"
    },
    "gpu.400.7": {
      "value": "3 PFLOP/s advertised; dense basis n/d",
      "field": "Dense BF16",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "400"
    },
    "gpu.400.8": {
      "value": "6 PFLOP/s FP8/MX8; dense basis n/d",
      "field": "Dense FP8",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "400"
    },
    "gpu.400.9": {
      "value": "12 PFLOP/s MX4; dense basis n/d",
      "field": "Dense FP6 / FP4",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "400"
    },
    "gpu.400.10": {
      "value": "n/d",
      "field": "FP64 vector / matrix",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "400"
    },
    "gpu.400.11": {
      "value": "HBM; stacks n/d; 288 GB; 9.2 TB/s",
      "field": "Memory: type; stacks; GB; TB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "400"
    },
    "gpu.400.12": {
      "value": "n/d",
      "field": "LLC / SRAM",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "400"
    },
    "gpu.400.13": {
      "value": "1200 GB/s one-way; 72 devices",
      "field": "Scale-up: links; GB/s per direction; domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "400"
    },
    "gpu.400.14": {
      "value": "n/d",
      "field": "Host link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "400"
    },
    "gpu.400.15": {
      "value": "1200 W module; liquid/AALC",
      "field": "Power / cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "400"
    },
    "gpu.400.16": {
      "value": "Rack module",
      "field": "Form factor",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "400"
    },
    "gpu.450.0": {
      "value": "MTIA450",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "450"
    },
    "gpu.450.1": {
      "value": "GenAI / inference",
      "field": "Architecture",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "450"
    },
    "gpu.450.2": {
      "value": "early 2027 target",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "450"
    },
    "gpu.450.3": {
      "value": "Roadmap",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "450"
    },
    "gpu.450.4": {
      "value": "n/d",
      "field": "Process",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "450"
    },
    "gpu.450.5": {
      "value": "n/d",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "450"
    },
    "gpu.450.6": {
      "value": "n/d",
      "field": "Compute units",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "450"
    },
    "gpu.450.7": {
      "value": "3.5 PFLOP/s advertised; dense basis n/d",
      "field": "Dense BF16",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "450"
    },
    "gpu.450.8": {
      "value": "7 PFLOP/s FP8/MX8; dense basis n/d",
      "field": "Dense FP8",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "450"
    },
    "gpu.450.9": {
      "value": "21 PFLOP/s MX4; dense basis n/d",
      "field": "Dense FP6 / FP4",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "450"
    },
    "gpu.450.10": {
      "value": "n/d",
      "field": "FP64 vector / matrix",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "450"
    },
    "gpu.450.11": {
      "value": "HBM; stacks n/d; 288 GB; 18.4 TB/s",
      "field": "Memory: type; stacks; GB; TB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "450"
    },
    "gpu.450.12": {
      "value": "n/d",
      "field": "LLC / SRAM",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "450"
    },
    "gpu.450.13": {
      "value": "1200 GB/s one-way; 72 devices",
      "field": "Scale-up: links; GB/s per direction; domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "450"
    },
    "gpu.450.14": {
      "value": "n/d",
      "field": "Host link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "450"
    },
    "gpu.450.15": {
      "value": "1400 W module; liquid/AALC",
      "field": "Power / cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "450"
    },
    "gpu.450.16": {
      "value": "Rack module",
      "field": "Form factor",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "450"
    },
    "gpu.500.0": {
      "value": "MTIA500",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "500"
    },
    "gpu.500.1": {
      "value": "GenAI / inference",
      "field": "Architecture",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "500"
    },
    "gpu.500.2": {
      "value": "2027 target",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "500"
    },
    "gpu.500.3": {
      "value": "Roadmap",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "500"
    },
    "gpu.500.4": {
      "value": "n/d",
      "field": "Process",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "500"
    },
    "gpu.500.5": {
      "value": "4 compute + 2 network + SoC",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "500"
    },
    "gpu.500.6": {
      "value": "n/d",
      "field": "Compute units",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "500"
    },
    "gpu.500.7": {
      "value": "5 PFLOP/s advertised; dense basis n/d",
      "field": "Dense BF16",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "500"
    },
    "gpu.500.8": {
      "value": "10 PFLOP/s FP8/MX8; dense basis n/d",
      "field": "Dense FP8",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "500"
    },
    "gpu.500.9": {
      "value": "30 PFLOP/s MX4; dense basis n/d",
      "field": "Dense FP6 / FP4",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "500"
    },
    "gpu.500.10": {
      "value": "n/d",
      "field": "FP64 vector / matrix",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "500"
    },
    "gpu.500.11": {
      "value": "HBM; stacks n/d; 384-512 GB; 27.6 TB/s",
      "field": "Memory: type; stacks; GB; TB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "500"
    },
    "gpu.500.12": {
      "value": "n/d",
      "field": "LLC / SRAM",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "500"
    },
    "gpu.500.13": {
      "value": "1200 GB/s one-way; 72 devices",
      "field": "Scale-up: links; GB/s per direction; domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "500"
    },
    "gpu.500.14": {
      "value": "n/d",
      "field": "Host link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "500"
    },
    "gpu.500.15": {
      "value": "1700 W module; liquid/AALC",
      "field": "Power / cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "500"
    },
    "gpu.500.16": {
      "value": "Rack module",
      "field": "Form factor",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "500"
    },
    "cpu.host.0": {
      "value": "External host CPUs",
      "field": "Generation / reference SKU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "E03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "host"
    },
    "cpu.host.1": {
      "value": "n/a",
      "field": "Codename",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "E03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "host"
    },
    "cpu.host.2": {
      "value": "n/a",
      "field": "GA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "E03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "host"
    },
    "cpu.host.3": {
      "value": "Supplier products",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "E03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "host"
    },
    "cpu.host.4": {
      "value": "n/a",
      "field": "Core µarch",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "E03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "host"
    },
    "cpu.host.5": {
      "value": "n/a",
      "field": "Cores / threads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "E03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "host"
    },
    "cpu.host.6": {
      "value": "n/a",
      "field": "Process per die",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "E03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "host"
    },
    "cpu.host.7": {
      "value": "n/a",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "E03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "host"
    },
    "cpu.host.8": {
      "value": "n/a",
      "field": "L2 per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "E03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "host"
    },
    "cpu.host.9": {
      "value": "n/a",
      "field": "L3 / domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "E03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "host"
    },
    "cpu.host.10": {
      "value": "n/a",
      "field": "Memory: channels; rate; GB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "E03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "host"
    },
    "cpu.host.11": {
      "value": "n/a",
      "field": "Sockets / links",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "E03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "host"
    },
    "cpu.host.12": {
      "value": "n/a",
      "field": "PCIe / CXL",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "E03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "host"
    },
    "cpu.host.13": {
      "value": "n/a",
      "field": "TDP",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "E03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "host"
    },
    "cpu.host.14": {
      "value": "n/a",
      "field": "Vector / matrix ISA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "E03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "host"
    },
    "nic.n.0": {
      "value": "MTIA300 network chiplets",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "deployed",
      "scope": "n"
    },
    "nic.n.1": {
      "value": "2026",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "deployed",
      "scope": "n"
    },
    "nic.n.2": {
      "value": "Shipping / available",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "deployed",
      "scope": "n"
    },
    "nic.n.3": {
      "value": "Integrated AI NIC",
      "field": "Class",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "deployed",
      "scope": "n"
    },
    "nic.n.4": {
      "value": "2×6×800 Gb/s",
      "field": "Ports × speed",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "deployed",
      "scope": "n"
    },
    "nic.n.5": {
      "value": "n/d",
      "field": "SerDes",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "deployed",
      "scope": "n"
    },
    "nic.n.6": {
      "value": "Die-to-die",
      "field": "Host interface",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "deployed",
      "scope": "n"
    },
    "nic.n.7": {
      "value": "Message engines / near-memory reduction",
      "field": "Programmable engine",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "deployed",
      "scope": "n"
    },
    "nic.n.8": {
      "value": "RISC-V control",
      "field": "Embedded CPU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "deployed",
      "scope": "n"
    },
    "nic.n.9": {
      "value": "Shared accelerator memory",
      "field": "On-card memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "deployed",
      "scope": "n"
    },
    "nic.n.10": {
      "value": "RDMA",
      "field": "Transport / RDMA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "deployed",
      "scope": "n"
    },
    "nic.n.11": {
      "value": "Credit-based fabric mechanisms",
      "field": "Congestion control",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "deployed",
      "scope": "n"
    },
    "nic.n.12": {
      "value": "Collectives; reductions; direct data path",
      "field": "Key offloads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "deployed",
      "scope": "n"
    },
    "nic.n.13": {
      "value": "Within module",
      "field": "Power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "deployed",
      "scope": "n"
    },
    "links.a.0": {
      "value": "MTIA200 host fabric",
      "field": "Interconnect",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "a"
    },
    "links.a.1": {
      "value": "2024",
      "field": "Year / generation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "a"
    },
    "links.a.2": {
      "value": "PCIe5 32 GT/s",
      "field": "Lane rate",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "a"
    },
    "links.a.3": {
      "value": "8",
      "field": "Lanes / link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "a"
    },
    "links.a.4": {
      "value": "~31.5 before packet overhead",
      "field": "GB/s per link per direction",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "a"
    },
    "links.a.5": {
      "value": "n/d",
      "field": "Links / device",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "a"
    },
    "links.a.6": {
      "value": "PCIe switching",
      "field": "Topology",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "a"
    },
    "links.a.7": {
      "value": "72/rack is packaging count",
      "field": "Domain limit",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "a"
    },
    "links.a.8": {
      "value": "PCIe",
      "field": "Coherence / semantics",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "a"
    },
    "links.b.0": {
      "value": "MTIA300 scale-up",
      "field": "Interconnect",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "b"
    },
    "links.b.1": {
      "value": "2026",
      "field": "Year / generation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "b"
    },
    "links.b.2": {
      "value": "800 Gb/s port",
      "field": "Lane rate",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "b"
    },
    "links.b.3": {
      "value": "n/d",
      "field": "Lanes / link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "b"
    },
    "links.b.4": {
      "value": "100",
      "field": "GB/s per link per direction",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "b"
    },
    "links.b.5": {
      "value": "Configuration-specific",
      "field": "Links / device",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "b"
    },
    "links.b.6": {
      "value": "Rack fabric",
      "field": "Topology",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "b"
    },
    "links.b.7": {
      "value": "16",
      "field": "Domain limit",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "b"
    },
    "links.b.8": {
      "value": "RDMA; explicit collectives",
      "field": "Coherence / semantics",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "b"
    },
    "links.c.0": {
      "value": "MTIA400/450/500 scale-up",
      "field": "Interconnect",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "c"
    },
    "links.c.1": {
      "value": "2026 roadmap",
      "field": "Year / generation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "c"
    },
    "links.c.2": {
      "value": "n/d",
      "field": "Lane rate",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "c"
    },
    "links.c.3": {
      "value": "n/d",
      "field": "Lanes / link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "c"
    },
    "links.c.4": {
      "value": "1200 aggregate/device",
      "field": "GB/s per link per direction",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "c"
    },
    "links.c.5": {
      "value": "n/d",
      "field": "Links / device",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "c"
    },
    "links.c.6": {
      "value": "Switched backplane",
      "field": "Topology",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "c"
    },
    "links.c.7": {
      "value": "72",
      "field": "Domain limit",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "c"
    },
    "links.c.8": {
      "value": "Explicit communication",
      "field": "Coherence / semantics",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "c"
    },
    "system.a.0": {
      "value": "MTIA200 rack",
      "field": "Platform",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "a"
    },
    "system.a.1": {
      "value": "2024",
      "field": "Year / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "a"
    },
    "system.a.2": {
      "value": "72 accelerators; 3 chassis",
      "field": "CPU / accelerator count",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "a"
    },
    "system.a.3": {
      "value": "PCIe topology",
      "field": "Scale-up domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "a"
    },
    "system.a.4": {
      "value": "Optional external RDMA NIC",
      "field": "Scale-out per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "a"
    },
    "system.a.5": {
      "value": "n/d",
      "field": "Rack power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "a"
    },
    "system.a.6": {
      "value": "Air",
      "field": "Cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04"
      ],
      "disclosure_date": "2024",
      "status": "deployed",
      "scope": "a"
    },
    "system.b.0": {
      "value": "MTIA300 rack",
      "field": "Platform",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "b"
    },
    "system.b.1": {
      "value": "2026",
      "field": "Year / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "b"
    },
    "system.b.2": {
      "value": "16 accelerators; 1 CPU/accelerator",
      "field": "CPU / accelerator count",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "b"
    },
    "system.b.3": {
      "value": "16",
      "field": "Scale-up domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "b"
    },
    "system.b.4": {
      "value": "200 GB/s nominal one-way",
      "field": "Scale-out per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "b"
    },
    "system.b.5": {
      "value": "n/d",
      "field": "Rack power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "b"
    },
    "system.b.6": {
      "value": "Liquid",
      "field": "Cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026",
      "status": "deployed",
      "scope": "b"
    },
    "system.c.0": {
      "value": "MTIA400/450/500 rack",
      "field": "Platform",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "c"
    },
    "system.c.1": {
      "value": "2026-2027 targets",
      "field": "Year / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "c"
    },
    "system.c.2": {
      "value": "72 accelerators",
      "field": "CPU / accelerator count",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "c"
    },
    "system.c.3": {
      "value": "72",
      "field": "Scale-up domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "c"
    },
    "system.c.4": {
      "value": "100 GB/s nominal one-way",
      "field": "Scale-out per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "c"
    },
    "system.c.5": {
      "value": "n/d",
      "field": "Rack power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "c"
    },
    "system.c.6": {
      "value": "AALC / facility liquid",
      "field": "Cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "c"
    },
    "software.a.0": {
      "value": "Frontend",
      "field": "Layer",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "P04"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "a"
    },
    "software.a.1": {
      "value": "PyTorch / torch.compile / export",
      "field": "Component",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "P04"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "a"
    },
    "software.a.2": {
      "value": "Model capture",
      "field": "Function",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "P04"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "a"
    },
    "software.a.3": {
      "value": "Shared framework interface",
      "field": "Architectural implication",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "P04"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "a"
    },
    "software.b.0": {
      "value": "Compiler",
      "field": "Layer",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "b"
    },
    "software.b.1": {
      "value": "TorchInductor / Triton / MLIR / LLVM",
      "field": "Component",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "b"
    },
    "software.b.2": {
      "value": "Graph and kernel lowering",
      "field": "Function",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "b"
    },
    "software.b.3": {
      "value": "Schedule local memories and engines",
      "field": "Architectural implication",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "b"
    },
    "software.c.0": {
      "value": "Communication",
      "field": "Layer",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04",
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "c"
    },
    "software.c.1": {
      "value": "Hoot Collective Communications Library",
      "field": "Component",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04",
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "c"
    },
    "software.c.2": {
      "value": "Collectives and reduction offload",
      "field": "Function",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04",
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "c"
    },
    "software.c.3": {
      "value": "HCCL here is Meta Hoot",
      "field": "Architectural implication",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04",
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "c"
    },
    "software.d.0": {
      "value": "Runtime",
      "field": "Layer",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "d"
    },
    "software.d.1": {
      "value": "Rust user-space driver / firmware",
      "field": "Component",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "d"
    },
    "software.d.2": {
      "value": "Memory, execution, observability",
      "field": "Function",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "d"
    },
    "software.d.3": {
      "value": "Host and device coordination",
      "field": "Architectural implication",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "d"
    },
    "software.e.0": {
      "value": "Serving",
      "field": "Layer",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "e"
    },
    "software.e.1": {
      "value": "vLLM plugin",
      "field": "Component",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "e"
    },
    "software.e.2": {
      "value": "Serving integration",
      "field": "Function",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "e"
    },
    "software.e.3": {
      "value": "Backend-specific optimized kernels",
      "field": "Architectural implication",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "e"
    },
    "ratios.a.0": {
      "value": "MTIA100 DRAM/BF16",
      "field": "Product / metric",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "a"
    },
    "ratios.a.1": {
      "value": "176e9/51.2e12 = 0.00344 B/FLOP",
      "field": "Calculation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "a"
    },
    "ratios.a.2": {
      "value": "Dense peak",
      "field": "Interpretation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "a"
    },
    "ratios.b.0": {
      "value": "MTIA200 DRAM/BF16",
      "field": "Product / metric",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "b"
    },
    "ratios.b.1": {
      "value": "204.8e9/177e12 = 0.00116 B/FLOP",
      "field": "Calculation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "b"
    },
    "ratios.b.2": {
      "value": "More reuse required than MTIA100",
      "field": "Interpretation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "b"
    },
    "ratios.c.0": {
      "value": "MTIA300 HBM/BF16",
      "field": "Product / metric",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "c"
    },
    "ratios.c.1": {
      "value": "6.1e12/560e12 = 0.0109 B/FLOP",
      "field": "Calculation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "c"
    },
    "ratios.c.2": {
      "value": "Paper configuration",
      "field": "Interpretation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "c"
    },
    "ratios.d.0": {
      "value": "MTIA300 capacity/BF16",
      "field": "Product / metric",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "d"
    },
    "ratios.d.1": {
      "value": "216e9/560e12 = 3.86e-4 B·s/FLOP",
      "field": "Calculation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "d"
    },
    "ratios.d.2": {
      "value": "Per accelerator",
      "field": "Interpretation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "d"
    },
    "ratios.e.0": {
      "value": "MTIA300 scale-up/HBM",
      "field": "Product / metric",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "e"
    },
    "ratios.e.1": {
      "value": "0.8/6.1 = 0.131",
      "field": "Calculation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "e"
    },
    "ratios.e.2": {
      "value": "Deployed paper configuration",
      "field": "Interpretation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "e"
    },
    "ratios.f.0": {
      "value": "MTIA400→500 scale-up/HBM",
      "field": "Product / metric",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "f"
    },
    "ratios.f.1": {
      "value": "1.2/9.2=0.130 → 1.2/27.6=0.0435",
      "field": "Calculation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "f"
    },
    "ratios.f.2": {
      "value": "Network grows slower than HBM",
      "field": "Interpretation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "f"
    },
    "ratios.g.0": {
      "value": "MTIA300 BF16/TDP",
      "field": "Product / metric",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "g"
    },
    "ratios.g.1": {
      "value": "560/912 = 0.614 TFLOP/s/W",
      "field": "Calculation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "g"
    },
    "ratios.g.2": {
      "value": "Peak/TDP; not application efficiency",
      "field": "Interpretation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "g"
    },
    "ratios.h.0": {
      "value": "Host DDR/core and L3/core",
      "field": "Product / metric",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "not_applicable",
      "scope": "h"
    },
    "ratios.h.1": {
      "value": "n/a",
      "field": "Calculation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "not_applicable",
      "scope": "h"
    },
    "ratios.h.2": {
      "value": "No Meta host-CPU SKU asserted",
      "field": "Interpretation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "not_applicable",
      "scope": "h"
    },
    "conference.a.0": {
      "value": "ISCA",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C02",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "published",
      "scope": "a"
    },
    "conference.a.1": {
      "value": "2023",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C02",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "published",
      "scope": "a"
    },
    "conference.a.2": {
      "value": "MTIA v1",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C02",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "published",
      "scope": "a"
    },
    "conference.a.3": {
      "value": "Meta authors",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C02",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "published",
      "scope": "a"
    },
    "conference.a.4": {
      "value": "MTIA100",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C02",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "published",
      "scope": "a"
    },
    "conference.a.5": {
      "value": "Architecture paper; official companion",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C02",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "published",
      "scope": "a"
    },
    "conference.a.6": {
      "value": "C02 P03",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C02",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "published",
      "scope": "a"
    },
    "conference.b.0": {
      "value": "ISCA",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03",
        "P04"
      ],
      "disclosure_date": "2025",
      "status": "published",
      "scope": "b"
    },
    "conference.b.1": {
      "value": "2025",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03",
        "P04"
      ],
      "disclosure_date": "2025",
      "status": "published",
      "scope": "b"
    },
    "conference.b.2": {
      "value": "Second-generation MTIA",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03",
        "P04"
      ],
      "disclosure_date": "2025",
      "status": "published",
      "scope": "b"
    },
    "conference.b.3": {
      "value": "Meta authors",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03",
        "P04"
      ],
      "disclosure_date": "2025",
      "status": "published",
      "scope": "b"
    },
    "conference.b.4": {
      "value": "MTIA200 / 2i",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03",
        "P04"
      ],
      "disclosure_date": "2025",
      "status": "published",
      "scope": "b"
    },
    "conference.b.5": {
      "value": "Paper record; official architecture",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03",
        "P04"
      ],
      "disclosure_date": "2025",
      "status": "published",
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