{
  "vendor": "Intel",
  "cutoff": "2026-09-28",
  "sections": [
    {
      "id": "01",
      "title": [
        "Executive synthesis and scope",
        "执行摘要与范围"
      ],
      "blocks": [
        {
          "id": "01.thesis",
          "type": "prose",
          "text": [
            "Intel’s AI infrastructure history is a history of several interacting architectures, rather than a single accelerator succession. Xeon remains the general-purpose execution and orchestration layer. Gaudi builds a training system around matrix engines and integrated Ethernet. Ponte Vecchio pursues heterogeneous packaging and high-performance scientific computing. IPUs remove infrastructure work from tenant CPUs. The latest inference GPU direction emphasizes model capacity and deployment into air-cooled servers. The central architectural question is how these independently developed components form a useful system.",
            "Intel 的 AI 基础设施史由多条相互作用的架构路线组成，并非单一加速器的连续换代。Xeon 承担通用执行与编排；Gaudi 围绕矩阵引擎和集成以太网构建训练系统；Ponte Vecchio 面向异构封装与高性能科学计算；IPU 将基础设施工作从租户 CPU 卸载；最新的推理 GPU 路线则强调模型容量以及在风冷服务器中的部署。核心架构问题是：这些独立发展的组件如何组成有效的系统。"
          ],
          "sources": [
            "P02",
            "P03",
            "P10",
            "E01"
          ]
        },
        {
          "id": "01.scope",
          "type": "prose",
          "text": [
            "Coverage runs from 2015 to 28 September 2026, with a short Haswell baseline. The organizing unit is the product generation. CPU and accelerator sections receive the greatest depth; networking, IPUs, packaging, optics, FPGA, memory, software and systems complete the portfolio. Client and edge products appear where they explain shared technology or a distinct deployment model. This is a curated technical history, not an inventory of every SKU or every Intel-affiliated conference paper.",
            "报告覆盖 2015 年至 2026 年 9 月 28 日，并以 Haswell 作简短基线。内容按产品代际组织，CPU 和加速器是重点；网络、IPU、封装、光互联、FPGA、内存、软件与系统补全产品版图。客户端和边缘产品用于解释共享技术或不同部署模式。本报告是经过筛选的技术史，并非全部 SKU 或 Intel 相关会议论文的穷尽目录。"
          ],
          "sources": [
            "P05",
            "E07"
          ]
        },
        {
          "id": "01.findings",
          "type": "prose",
          "text": [
            "The most consequential CPU transitions are the move from ring to mesh, the separation of private-cache and last-level-cache roles, the arrival of AMX and integrated offload engines, and the split into performance-core and efficiency-core server products. Chiplets then change from a way to extend die area into a way to place cores, cache and I/O on different processes. Clearwater Forest makes that separation vertical; Diamond Rapids extends it into a new announced performance-core platform. On accelerators, continuity is weaker: technical achievement and commercial roadmap survival must be assessed separately.",
            "CPU 最重要的变化包括：环形互联转向网格，私有缓存与末级缓存重新分工，AMX 和集成卸载引擎加入，以及服务器产品分为性能核和能效核路线。芯粒也从扩展裸片面积的手段，演变为让核心、缓存和 I/O 使用不同工艺的组织方式。Clearwater Forest 将这种分工推进到垂直堆叠；Diamond Rapids 则把它扩展至新公布的性能核平台。加速器路线的连续性较弱，必须分别评价技术成果和商业路线能否延续。"
          ],
          "sources": [
            "P06",
            "P03",
            "C12",
            "E01",
            "E02"
          ]
        },
        {
          "id": "portfolio",
          "type": "table",
          "table": "portfolio"
        }
      ]
    },
    {
      "id": "02",
      "title": [
        "How to read the numbers",
        "数值口径"
      ],
      "blocks": [
        {
          "id": "02.units",
          "type": "prose",
          "text": [
            "All bandwidths use decimal GB/s or TB/s. DRAM peak equals channels × transfer rate × eight data bytes; ECC bits do not add payload bandwidth. PCIe figures are per direction and precede protocol overhead. Ethernet Gb/s is divided by eight before comparison with memory bandwidth. A bidirectional aggregate is divided by two only when the source makes that convention explicit. HBM, package fabric, scale-up and scale-out bandwidth remain separate budgets.",
            "带宽统一采用十进制 GB/s 或 TB/s。DRAM 峰值等于通道数乘传输率再乘八个数据字节；ECC 位不增加有效载荷带宽。PCIe 数值按单方向计算，尚未扣除协议开销。以太网 Gb/s 先除以八，再与内存带宽比较。只有来源明确使用双向聚合口径时，才将数值除以二。HBM、封装内部互联、纵向扩展和横向扩展分别统计。"
          ],
          "sources": [
            "P02",
            "P05"
          ]
        },
        {
          "id": "02.status",
          "type": "prose",
          "text": [
            "CPU rows use representative high-end shipping configurations, not a composite assembled from different SKUs. Accelerator arithmetic is dense peak, with multiply-add counted as two operations. Tensor BF16 is not vector BF16; emulated formats are not native formats. Historical shipping does not mean currently orderable. Announcement, sampling and general availability are distinct. n/d means the reviewed evidence did not establish the value; n/a means the field does not apply. Sources are collected in the final source map and bibliography so the narrative can remain readable.",
            "CPU 表采用有代表性的高端商用配置，不将不同 SKU 的最大值拼成虚构产品。加速器算力使用稠密峰值，乘加计为两次运算。矩阵 BF16 不等于向量 BF16，模拟格式也不等于原生格式。历史已商用不代表目前仍可订购。公布、送样与正式商用分别标识。n/d 表示已审阅证据未确定该数值，n/a 表示不适用。来源集中列于文末映射和参考资料，保持正文流畅。"
          ],
          "sources": [
            "P02",
            "P09",
            "P16",
            "P17"
          ]
        }
      ]
    },
    {
      "id": "03",
      "title": [
        "Xeon generation atlas",
        "Xeon 代际总览"
      ],
      "blocks": [
        {
          "id": "03.notes",
          "type": "prose",
          "text": [
            "The table is a reference-SKU comparison: 8592+ is 350 W, while other Emerald Rapids SKUs have different power limits. Cooper Lake and Ice Lake are both called third-generation Xeon Scalable but address different socket segments and use different cores. Sierra Forest’s shipping 144-core reference must not be silently replaced by an earlier 288-core roadmap target. The Diamond Rapids row records the August 2026 disclosure, not final SKU specifications. Its memory figure is a channel-rate calculation; the reviewed announcement does not establish the final DIMM qualification matrix.",
            "表格比较参考 SKU：8592+ 为 350 W，其他 Emerald Rapids 型号的功耗限制不同。Cooper Lake 和 Ice Lake 都属于第三代 Xeon Scalable，但面向不同插槽市场并采用不同核心。不能用早期路线图中的 288 核目标替换 Sierra Forest 已商用的 144 核参考配置。Diamond Rapids 行记录 2026 年 8 月披露，并非最终 SKU 规格；内存带宽由通道和速率计算，已审阅公告尚未给出最终 DIMM 验证矩阵。"
          ],
          "sources": [
            "P17",
            "P26",
            "E01"
          ]
        },
        {
          "id": "cpu",
          "type": "table",
          "table": "cpu"
        }
      ]
    },
    {
      "id": "04",
      "title": [
        "Haswell and Broadwell: the monolithic baseline",
        "Haswell 与 Broadwell：单裸片基线"
      ],
      "blocks": [
        {
          "id": "04.core",
          "type": "prose",
          "text": [
            "Haswell-EP established the 2015 starting point with AVX2, DDR4 and a ring-connected server die. Broadwell-EP’s 2016 shrink to 14 nm raised the high-end E5 core count to 22 while retaining a 256 KB private L2 and a large inclusive LLC. The important constraint is the balance among cores, four memory channels and the ring. More cores increase aggregate execution demand without proportionately increasing off-chip bandwidth. Even before dedicated AI hardware, streaming and sparse workloads could run out of memory bandwidth before they ran out of arithmetic.",
            "Haswell-EP 以 AVX2、DDR4 和环形片上互联构成 2015 年的起点。2016 年 Broadwell-EP 转向 14 nm，将高端 E5 核心数提高到 22，同时保留每核 256 KB L2 与较大的包含式末级缓存。关键约束是核心、四个内存通道和环形互联之间的配比。增加核心会提高总执行需求，却不会同比增加片外带宽。即使在专用 AI 硬件出现之前，流式和稀疏工作负载也可能先耗尽内存带宽，而不是算术能力。"
          ],
          "sources": [
            "P05",
            "P20"
          ]
        },
        {
          "id": "04.segment",
          "type": "prose",
          "text": [
            "E5-2600 and E7 should be kept separate: E7 emphasized larger coherent socket domains and reliability, while E5 defined mainstream one- and two-socket servers. Xeon D brought related x86 technology into an integrated, lower-power SoC for network and edge systems. Desktop Core shared a core lineage but not the server’s memory-channel count, cache organization or socket interconnect. This distinction remains necessary throughout the report: core architecture is only one component of a server product.",
            "E5-2600 与 E7 应分别讨论：E7 强调更大的多路一致性域与可靠性，E5 则定义主流单路和双路服务器。Xeon D 将相关 x86 技术带入面向网络与边缘的低功耗集成 SoC。桌面 Core 共享核心谱系，但不共享服务器的内存通道数、缓存组织或插槽互联。后续各代也必须保持这一区分：核心架构只是服务器产品的一部分。"
          ],
          "sources": [
            "P05",
            "P07"
          ]
        }
      ]
    },
    {
      "id": "05",
      "title": [
        "Skylake, Cascade Lake and Cooper Lake",
        "Skylake、Cascade Lake 与 Cooper Lake"
      ],
      "blocks": [
        {
          "id": "05.mesh",
          "type": "prose",
          "text": [
            "Skylake-SP’s 2017 change is architectural, not merely a core-count increment. A two-dimensional mesh replaces the ring. Private L2 grows from 256 KB to 1 MB, while the LLC becomes smaller per core and non-inclusive. Capacity comparisons that add or compare L3 alone therefore misread the hierarchy. The larger private cache retains active data closer to execution; the LLC can act more effectively as a shared capacity and victim resource. Mesh routing, directory behavior and sub-NUMA clustering make placement important even inside one socket.",
            "2017 年 Skylake-SP 的变化是架构性的，而不仅是增加核心。二维网格取代环形互联；私有 L2 从 256 KB 增加到 1 MB；每核对应的末级缓存则缩小并转为非包含式。因此，仅比较或相加 L3 容量会误读整个层次。更大的私有缓存将活跃数据留在执行单元附近，末级缓存更多承担共享容量和被逐出数据的存储。网格路由、目录行为与子 NUMA 聚类，使单插槽内部的数据放置也变得重要。"
          ],
          "sources": [
            "P06",
            "P05"
          ]
        },
        {
          "id": "05.vector",
          "type": "prose",
          "text": [
            "Six DDR4 channels, UPI and AVX-512 accompany the mesh. AVX-512 doubles vector width relative to AVX2, but supported execution resources and operating frequency depend on SKU and instruction mix. Sustained application gain cannot be inferred from width alone. Cascade Lake keeps this broad organization and adds VNNI to reduce the instruction work for low-precision dot products. Its Optane persistent-memory support changes capacity and persistence semantics, not simply memory speed. The 9200-series Cascade Lake AP places two dies in one package; its 56-core headline is a separate product construction.",
            "网格同时配合六通道 DDR4、UPI 与 AVX-512。AVX-512 相比 AVX2 将向量宽度翻倍，但执行资源与运行频率取决于 SKU 和指令组合，不能由宽度直接推导持续应用收益。Cascade Lake 延续总体组织，并通过 VNNI 减少低精度点积所需指令。它对 Optane 持久内存的支持改变容量和持久性语义，而不只是改变速度。Cascade Lake AP 的 9200 系列在一个封装中放置两个裸片，56 核属于另一种产品构造。"
          ],
          "sources": [
            "P05",
            "C06",
            "P22"
          ]
        },
        {
          "id": "05.cooper",
          "type": "prose",
          "text": [
            "Cooper Lake adds AVX-512 BF16 and stronger multi-socket connectivity for scale-up systems. It is not the same silicon generation as Ice Lake, despite sharing the third-generation Xeon Scalable label. BF16 keeps FP32-like exponent range while shortening the significand, making it useful for neural-network arithmetic with appropriate accumulation. This is still vector execution, before AMX’s tile-based matrix datapath. Hot Chips’ Cascade Lake presentation supplies the feature transition; product and optimization documentation identify the actual deployment and programming constraints.",
            "Cooper Lake 为多路扩展系统增加 AVX-512 BF16 和更强的插槽互联。虽然同属第三代 Xeon Scalable，它并不是 Ice Lake 的同一种芯片。BF16 保留类似 FP32 的指数范围，同时缩短有效数，在合适累加方式下适合神经网络运算。这仍是向量执行，还未采用 AMX 的分块矩阵数据通路。Hot Chips 的 Cascade Lake 演讲解释功能转折，产品和优化文档则限定实际部署与编程条件。"
          ],
          "sources": [
            "P23",
            "P05",
            "C06"
          ]
        }
      ]
    },
    {
      "id": "06",
      "title": [
        "Ice Lake: a wider core and a wider server",
        "Ice Lake：核心与服务器同时扩展"
      ],
      "blocks": [
        {
          "id": "06.core",
          "type": "prose",
          "text": [
            "Ice Lake-SP arrives in 2021 with Sunny Cove, up to 40 cores, eight DDR4 channels and PCIe 4. The core expands out-of-order resources and the memory subsystem relative to the Skylake family, while the server implementation supplies a 1.25 MB L2 per core. A client Sunny Cove block diagram is useful background but is not a substitute for server cache and uncore documentation. The shift to eight memory channels raises theoretical DDR bandwidth to 204.8 GB/s, a substantial system change alongside the process and core improvements.",
            "2021 年 Ice Lake-SP 采用 Sunny Cove，最高 40 核、八通道 DDR4 和 PCIe 4。相对 Skylake 家族，核心扩展乱序执行资源和内存子系统，服务器实现提供每核 1.25 MB L2。客户端 Sunny Cove 框图可以提供背景，却不能替代服务器缓存与非核心部分文档。八通道内存将理论 DDR 带宽提高至 204.8 GB/s，这是与工艺和核心改进同样重要的系统变化。"
          ],
          "sources": [
            "P05",
            "P24"
          ]
        },
        {
          "id": "06.system",
          "type": "prose",
          "text": [
            "The server gains a more useful I/O budget for storage and accelerators, while SGX and memory-protection features address cloud isolation requirements. Yet it remains a monolithic CPU with a conventional external accelerator relationship. PCIe 4 x16 offers about 31.5 GB/s in one direction before higher-level overhead, far below the local memory bandwidth of contemporary HBM accelerators. Offloading a small kernel can therefore lose to keeping the computation on the CPU once transfer and synchronization are included. Xeon D derivatives adapt related technology to edge connectivity and long-lived platforms rather than reproducing the full server socket.",
            "服务器获得更实用的存储与加速器 I/O 预算，SGX 和内存保护功能服务于云隔离需求。但它仍是单裸片 CPU，与外部加速器保持传统连接关系。PCIe 4 x16 在扣除高层协议开销前，单方向约为 31.5 GB/s，远低于同期 HBM 加速器的本地带宽。因此计入传输与同步后，将小型内核卸载到加速器，可能反而不如留在 CPU 上执行。Xeon D 衍生产品将相关技术用于边缘连接和长生命周期平台，并不复制完整服务器插槽。"
          ],
          "sources": [
            "P24",
            "P05",
            "P07"
          ]
        }
      ]
    },
    {
      "id": "07",
      "title": [
        "Sapphire Rapids and Xeon Max: tiles and engines",
        "Sapphire Rapids 与 Xeon Max：芯粒和专用引擎"
      ],
      "blocks": [
        {
          "id": "07.package",
          "type": "prose",
          "text": [
            "Sapphire Rapids, commercially launched in January 2023, combines Golden Cove cores with DDR5, PCIe 5, CXL 1.1 and a four-tile EMIB construction in its high-end configuration. Each tile participates in a package-wide coherent system rather than exposing four independent processors. The ISSCC 2022 disclosure describes a quasi-monolithic integration approach and 10 TB/s of total die-to-die bandwidth across 20 interfaces at 0.5 pJ/bit. Those are implementation-level aggregate figures; they are not socket DRAM bandwidth or a software-visible remote-memory guarantee. Intel 7 is the commercial process name despite differing terminology in some conference summaries.",
            "2023 年 1 月商用的 Sapphire Rapids 将 Golden Cove 核心与 DDR5、PCIe 5、CXL 1.1 相结合，高端配置通过 EMIB 连接四个芯粒。各芯粒共同构成封装级一致性系统，并非四颗独立处理器。ISSCC 2022 披露准单片式集成方案，20 个接口合计提供 10 TB/s 裸片间带宽，能耗为 0.5 pJ/bit。这些是实现层面的聚合数值，不能作为插槽 DRAM 带宽或软件可见的远端内存保证。其商业工艺名称为 Intel 7，部分会议摘要的命名不同。"
          ],
          "sources": [
            "P03",
            "C03"
          ]
        },
        {
          "id": "07.amx",
          "type": "prose",
          "text": [
            "AMX changes CPU AI execution more fundamentally than another vector-width increase. Software configures tile registers and invokes matrix operations on blocks of INT8 or BF16 data. Libraries must select supported kernels, pack operands and manage tile state. Matrix peak rises faster than DRAM bandwidth, so cache reuse and batching become more valuable. AMX is therefore especially useful when a workload can retain data in cache or amortize weight reads; it does not make every inference workload compute-bound. CPU computation remains attractive for control-heavy operators and modest deployment sizes.",
            "AMX 对 CPU AI 执行方式的改变，比再次增加向量宽度更根本。软件配置 tile 寄存器，对 INT8 或 BF16 数据块执行矩阵操作。库需要选择适用内核、打包操作数并管理 tile 状态。矩阵峰值增长快于 DRAM 带宽，因此缓存复用和批处理更加重要。工作负载能够将数据保留在缓存，或摊薄权重读取成本时，AMX 尤其有效；它不会让所有推理任务都变成计算受限。控制密集型算子和较小部署规模仍适合 CPU。"
          ],
          "sources": [
            "P03",
            "R01",
            "P05"
          ]
        },
        {
          "id": "07.offload",
          "type": "prose",
          "text": [
            "DSA, IAA, QAT and DLB target different kinds of overhead: data movement, analytics/compression, cryptography/compression, and event distribution. Their value comes from removing work and cache pollution from cores, but queue submission, completion, data locality and minimum useful transfer sizes still matter. The ASPLOS 2024 DSA study measures these tradeoffs on actual hardware. A block appearing on the package is not evidence that an application automatically uses it; software enablement and SKU licensing/configuration must be checked.",
            "DSA、IAA、QAT 与 DLB 分别处理不同开销：数据搬移、分析／压缩、密码／压缩以及事件分发。它们通过减少核心工作和缓存污染创造价值，但队列提交、完成通知、数据局部性以及有效传输规模仍然重要。ASPLOS 2024 的 DSA 研究在真实硬件上测量了这些权衡。封装内存在某个模块，不代表应用自动使用它；还需要核对软件启用和 SKU 授权／配置。"
          ],
          "sources": [
            "P03",
            "R02"
          ]
        },
        {
          "id": "07.hbm",
          "type": "prose",
          "text": [
            "Xeon Max adds 64 GB of HBM2e around the CPU tiles, exposing HBM-only, flat and cache usage modes. This brings roughly 1 TB/s of local high-bandwidth memory to CPU code without converting the application to a GPU execution model. In flat mode, allocation policy determines which objects receive HBM service; in cache mode, locality and working-set behavior determine the benefit. HBM and DDR peaks cannot simply be added as the sustained bandwidth of one stream. Capacity-limited applications may still require DDR, while bandwidth-heavy scientific kernels can benefit substantially from the near-memory tier.",
            "Xeon Max 在 CPU 芯粒周围加入 64 GB HBM2e，提供仅 HBM、平坦寻址和缓存等使用模式。CPU 代码因此获得约 1 TB/s 的本地高带宽内存，而无需改写为 GPU 执行模型。平坦模式下，分配策略决定哪些对象使用 HBM；缓存模式下，局部性与工作集行为决定收益。不能将 HBM 和 DDR 峰值直接相加，视为单一数据流的持续带宽。容量受限应用仍可能需要 DDR，而带宽密集型科学内核可以显著受益于近端内存层。"
          ],
          "sources": [
            "P13",
            "P03"
          ]
        }
      ]
    },
    {
      "id": "08",
      "title": [
        "Emerald Rapids: cache and integration efficiency",
        "Emerald Rapids：缓存与集成效率"
      ],
      "blocks": [
        {
          "id": "08.design",
          "type": "prose",
          "text": [
            "Emerald Rapids launches in December 2023 on the established platform, with up to 64 cores and 320 MB LLC. The high-end implementation uses two larger tiles rather than Sapphire Rapids’ four-tile arrangement. Reducing tile boundaries changes fabric traffic, physical integration and cache organization without requiring a wholesale platform replacement. ISSCC 2024 is the useful implementation anchor: the disclosure emphasizes the Intel 7 multichip construction and substantially larger shared cache. Its reported iso-power workload gains are measured comparisons, not a universal IPC multiplier.",
            "Emerald Rapids 于 2023 年 12 月在既有平台上推出，最高 64 核、320 MB 末级缓存。高端实现使用两个较大芯粒，而不是 Sapphire Rapids 的四芯粒组织。减少芯粒边界会改变互联流量、物理集成与缓存组织，同时避免全面更换平台。ISSCC 2024 是重要实现依据，重点披露 Intel 7 多芯片构造和大幅扩大的共享缓存。其中的等功耗工作负载收益属于特定测量，不能当作通用 IPC 倍数。"
          ],
          "sources": [
            "C04",
            "P26"
          ]
        },
        {
          "id": "08.balance",
          "type": "prose",
          "text": [
            "The representative 64-core part provides 5 MB of LLC per core, versus 1.875 MB for the 60-core Sapphire Rapids reference. That capacity increase can reduce expensive DRAM accesses for databases, graph structures and reused model data. DDR5-5600 also raises the channel peak, but the architectural gain depends on whether a workload was cache-capacity-limited, bandwidth-limited or compute-limited. This generation demonstrates why packaging and cache redesign can matter even when the process node and major matrix ISA remain unchanged.",
            "64 核参考产品平均每核对应 5 MB LLC，而 60 核 Sapphire Rapids 参考产品为 1.875 MB。容量增加可以减少数据库、图结构和重复使用的模型数据所产生的昂贵 DRAM 访问。DDR5-5600 同时提高通道峰值，但实际架构收益取决于工作负载原先受限于缓存容量、带宽还是计算。这一代说明：即使工艺节点和主要矩阵 ISA 不变，封装与缓存重构仍可能非常重要。"
          ],
          "sources": [
            "P26",
            "P03",
            "C04"
          ]
        }
      ]
    },
    {
      "id": "09",
      "title": [
        "Xeon 6: separating performance and density",
        "Xeon 6：性能与密度分线"
      ],
      "blocks": [
        {
          "id": "09.common",
          "type": "prose",
          "text": [
            "Hot Chips 2023 disclosed the shared platform strategy behind Granite Rapids and Sierra Forest before their 2024 launches. Compute tiles and I/O tiles are separated, allowing Intel 3 cores to be combined with Intel 7 I/O. The server family offers common infrastructure with different compute choices; it is not a hybrid desktop CPU mixing P-cores and E-cores in one socket. DDR5, CXL 2.0 and built-in accelerators belong to the platform story, while vector capability, cache organization and thread behavior remain core-family-specific.",
            "Hot Chips 2023 在两款产品于 2024 年商用前，披露了 Granite Rapids 和 Sierra Forest 的共享平台策略。计算芯粒与 I/O 芯粒分离，使 Intel 3 核心可以搭配 Intel 7 I/O。服务器家族在共同基础设施上提供不同计算选择，并不是在同一插槽混合 P 核与 E 核的桌面混合 CPU。DDR5、CXL 2.0 和内置加速器属于平台层面；向量能力、缓存组织与线程行为则因核心家族而异。"
          ],
          "sources": [
            "C12",
            "E04",
            "P16",
            "P17"
          ]
        },
        {
          "id": "09.p",
          "type": "prose",
          "text": [
            "Granite Rapids’ high-end 6900P configuration reaches 128 Redwood Cove cores, three compute tiles, twelve memory channels and 500 W on the 6980P reference. MRDIMM raises the qualified memory data rate to 8800 MT/s, yielding 844.8 GB/s of theoretical channel bandwidth. AMX adds FP16 support. The engineering point is balanced throughput: a much larger core complex needs more memory bandwidth and package connectivity, not just faster cores. The 6700P expansion in 2025 serves a different platform and channel envelope; its specifications should not be mixed with 6900P.",
            "Granite Rapids 高端 6900P 配置达到 128 个 Redwood Cove 核心、三个计算芯粒和十二个内存通道，6980P 参考产品为 500 W。MRDIMM 将支持的数据速率提高到 8800 MT/s，对应 844.8 GB/s 理论通道带宽。AMX 增加 FP16 支持。工程重点是吞吐配比：更大的核心复合体需要更多内存带宽和封装连接，而不仅是更快的核心。2025 年扩展的 6700P 使用不同平台和通道配置，不能与 6900P 混用规格。"
          ],
          "sources": [
            "P16",
            "P18",
            "E06",
            "C12"
          ]
        },
        {
          "id": "09.e",
          "type": "prose",
          "text": [
            "Sierra Forest’s 144-core shipping reference uses Crestmont E-cores without SMT or AMX. Four-core clusters share L2. The intended gain is density for independent throughput-oriented services, not equivalence to 144 large vector cores. A cloud service with many small requests can exploit this configuration; a heavily vectorized AMX workload cannot assume the same instruction path as Granite Rapids. At full population, the reference has about 2.84 GB/s of DRAM channel bandwidth per core. Core count is therefore meaningful only alongside workload concurrency, cache behavior and memory demand.",
            "Sierra Forest 已商用参考配置采用 144 个 Crestmont 能效核，没有 SMT 或 AMX，四核簇共享 L2。其目标是提高相互独立、面向吞吐的服务密度，而不是等同于 144 个大型向量核心。包含大量小请求的云服务可以利用这一配置；重度依赖向量和 AMX 的工作负载不能假设它具有 Granite Rapids 的执行路径。满核配置下，理论 DRAM 通道带宽平均每核约 2.84 GB/s。因此核心数必须结合并发度、缓存行为和内存需求理解。"
          ],
          "sources": [
            "P17",
            "C12"
          ]
        }
      ]
    },
    {
      "id": "10",
      "title": [
        "Clearwater Forest and Diamond Rapids",
        "Clearwater Forest 与 Diamond Rapids"
      ],
      "blocks": [
        {
          "id": "10.cwf",
          "type": "prose",
          "text": [
            "Clearwater Forest was discussed at Hot Chips 2025 and MWC 2026, then launched as Xeon 6+ in June 2026. Its 288 Darkmont E-cores occupy twelve Intel 18A compute chiplets above three Intel 3 base dies, with Intel 7 I/O. Foveros Direct 3D and EMIB combine vertical and lateral integration. This separates dense compute from cache/fabric and I/O implementation. The architectural opportunity is process specialization and shorter dense vertical connections; the corresponding engineering burden includes assembly yield, thermal coupling, power delivery and fabric placement.",
            "Clearwater Forest 在 Hot Chips 2025 和 MWC 2026 进行展示，随后于 2026 年 6 月以 Xeon 6+ 商用。288 个 Darkmont 能效核位于十二个 Intel 18A 计算芯粒中，下方为三个 Intel 3 基底裸片，并配合 Intel 7 I/O。Foveros Direct 3D 与 EMIB 结合垂直和水平集成，使高密度计算与缓存／互联、I/O 实现分离。架构机会在于工艺分工和更短、更密集的垂直连接；对应工程负担包括组装良率、热耦合、供电与互联放置。"
          ],
          "sources": [
            "E02",
            "P01",
            "P19",
            "E16",
            "P08",
            "P35"
          ]
        },
        {
          "id": "10.balance",
          "type": "prose",
          "text": [
            "The 6990E+ reference has 576 MB LLC and twelve DDR5-8000 channels. Compared with Sierra Forest’s reference, core count doubles while DRAM peak rises from 409.6 to 768 GB/s. Per-core channel bandwidth therefore changes from about 2.84 to 2.67 GB/s, while average LLC capacity rises from 0.75 to 2 MB per core. This is a cache-and-density design, not a claim that every core receives more external bandwidth. Its 288 cores are 288 hardware threads; multiplying by two would incorrectly apply P-core SMT behavior.",
            "6990E+ 参考配置具有 576 MB LLC 和十二通道 DDR5-8000。相对 Sierra Forest 参考配置，核心数翻倍，DRAM 峰值从 409.6 增至 768 GB/s。因此平均每核通道带宽从约 2.84 变为 2.67 GB/s，而平均每核 LLC 容量从 0.75 增至 2 MB。这是强调缓存和密度的设计，并不意味着每个核心获得更多外部带宽。288 个核心对应 288 个硬件线程，不能套用 P 核 SMT 行为再乘以二。"
          ],
          "sources": [
            "P01",
            "P17",
            "E02",
            "P19",
            "P08"
          ]
        },
        {
          "id": "10.dmr",
          "type": "prose",
          "text": [
            "At Hot Chips 2026, Intel disclosed Diamond Rapids with up to 256 new cores, 1.28 GB LLC, sixteen memory channels at 12800 MT/s, 128 PCIe 6 lanes and CXL 3.0. Intel 18A-P, Foveros Direct 3D, UCIe-S, a unified memory fabric, APX and enhanced AMX define the announced direction. The design moves performance-core Xeon toward a much larger distributed package. The public announcement establishes these headline parameters; it does not establish final SKU power, detailed queue sizes, thread count or commercial availability. Coral Rapids remains a subsequent roadmap name rather than a table of shipping specifications.",
            "Intel 在 Hot Chips 2026 披露 Diamond Rapids：最高 256 个新核心、1.28 GB LLC、十六个 12800 MT/s 内存通道、128 条 PCIe 6 通道以及 CXL 3.0。Intel 18A-P、Foveros Direct 3D、UCIe-S、统一内存互联、APX 和增强 AMX 构成已公布方向。性能核 Xeon 因此走向更大的分布式封装。公开公告确认这些主要参数，但未确定最终 SKU 功耗、详细队列规模、线程数或商用时间。Coral Rapids 仍属于后续路线图名称，不能填写为已商用规格。"
          ],
          "sources": [
            "E01",
            "E08"
          ]
        }
      ]
    },
    {
      "id": "11",
      "title": [
        "Accelerator generation atlas",
        "加速器代际总览"
      ],
      "blocks": [
        {
          "id": "accelerators",
          "type": "table",
          "table": "accelerators"
        },
        {
          "id": "11.basis",
          "type": "prose",
          "text": [
            "Gaudi 3 uses the retrieved architecture whitepaper’s 1678 TFLOPS BF16/FP8 values, not a mixture with other clock-point marketing figures. The 600 W HL-338 PCIe card is a separate configuration and should not inherit OAM peak numbers without verification. GPU Max’s 636 GB/s bidirectional Xe Link figure comes from the specific Lenovo system specification and is normalized to 318 GB/s per direction. It is not a claim that every Ponte Vecchio system exposes the same external link topology. Xeon Phi is included as a historical many-core accelerator lineage, although Knights Landing can boot its own operating system.",
            "Gaudi 3 使用本次获取的架构白皮书中 BF16／FP8 均为 1678 TFLOPS 的数值，不与其他时钟工作点的宣传值混合。600 W 的 HL-338 PCIe 卡属于另一配置，未经核实不能套用 OAM 峰值。GPU Max 的 Xe Link 双向 636 GB/s 来自特定 Lenovo 系统规格，归一化为单方向 318 GB/s，并不代表所有 Ponte Vecchio 系统都开放相同外部链路拓扑。Xeon Phi 作为历史多核加速器谱系列入，尽管 Knights Landing 能独立启动操作系统。"
          ],
          "sources": [
            "P02",
            "P09",
            "P27",
            "P28"
          ]
        }
      ]
    },
    {
      "id": "12",
      "title": [
        "Xeon Phi and Nervana: earlier parallel-compute paths",
        "Xeon Phi 与 Nervana：早期并行计算路线"
      ],
      "blocks": [
        {
          "id": "12.phi",
          "type": "prose",
          "text": [
            "Knights Landing, disclosed at Hot Chips 2015 and commercialized in 2016, combines many small x86 cores, four hardware threads per core, wide vector execution, a mesh and 16 GB of on-package MCDRAM. It is more than a PCIe coprocessor: a self-hosted system can run a conventional operating system and use DDR4 for capacity. Cache, flat and hybrid memory modes expose an early version of the placement problem later revisited by Xeon Max. The software appeal is x86 and familiar parallel programming; achieving throughput still requires vectorization, many concurrent threads and careful memory use.",
            "Knights Landing 在 Hot Chips 2015 披露，并于 2016 年商用。它结合大量小型 x86 核心、每核四个硬件线程、宽向量执行、网格互联和 16 GB 封装内 MCDRAM。它不只是 PCIe 协处理器，还能独立运行常规操作系统，并通过 DDR4 扩充容量。缓存、平坦和混合内存模式，较早暴露了后来 Xeon Max 再次面对的数据放置问题。软件吸引力是 x86 和熟悉的并行编程，但高吞吐仍依赖向量化、大量并发线程和谨慎的内存使用。"
          ],
          "sources": [
            "P28",
            "P05",
            "C13"
          ]
        },
        {
          "id": "12.end",
          "type": "prose",
          "text": [
            "Knights Mill redirected the many-core line toward deep learning with specialized vector instructions, but it did not become the AMX architecture used by later Xeons. Nervana’s NNP-T and NNP-I subsequently explored dedicated training and inference datapaths. Intel’s acquisition of Habana and the later concentration on Gaudi changed the commercial direction. These branches belong in the history because they reveal changing assumptions about programmability, numerical formats and interconnect, not because they form a continuous shipping sequence into current GPUs. A discontinued program’s projected successor must not appear as a delivered generation.",
            "Knights Mill 通过专门向量指令将多核路线转向深度学习，但它并未成为后来 Xeon 的 AMX 架构。此后 Nervana 的 NNP-T 和 NNP-I 分别探索专用训练与推理数据通路。Intel 收购 Habana 并随后集中资源于 Gaudi，改变了商业方向。这些分支值得纳入历史，是因为它们反映了对可编程性、数值格式和互联假设的变化，而不是因为它们与当前 GPU 构成连续商用序列。已终止项目所规划的后继者不能列作已交付代际。"
          ],
          "sources": [
            "E17",
            "P30",
            "C14"
          ]
        }
      ]
    },
    {
      "id": "13",
      "title": [
        "Gaudi 1, 2 and 3: Ethernet inside the accelerator",
        "Gaudi 1、2 与 3：加速器内置以太网"
      ],
      "blocks": [
        {
          "id": "13.first",
          "type": "prose",
          "text": [
            "Gaudi begins with a different decomposition from a graphics-derived GPU. Matrix multiplication engines perform the dense linear algebra; programmable Tensor Processor Cores handle the surrounding operations; local HBM supplies capacity and bandwidth; integrated RoCE-capable Ethernet ports carry device communication. AWS DL1’s October 2021 general availability provides a concrete first-generation deployment milestone: eight Gaudi devices with 32 GB HBM each. Its 400 Gb/s instance networking is a cloud service limit and must not be confused with the sum of every on-chip Gaudi port.",
            "Gaudi 的功能划分不同于源于图形处理的 GPU。矩阵乘法引擎负责稠密线性代数，可编程 Tensor Processor Core 处理周边运算，本地 HBM 提供容量和带宽，集成的支持 RoCE 的以太网端口承担设备通信。AWS DL1 于 2021 年 10 月正式商用，为第一代提供具体部署里程碑：八颗 Gaudi，每颗 32 GB HBM。实例的 400 Gb/s 网络吞吐属于云服务限制，不能与 Gaudi 所有片上端口之和混淆。"
          ],
          "sources": [
            "E14",
            "P30"
          ]
        },
        {
          "id": "13.second",
          "type": "prose",
          "text": [
            "Gaudi 2 scales the design to 24 TPCs, two MMEs, 96 GB HBM2e and 24 × 100 GbE ports. The matrix path supports BF16 and FP8 at different peak rates. A large software-managed SRAM helps reuse data and reduce HBM traffic, but it is not automatically equivalent to a CPU’s coherent last-level cache. The architecture depends on compiler scheduling across matrix, vector, DMA and communication resources. Its main system distinction is the ability to build both the local accelerator group and the external fabric from Ethernet mechanisms.",
            "Gaudi 2 将设计扩展至 24 个 TPC、两个 MME、96 GB HBM2e 和 24×100 GbE 端口。矩阵路径对 BF16 与 FP8 提供不同峰值。较大的软件管理 SRAM 帮助复用数据并减少 HBM 流量，但它不自动等同于 CPU 的一致性末级缓存。架构依赖编译器对矩阵、向量、DMA 和通信资源进行调度。系统上的主要区别是：本地加速器组和外部网络都可以基于以太网机制构建。"
          ],
          "sources": [
            "P02",
            "P30"
          ]
        },
        {
          "id": "13.third",
          "type": "prose",
          "text": [
            "Gaudi 3 moves to two compute dies, eight MMEs, 64 TPCs, 128 GB HBM2e and 24 × 200 GbE. The two-die construction expands compute and memory interfaces, while communication must cross internal partitions when data is not local. On the eight-accelerator baseboard, 21 ports per device supply three links to each of seven peers, leaving three ports for scale-out. That partitions the 600 GB/s one-way all-port budget into 525 GB/s local peer traffic and 75 GB/s external traffic. The total cannot be counted independently in both directions and both roles.",
            "Gaudi 3 转向双计算裸片，配备八个 MME、64 个 TPC、128 GB HBM2e 和 24×200 GbE。双裸片扩大计算和内存接口，但非本地数据需要跨越内部区域通信。在八加速器基板上，每颗芯片的 21 个端口分别以三条链路连接其余七颗芯片，留下三个端口用于横向扩展。因此单方向 600 GB/s 的全部端口预算，被划分为 525 GB/s 本地对等流量和 75 GB/s 外部流量，不能在两个方向和两种用途上重复计算总量。"
          ],
          "sources": [
            "P02"
          ]
        },
        {
          "id": "13.system",
          "type": "prose",
          "text": [
            "Integrated networking removes the need for a separate NIC for these accelerator links, but it does not remove the Ethernet switching fabric, congestion control, cabling or collective algorithms. HCCL, SynapseAI and framework integration determine whether the hardware overlaps communication with computation and supports the needed operators. Gaudi 3’s PCIe variant extends deployment into more conventional servers with a different power envelope. The practical comparison with a GPU system is therefore a complete supported training or inference configuration, including software and network topology, rather than a single peak-FLOPS column.",
            "集成网络消除了这些加速器链路对独立 NIC 的需求，却不会消除以太网交换网络、拥塞控制、布线或集合通信算法。HCCL、SynapseAI 和框架集成决定硬件能否重叠通信与计算，以及是否支持所需算子。Gaudi 3 的 PCIe 变体以不同功耗范围进入更常规的服务器。与 GPU 系统比较时，应比较完整且受支持的训练或推理配置，包括软件和网络拓扑，而不是只看一个峰值 FLOPS 列。"
          ],
          "sources": [
            "P02",
            "P09",
            "P04",
            "E09"
          ]
        }
      ]
    },
    {
      "id": "14",
      "title": [
        "Ponte Vecchio: a heterogeneous HPC package",
        "Ponte Vecchio：异构 HPC 封装"
      ],
      "blocks": [
        {
          "id": "14.package",
          "type": "prose",
          "text": [
            "Ponte Vecchio’s ISSCC 2022 disclosure is one of the clearest examples of implementation driving architecture. The 47-tile integration includes sixteen 5 nm compute tiles and multiple process technologies, connected through Foveros and EMIB. The count is not 47 compute dies. Compute tiles, base/cache resources, link tiles and HBM perform different roles. This lets each function use a suitable manufacturing and integration choice, at the cost of complex assembly, testing, power delivery and thermal management. The conference prototype’s measured figures and the later GPU Max SKU peaks are different evidence points.",
            "Ponte Vecchio 在 ISSCC 2022 的披露，是实现方式推动架构的典型案例。47 芯粒集成包含十六个 5 nm 计算芯粒及多种工艺，并通过 Foveros 和 EMIB 连接。这里并非 47 个计算裸片：计算芯粒、基底／缓存资源、互联芯粒和 HBM 分别承担不同角色。各功能可以采用适合的制造与集成方式，代价是复杂组装、测试、供电和热管理。会议原型的实测指标与后来 GPU Max SKU 的峰值属于不同证据点。"
          ],
          "sources": [
            "C03",
            "P11",
            "P27"
          ]
        },
        {
          "id": "14.compute",
          "type": "prose",
          "text": [
            "The commercial Max 1550 combines 128 Xe-HPC cores, XMX matrix execution, strong native FP64, 128 GB HBM2e and a large distributed L2. Unlike an inference-only accelerator, it invests heavily in scientific arithmetic and HPC execution. Xe Link connects peer GPUs; PCIe connects the host. A unified programming abstraction does not make CPU DDR and GPU HBM physically uniform or equally fast. Aurora demonstrates a system built around CPU and GPU high-bandwidth memory, but its communication and placement costs still have to be managed by applications and runtimes.",
            "商用 Max 1550 结合 128 个 Xe-HPC 核心、XMX 矩阵执行、较强的原生 FP64、128 GB HBM2e 和大型分布式 L2。与仅面向推理的加速器不同，它在科学计算精度和 HPC 执行方面投入较多资源。Xe Link 连接对等 GPU，PCIe 连接主机。统一编程抽象不会让 CPU DDR 与 GPU HBM 在物理上统一或等速。Aurora 展示了围绕 CPU 和 GPU 高带宽内存构建的系统，但应用与运行时仍需管理通信和数据放置成本。"
          ],
          "sources": [
            "P27",
            "P11",
            "P31"
          ]
        },
        {
          "id": "14.roadmap",
          "type": "prose",
          "text": [
            "Ponte Vecchio’s technical success as an integration vehicle should be separated from the breadth and longevity of the commercial line. Lenovo’s SD650-I V3 product guide is explicitly marked withdrawn, despite documenting a real four-GPU system. Falcon Shores was later designated an internal test chip rather than a marketed successor. Consequently, it is misleading to draw an uninterrupted arrow from Xeon Phi through GPU Max to a shipping Falcon Shores platform. Product continuity, software support and deployable system supply are architecture constraints in their own right.",
            "Ponte Vecchio 作为集成技术载体的成果，应与商业产品线的覆盖范围和持续时间分开评价。Lenovo SD650-I V3 产品指南明确标记停止营销，但它确实记录了实际存在的四 GPU 系统。Falcon Shores 后来被定位为内部测试芯片，而非上市后继产品。因此，不能画出从 Xeon Phi 经 GPU Max 直接走向已商用 Falcon Shores 的连续路线。产品延续性、软件支持和可部署系统供应本身就是架构约束。"
          ],
          "sources": [
            "P27",
            "E17"
          ]
        }
      ]
    },
    {
      "id": "15",
      "title": [
        "Flex, Arc and Crescent Island: inference branches",
        "Flex、Arc 与 Crescent Island：推理分支"
      ],
      "blocks": [
        {
          "id": "15.flex",
          "type": "prose",
          "text": [
            "Flex 140 and Flex 170 serve media processing, cloud graphics, virtualization and visual inference with Xe-HPG technology and GDDR6. Flex 140 places two small GPUs on a 75 W card, with separate 6 GB memories; these are not one coherent 12 GB GPU. Flex 170 uses one 32-core GPU with 16 GB and a 150 W board envelope. Shared technology with Arc explains the graphics and media engines, but server drivers, virtualization, cooling and supported workloads determine the datacenter product. A graphics-derived matrix engine does not imply GPU Max’s FP64 or HBM characteristics.",
            "Flex 140 和 Flex 170 采用 Xe-HPG 与 GDDR6，服务于媒体处理、云图形、虚拟化和视觉推理。Flex 140 在 75 W 板卡上放置两颗小 GPU，各有独立的 6 GB 内存，并非一颗具有一致性 12 GB 内存的 GPU。Flex 170 采用单颗 32 核 GPU、16 GB 内存和 150 W 板级功耗。与 Arc 共享技术解释了图形和媒体引擎，但服务器驱动、虚拟化、散热和受支持工作负载才定义数据中心产品。源于图形路线的矩阵引擎不意味着具有 GPU Max 的 FP64 或 HBM 特性。"
          ],
          "sources": [
            "P29",
            "P11"
          ]
        },
        {
          "id": "15.crescent",
          "type": "prose",
          "text": [
            "Crescent Island is a distinct inference-oriented direction. The October 2025 OCP announcement described 160 GB LPDDR5X and customer sampling targeted for the second half of 2026. By Computex and Hot Chips 2026, Intel described up to 480 GB, a 350 W air-cooled PCIe card, 32 Xe3P cores and 256 XMX engines. The later capacity disclosure supersedes the earlier headline rather than proving that every future SKU has 480 GB. Sampling expectations are not general availability. No unsupported memory-bandwidth or low-precision throughput figure is inferred from the core count.",
            "Crescent Island 是另一条面向推理的路线。2025 年 10 月 OCP 公告描述 160 GB LPDDR5X，并计划于 2026 年下半年向客户送样。到 Computex 和 Hot Chips 2026，Intel 披露最高 480 GB、350 W 风冷 PCIe 卡、32 个 Xe3P 核心和 256 个 XMX 引擎。后续容量披露更新了早期主要指标，并不证明所有未来 SKU 都有 480 GB。送样计划不等于正式商用，也不能仅凭核心数推算未披露的内存带宽或低精度算力。"
          ],
          "sources": [
            "E03",
            "E02",
            "E01"
          ]
        },
        {
          "id": "15.inference",
          "type": "prose",
          "text": [
            "The architectural inference is that Intel is prioritizing resident model capacity, long contexts and installation in existing air-cooled facilities. Large memory can avoid model sharding and repeated host transfers, but capacity alone does not establish token latency. Decode may remain bandwidth-bound, while prefill demands matrix throughput; concurrency changes both. LPDDR and HBM therefore occupy different design points. The meaningful test is tokens per second at a specified latency, model, context length, precision and power limit, not whether one memory capacity number exceeds an HBM GPU’s capacity.",
            "从架构上可以推断，Intel 正优先考虑模型常驻容量、长上下文，以及在既有风冷机房中的安装。大内存可以减少模型分片和反复主机传输，但容量本身不能决定 token 延迟。解码可能仍受带宽限制，预填充则需要矩阵吞吐，并发度又会改变两者。因此 LPDDR 与 HBM 对应不同设计点。有效测试应在指定延迟、模型、上下文长度、精度和功耗条件下测量每秒 token 数，而不是只比较内存容量是否超过某款 HBM GPU。"
          ],
          "sources": [
            "E01",
            "E03",
            "R01"
          ]
        },
        {
          "id": "15.client",
          "type": "prose",
          "text": [
            "Core Ultra extends the same heterogeneous-compute idea into the client and edge, combining CPU, integrated GPU and NPU. The NPU’s low-power inference role differs from a datacenter training accelerator, while Arc-derived graphics and media technology connects to the Flex lineage. OpenVINO provides an inference deployment layer across supported CPU, GPU and NPU devices. Model conversion and common APIs help portability, but device plugins, supported operators, memory limits and precision still differ. Shared branding or a common runtime must not be used to transfer server GPU bandwidth or matrix rates to a client part.",
            "Core Ultra 将异构计算思路扩展至客户端与边缘，结合 CPU、集成 GPU 和 NPU。NPU 的低功耗推理角色不同于数据中心训练加速器，而源于 Arc 的图形与媒体技术则与 Flex 谱系关联。OpenVINO 在受支持的 CPU、GPU 和 NPU 上提供推理部署层。模型转换和共同 API 有助于可移植性，但设备插件、算子覆盖、内存限制和精度仍然不同。共享品牌或运行时不能作为将服务器 GPU 带宽和矩阵算力套用到客户端产品的依据。"
          ],
          "sources": [
            "P38",
            "E01"
          ]
        }
      ]
    },
    {
      "id": "16",
      "title": [
        "Ethernet NICs, IPUs and programmable networks",
        "以太网 NIC、IPU 与可编程网络"
      ],
      "blocks": [
        {
          "id": "network",
          "type": "table",
          "table": "network"
        },
        {
          "id": "16.nic",
          "type": "prose",
          "text": [
            "Intel’s conventional Ethernet controllers evolve from E810’s 100 GbE generation toward E830 and E835 configurations reaching 200 GbE. These products support general server networking, virtualization, timing and selected RDMA capabilities. They should not be relabeled as dedicated AI collective engines merely because they can carry AI traffic. The host link, port allocation and transport configuration limit delivered bandwidth. A 200 Gb/s port is 25 GB/s in one direction before overhead; two connectors do not necessarily mean two independently available 200 Gb/s ports.",
            "Intel 常规以太网控制器从 E810 的 100 GbE 代际，发展到可达 200 GbE 的 E830 和 E835 配置。这些产品支持通用服务器网络、虚拟化、定时和部分 RDMA 能力。能够承载 AI 流量，并不意味着它们就是专门的 AI 集合通信引擎。主机接口、端口分配和传输配置共同限制实际带宽。200 Gb/s 端口在扣除开销前单方向为 25 GB/s，两个连接器也不一定代表两个可独立使用的 200 Gb/s 端口。"
          ],
          "sources": [
            "P14",
            "P15",
            "E02"
          ]
        },
        {
          "id": "16.ipu",
          "type": "prose",
          "text": [
            "The IPU is a different architectural layer. Mount Evans/E2000 introduced an ASIC infrastructure processor co-developed with Google; E2100 adapter documentation specifies a 16-core Arm Neoverse N1 complex, a P4 packet pipeline, 48 GB LPDDR4x and hardware storage/security engines. The Arm cores run infrastructure software independently of the tenant host. The offload path can terminate virtual storage and networking while preserving a separate trust and management domain. E2000 denotes the family/architectural lineage; the E2100 adapter brief explicitly names an E2100 SoC, so those labels should not be collapsed into an unsupported silicon identity claim.",
            "IPU 属于另一架构层。Mount Evans／E2000 引入与 Google 联合开发的 ASIC 基础设施处理器；E2100 适配器文档列出 16 核 Arm Neoverse N1 复合体、P4 报文流水线、48 GB LPDDR4x，以及硬件存储和安全引擎。Arm 核心独立于租户主机运行基础设施软件。卸载路径可以终结虚拟存储和网络，同时保留独立的信任与管理域。E2000 表示家族／架构谱系，而 E2100 适配器简报明确称其采用 E2100 SoC，因此不能未经证实就把这些名称合并为完全相同的芯片。"
          ],
          "sources": [
            "P10",
            "P32",
            "E15"
          ]
        },
        {
          "id": "16.google",
          "type": "prose",
          "text": [
            "Google Cloud Next 2022 connected the IPU architecture to a real service: C3 combined fourth-generation Xeon with Google’s custom Intel IPU, initially in private preview and generally available in May 2023. This is stronger deployment evidence than a generic roadmap slide. FPGA-based IPU and SmartNIC designs represent another implementation branch, trading reconfigurability for a different power, cost and software profile. Tofino’s P4-programmable switch datapath is yet another class: switching and stateful packet processing do not make it a host IPU. Intel’s discontinuation of the Tofino line limits its role to historical infrastructure and deployed systems.",
            "Google Cloud Next 2022 将 IPU 架构与实际服务连接起来：C3 搭配第四代 Xeon 和 Google 定制的 Intel IPU，先进行私有预览，再于 2023 年 5 月正式商用。这比一般路线图幻灯片更能证明实际部署。基于 FPGA 的 IPU 与 SmartNIC 是另一实现分支，以可重构性换取不同功耗、成本和软件特征。Tofino 的 P4 可编程交换数据通路又属于不同类别，交换和有状态报文处理并不使其成为主机 IPU。Intel 终止 Tofino 产品线后，它主要属于历史基础设施和既有部署。"
          ],
          "sources": [
            "E15",
            "E18",
            "P32"
          ]
        },
        {
          "id": "16.fpga",
          "type": "prose",
          "text": [
            "Architecture Day 2021 made the implementation branches explicit. Oak Springs Canyon combined Xeon D and Agilex FPGA as an IPU reference platform, while Arrow Creek became the N6000 FPGA-based acceleration development platform/SmartNIC. Mount Evans used an ASIC approach. The distinction matters when evaluating programmability: FPGA logic can change the datapath itself, whereas an ASIC packet pipeline exposes a bounded programming model and general-purpose cores handle exceptions and control. None of these names alone establishes a particular AI collective-offload capability.",
            "Architecture Day 2021 明确区分了这些实现分支。Oak Springs Canyon 将 Xeon D 与 Agilex FPGA 组合为 IPU 参考平台；Arrow Creek 则对应 N6000 基于 FPGA 的加速开发平台／SmartNIC；Mount Evans 采用 ASIC 路线。评估可编程性时，这一区别非常重要：FPGA 逻辑可以改变数据通路本身，ASIC 报文流水线则开放有边界的编程模型，通用核心处理异常与控制。这些产品名称本身都不能证明具备某种 AI 集合通信卸载能力。"
          ],
          "sources": [
            "E21",
            "P32"
          ]
        }
      ]
    },
    {
      "id": "17",
      "title": [
        "Interconnect, memory, optics and programmable logic",
        "互联、内存、光学与可编程逻辑"
      ],
      "blocks": [
        {
          "id": "links",
          "type": "table",
          "table": "links"
        },
        {
          "id": "17.cxl",
          "type": "prose",
          "text": [
            "UPI maintains CPU socket coherence, whereas PCIe is primarily an I/O transport and CXL adds defined cache and memory protocols over related physical links. Version support alone does not prove that every device type, switching configuration or pooling mode is enabled in a server. Real CXL measurements on Sapphire Rapids at MICRO 2023 show why latency, bandwidth asymmetry, placement and device implementation matter. A larger addressable memory tier is useful only if software places the right data there. The same reasoning applies to Optane: persistence requires crash-consistency mechanisms and has different read/write behavior from DRAM.",
            "UPI 维持 CPU 插槽间一致性；PCIe 主要承担 I/O 传输；CXL 则在相关物理链路上加入定义明确的缓存和内存协议。支持某版本，不证明服务器启用了所有设备类型、交换配置或池化模式。MICRO 2023 对 Sapphire Rapids 上真实 CXL 设备的测量，说明延迟、带宽不对称、数据放置与设备实现的重要性。更大的可寻址内存层只有在软件放入合适数据时才有价值。Optane 同理：持久性需要崩溃一致性机制，其读写行为也不同于 DRAM。"
          ],
          "sources": [
            "R04",
            "R05",
            "P03"
          ]
        },
        {
          "id": "17.optics",
          "type": "prose",
          "text": [
            "Intel’s OFC 2024 optical compute interconnect demonstration co-packaged an optical I/O chiplet with a CPU and carried live data. The disclosed 4 Tb/s bidirectional aggregate is 500 GB/s combined, or 250 GB/s per direction under the stated symmetric convention. Its purpose is to extend reach and improve electrical-to-optical integration as electrical package escape becomes expensive. It is a technology demonstration, not evidence that shipping Xeons already expose an optical coherent fabric. Optical I/O, Ethernet switching and memory coherence solve different layers of the system problem.",
            "Intel 在 OFC 2024 的光计算互联演示，将光 I/O 芯粒与 CPU 共封装并传输实时数据。披露的双向聚合 4 Tb/s 相当于合计 500 GB/s，在对称口径下每方向为 250 GB/s。目标是在电气封装出线代价上升时，扩大连接距离并改善电光集成。这属于技术演示，不证明已商用 Xeon 已经开放光学一致性网络。光 I/O、以太网交换和内存一致性解决的是不同系统层问题。"
          ],
          "sources": [
            "E12",
            "E13"
          ]
        },
        {
          "id": "17.altera",
          "type": "prose",
          "text": [
            "Altera’s Stratix and Agilex families bring reconfigurable datapaths, hardened interfaces and packaging experience into Intel’s historical infrastructure portfolio. FPGA acceleration is attractive when a streaming pipeline, protocol or low-latency operation can be specialized; it is not interchangeable with a general training GPU. EMIB’s role in FPGA integration also helps explain its later use in Xeon and GPU packages. Ownership changes the current portfolio boundary: the sale of 51% of Altera closed on 12 September 2025, leaving Intel with 49%. Treating Altera as a wholly owned Intel product group in 2026 would therefore be incorrect.",
            "Altera 的 Stratix 和 Agilex 家族将可重构数据通路、硬化接口和封装经验带入 Intel 的历史基础设施版图。当流式流水线、协议或低延迟操作适合专门化时，FPGA 加速具有吸引力，但它不能与通用训练 GPU 互换。EMIB 在 FPGA 集成中的作用，也有助于理解其后来在 Xeon 和 GPU 封装中的应用。所有权变化决定当前产品边界：2025 年 9 月 12 日完成出售 Altera 51% 股权，Intel 保留 49%。因此，2026 年不能再将 Altera 写成 Intel 全资产品部门。"
          ],
          "sources": [
            "E11",
            "E07",
            "C14"
          ]
        },
        {
          "id": "17.exits",
          "type": "prose",
          "text": [
            "Optane was exited in 2022; a planned future persistent-memory module should not be counted as a shipped Sapphire Rapids feature. Omni-Path belongs to Intel’s earlier HPC fabric history, while subsequent Cornelis products belong to that company’s portfolio. Loihi 2 and Hala Point are neuromorphic research systems with event-driven computation and a different programming model, not drop-in datacenter GPUs. These technologies are important context, but none should be used to inflate the count of currently supported Intel AI training platforms.",
            "Intel 于 2022 年退出 Optane；不能把规划中的后续持久内存模块算作已交付的 Sapphire Rapids 功能。Omni-Path 属于 Intel 早期 HPC 网络历史，后续 Cornelis 产品则属于该公司版图。Loihi 2 和 Hala Point 是采用事件驱动计算及不同编程模型的神经形态研究系统，并非可直接替换的数据中心 GPU。这些技术提供重要背景，但不能据此扩大当前受支持的 Intel AI 训练平台数量。"
          ],
          "sources": [
            "E17",
            "E10",
            "P33"
          ]
        }
      ]
    },
    {
      "id": "18",
      "title": [
        "Systems and software: the usable architecture",
        "系统与软件：可实际使用的架构"
      ],
      "blocks": [
        {
          "id": "systems",
          "type": "table",
          "table": "systems"
        },
        {
          "id": "18.system",
          "type": "prose",
          "text": [
            "Aurora’s two CPU Max and six GPU Max devices per node demonstrate why system ratios matter. Eight Slingshot endpoints provide scale-out connectivity, but dividing their aggregate rate by six is an average budget, not six dedicated identical NIC paths. Affinity among CPU NUMA domains, GPU tiles and network endpoints affects real communication. Likewise, an eight-Gaudi baseboard’s local fully connected graph is not an entire datacenter fabric. Oversubscription, collective scheduling and failure recovery determine cluster behavior beyond the node.",
            "Aurora 每节点两颗 CPU Max 和六颗 GPU Max，说明系统配比的重要性。八个 Slingshot 端点提供横向连接，但将总速率除以六只是平均预算，并不代表六条独立相同的 NIC 路径。CPU NUMA 域、GPU 区域与网络端点之间的亲和性会影响实际通信。同样，八 Gaudi 基板的本地全连接图并不是完整数据中心网络。超售、集合通信调度和故障恢复决定节点之外的集群行为。"
          ],
          "sources": [
            "P31",
            "P02"
          ]
        },
        {
          "id": "software",
          "type": "table",
          "table": "software"
        },
        {
          "id": "18.software",
          "type": "prose",
          "text": [
            "The software lines are related but not interchangeable. oneAPI/SYCL and Level Zero expose Intel GPU execution; Gaudi uses its own compiler/runtime and communication stack; Xeon libraries dispatch to vector or AMX kernels; IPU software manages infrastructure services. A common framework frontend does not guarantee equal operator coverage, numerical behavior or performance. Evaluate complete model graphs, fallback behavior, quantization, checkpoint portability and distributed communication. This is especially important when a hardware roadmap changes: a technically portable source program may still depend on a vendor-specific optimized kernel ecosystem.",
            "这些软件路线相互关联，但不能互换。oneAPI／SYCL 和 Level Zero 开放 Intel GPU 执行；Gaudi 使用自己的编译器、运行时和通信栈；Xeon 库分派到向量或 AMX 内核；IPU 软件管理基础设施服务。相同框架前端不保证相同算子覆盖、数值行为或性能。评估应覆盖完整模型图、回退行为、量化、检查点可移植性与分布式通信。硬件路线发生变化时，这一点尤其重要：源代码在技术上可移植，仍可能依赖厂商专用的优化内核生态。"
          ],
          "sources": [
            "P11",
            "P30",
            "P34",
            "R02"
          ]
        },
        {
          "id": "18.openvino",
          "type": "prose",
          "text": [
            "OpenVINO is the inference-oriented bridge across Intel’s CPU, GPU and NPU portfolio. It belongs alongside, rather than in place of, the lower-level compiler/runtime and mathematical libraries. For an enterprise inference deployment, supported model transformations, precision conversion, batching, device selection and profiling can matter more than the application seeing a particular instruction. Its hardware support matrix should be checked against the exact runtime release; a framework’s generic device name is not a promise that every older Intel accelerator remains supported.",
            "OpenVINO 是连接 Intel CPU、GPU 和 NPU 产品的推理部署层，与底层编译器／运行时及数学库协作，而非取代它们。企业推理部署中，受支持的模型变换、精度转换、批处理、设备选择和性能分析，可能比应用是否直接看到某条指令更重要。硬件支持矩阵必须与具体运行时版本核对；框架使用通用设备名称，不代表所有旧 Intel 加速器都仍受支持。"
          ],
          "sources": [
            "P38"
          ]
        }
      ]
    },
    {
      "id": "19",
      "title": [
        "Four system views",
        "四个时期的系统视图"
      ],
      "blocks": [
        {
          "id": "19.intro",
          "type": "prose",
          "text": [
            "These diagrams summarize actual architectural relationships across four eras. Lines identify data paths, not necessarily coherent memory. A per-device bandwidth is not multiplied by device count unless an aggregate is explicitly requested. The drawings intentionally distinguish accelerator-local memory, host memory and external networking; none represents all memory as a uniform pool.",
            "以下图示概括四个时期的架构关系。连线表示数据路径，并不必然意味着内存一致性。除非明确统计聚合值，否则不将单设备带宽乘以设备数。图中区分加速器本地内存、主机内存和外部网络，不把全部内存画成统一等速池。"
          ],
          "sources": [
            "P05",
            "P02",
            "P31",
            "E01"
          ]
        },
        {
          "id": "era1",
          "type": "figure",
          "figure": "era1"
        },
        {
          "id": "era2",
          "type": "figure",
          "figure": "era2"
        },
        {
          "id": "era3",
          "type": "figure",
          "figure": "era3"
        },
        {
          "id": "era4",
          "type": "figure",
          "figure": "era4"
        }
      ]
    },
    {
      "id": "20",
      "title": [
        "Normalized ratios and design implications",
        "归一化配比与设计含义"
      ],
      "blocks": [
        {
          "id": "ratios",
          "type": "table",
          "table": "ratios"
        },
        {
          "id": "balance",
          "type": "table",
          "table": "balance"
        },
        {
          "id": "20.analysis",
          "type": "prose",
          "text": [
            "Gaudi 3 increases matrix peak more quickly than HBM bandwidth relative to Gaudi 2: the HBM bytes available per peak BF16 operation fall by more than half on the selected whitepaper basis. More reuse, larger useful tiles or greater batching is needed to approach compute peak. Network bandwidth also remains a fraction of local HBM bandwidth. Communication-heavy parallelism cannot be judged by arithmetic scaling alone. These ratios describe resource balance; they do not predict a model benchmark without its arithmetic intensity and communication pattern.",
            "按所选白皮书口径，Gaudi 3 相比 Gaudi 2 的矩阵峰值增长快于 HBM 带宽，每个峰值 BF16 运算对应的 HBM 字节预算下降超过一半。要接近计算峰值，需要更多复用、更有效的矩阵块或更大批处理。网络带宽也仍只是本地 HBM 带宽的一部分，通信密集型并行不能只按算力增长评价。这些配比描述资源平衡；若不知道算术强度和通信模式，就无法预测模型基准成绩。"
          ],
          "sources": [
            "P02",
            "P30"
          ]
        },
        {
          "id": "20.power",
          "type": "prose",
          "text": [
            "Peak FLOPS divided by board or device power is an upper-level arithmetic normalization, not measured energy efficiency. It omits host CPUs, DIMMs, switches, optics, cooling and utilization. No cross-vendor performance-per-watt ranking is inferred from this table. For CPUs, per-core memory bandwidth is similarly an equal-share budget, not a guaranteed allocation. The useful engineering question is which layer saturates first and whether software can increase locality or overlap before more hardware is added.",
            "峰值 FLOPS 除以板级或设备功耗，只是算术能力归一化，并非实测能效。它没有计入主机 CPU、DIMM、交换机、光学、散热和利用率，因此不能据此给出跨厂商每瓦性能排名。CPU 的每核内存带宽也只是均分预算，不是保证分配量。工程上更有用的问题是：哪一层首先饱和，以及增加硬件之前，软件能否改善局部性或重叠执行。"
          ],
          "sources": [
            "P02",
            "P16",
            "P27"
          ]
        }
      ]
    },
    {
      "id": "21",
      "title": [
        "What the major architecture conferences add",
        "主要架构会议补充了什么"
      ],
      "blocks": [
        {
          "id": "21.layers",
          "type": "prose",
          "text": [
            "Hot Chips and ISSCC answer complementary questions. Hot Chips usually exposes the block diagram, hierarchy, interfaces and product intent. ISSCC can explain the physical implementation that makes those blocks practical: multi-die signaling, energy per bit, package construction, clocking and power. The strongest examples here are Sapphire Rapids’ quasi-monolithic EMIB fabric, Ponte Vecchio’s multi-process 3D integration and Emerald Rapids’ cache-rich two-tile design. Conference numbers must remain attached to their prototype, measurement condition and disclosure date before being reconciled with commercial SKU data.",
            "Hot Chips 与 ISSCC 回答互补问题。Hot Chips 通常公开框图、层次、接口和产品意图；ISSCC 则解释这些模块如何实现，包括多裸片信号、每比特能耗、封装构造、时钟和供电。本报告中最强的组合案例是 Sapphire Rapids 的准单片 EMIB 互联、Ponte Vecchio 的多工艺 3D 集成，以及 Emerald Rapids 的大缓存双芯粒设计。会议数值必须保留原型、测量条件和披露日期，再与商业 SKU 对照。"
          ],
          "sources": [
            "C03",
            "C04",
            "C12"
          ]
        },
        {
          "id": "21.research",
          "type": "prose",
          "text": [
            "ISCA, MICRO, HPCA and ASPLOS are particularly valuable for testing how product mechanisms behave. LIA at ISCA 2025 uses AMX-enabled Xeons and a GPU cooperatively, showing that CPU matrix execution can change offloading decisions. MICRO 2023’s real-device CXL study distinguishes actual memory expansion from software emulation. ASPLOS 2024’s DSA analysis identifies when asynchronous data movement pays for its submission and completion overhead. HPCA 2020’s persistent-memory keynote examines the programming consequences of capacity, persistence and asymmetric access. These are research or measurement results, not proof that Intel adopted every proposed mechanism in silicon.",
            "ISCA、MICRO、HPCA 和 ASPLOS 尤其适合检验产品机制在系统中的行为。ISCA 2025 的 LIA 协同使用支持 AMX 的 Xeon 与 GPU，说明 CPU 矩阵执行可以改变卸载决策。MICRO 2023 的真实设备 CXL 研究区分实际内存扩展和软件模拟。ASPLOS 2024 的 DSA 分析识别异步数据搬移何时能够抵消提交和完成开销。HPCA 2020 的持久内存主题演讲讨论容量、持久性和非对称访问带来的编程后果。这些属于研究或测量结果，不证明 Intel 将所有提议机制都采用到芯片中。"
          ],
          "sources": [
            "R01",
            "R04",
            "R02",
            "R05"
          ]
        },
        {
          "id": "21.coverage",
          "type": "prose",
          "text": [
            "The conference index distinguishes direct product disclosure, implementation disclosure, independent measurement, and deployment evidence. DAC and Foundry Direct Connect are useful for design enablement, packaging and EDA context; MWC emphasizes telecom and edge; OCP emphasizes platform integration; Computex and Intel’s own launch events establish product positioning and availability. Cloud Next and AWS disclosures connect chips to services. No specific GTC, Microsoft Ignite or DAC product-architecture talk is asserted where a qualifying primary record was not established in this review. That is a bounded coverage gap, not evidence that Intel never participated.",
            "会议索引区分直接产品披露、实现披露、独立测量和部署证据。DAC 与 Foundry Direct Connect 对设计使能、封装和 EDA 背景有价值；MWC 强调电信和边缘；OCP 强调平台集成；Computex 和 Intel 自身发布活动用于确认产品定位与供应。Cloud Next 与 AWS 公告将芯片连接到云服务。本次未建立合格一手记录的 GTC、Microsoft Ignite 或 DAC 产品架构演讲，不在报告中虚构具体条目。这是本次覆盖的边界，并不意味着 Intel 从未参加这些活动。"
          ],
          "sources": [
            "E15",
            "E14",
            "E16",
            "E03",
            "E02",
            "E19"
          ]
        },
        {
          "id": "conferences",
          "type": "table",
          "table": "conferences"
        }
      ]
    },
    {
      "id": "22",
      "title": [
        "Architecture conclusions and remaining gaps",
        "架构结论与剩余缺口"
      ],
      "blocks": [
        {
          "id": "22.conclusion",
          "type": "prose",
          "text": [
            "Intel’s durable architectural assets are the CPU software base, increasingly specialized host execution, heterogeneous packaging, and infrastructure offload. Its accelerator history is more fragmented. Gaudi offers a distinctive Ethernet-centered system; GPU Max demonstrates ambitious HPC integration; Crescent Island pursues capacity-oriented inference economics. These are complementary design points, not interchangeable generations of one GPU. The correct unit of comparison is the deployable workload system: compute format, memory residence, locality, fabric, power envelope and maintained software path.",
            "Intel 持续积累的架构资产包括 CPU 软件基础、日益专门化的主机执行、异构封装和基础设施卸载。加速器历史则更为分散。Gaudi 提供具有特色的以太网系统，GPU Max 展示复杂的 HPC 集成，Crescent Island 追求容量导向的推理经济性。这些是互补设计点，而非同一 GPU 的可互换代际。正确比较单位是可部署的工作负载系统：计算格式、内存常驻、局部性、网络、功耗范围以及持续维护的软件路径。"
          ],
          "sources": [
            "P02",
            "P03",
            "P10",
            "E01"
          ]
        },
        {
          "id": "22.gaps",
          "type": "prose",
          "text": [
            "The remaining material gaps are concentrated in final Diamond Rapids SKU and availability details, Crescent Island’s memory bandwidth and arithmetic rates, the precise shipping configuration matrix of newer NICs, and restricted conference slide or full-paper access. The report therefore uses official announcement-level claims for those products and leaves unsupported fields as n/d. Earlier packaging roadmaps are reconciled with later launch records rather than treated as actual shipment dates. The canonical data file preserves source IDs, claim scope, numerical basis and product status so these gaps can be updated without changing the report structure.",
            "剩余重要缺口集中在 Diamond Rapids 最终 SKU 与商用细节、Crescent Island 的内存带宽和算力、新 NIC 的具体商用配置矩阵，以及部分会议幻灯片或论文全文访问。相关产品因此采用官方公告层面的事实，未获支持的字段保留 n/d。早期封装路线图与后续发布记录进行对照，而不把计划时间当作实际出货日期。配套规范数据文件保留来源编号、事实范围、数值口径和产品状态，便于沿用报告结构更新这些缺口。"
          ],
          "sources": [
            "E01",
            "E02",
            "E03",
            "P14",
            "E07"
          ]
        }
      ]
    }
  ],
  "tables": {
    "portfolio": {
      "id": "portfolio",
      "title": [
        "Portfolio map at the cutoff",
        "截止日期的产品版图"
      ],
      "headers": [
        [
          "Layer",
          "层次"
        ],
        [
          "Families",
          "产品线"
        ],
        [
          "Architectural role",
          "架构角色"
        ],
        [
          "Status boundary",
          "状态边界"
        ]
      ],
      "rows": [
        {
          "id": "cpu",
          "values": [
            [
              "Host compute",
              "主机计算"
            ],
            [
              "Xeon Scalable / Xeon 6 / 6+",
              "Xeon Scalable / Xeon 6 / 6+"
            ],
            [
              "General compute, AMX, orchestration",
              "通用计算、AMX、编排"
            ],
            [
              "Diamond Rapids disclosed; GA not established",
              "Diamond Rapids 已披露；GA 未确定"
            ]
          ],
          "sources": [
            "E01",
            "E02",
            "P03"
          ]
        },
        {
          "id": "accelerator",
          "values": [
            [
              "Accelerators",
              "加速器"
            ],
            [
              "Gaudi / GPU Max / Flex / Crescent Island",
              "Gaudi / GPU Max / Flex / Crescent Island"
            ],
            [
              "Training, HPC, media and inference",
              "训练、HPC、媒体与推理"
            ],
            [
              "Crescent Island announced; Falcon Shores internal only",
              "Crescent Island 已公布；Falcon Shores 仅内部使用"
            ]
          ],
          "sources": [
            "P02",
            "C03",
            "E01",
            "E17"
          ]
        },
        {
          "id": "network",
          "values": [
            [
              "Network / infrastructure",
              "网络／基础设施"
            ],
            [
              "E810 / E830 / E835; IPU E2000/E2100",
              "E810 / E830 / E835; IPU E2000/E2100"
            ],
            [
              "RDMA, packet processing, storage isolation",
              "RDMA、报文处理、存储隔离"
            ],
            [
              "NIC and IPU are different device classes",
              "NIC 与 IPU 属于不同设备类别"
            ]
          ],
          "sources": [
            "P10",
            "P14",
            "E02"
          ]
        },
        {
          "id": "adjacent",
          "values": [
            [
              "Adjacent technology",
              "邻接技术"
            ],
            [
              "EMIB / Foveros / OCI / Altera / Optane",
              "EMIB / Foveros / OCI / Altera / Optane"
            ],
            [
              "Integration, optical links, programmable logic, memory",
              "集成、光链路、可编程逻辑、内存"
            ],
            [
              "OCI demonstration; Altera 49% retained; Optane exited",
              "OCI 为演示；保留 Altera 49% 股权；Optane 已退出"
            ]
          ],
          "sources": [
            "E11",
            "E12",
            "E17"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "cpu": {
      "id": "cpu",
      "title": [
        "CPU reference configurations",
        "CPU 参考配置"
      ],
      "headers": [
        [
          "Generation / reference SKU",
          "代际／参考 SKU"
        ],
        [
          "Codename",
          "代号"
        ],
        [
          "GA",
          "正式商用"
        ],
        [
          "Status",
          "状态"
        ],
        [
          "Core µarch",
          "核心微架构"
        ],
        [
          "Cores / threads",
          "核心／线程"
        ],
        [
          "Process per die",
          "各裸片工艺"
        ],
        [
          "Dies / packaging",
          "裸片／封装"
        ],
        [
          "L2 per core",
          "每核 L2"
        ],
        [
          "L3 / domain",
          "L3／共享域"
        ],
        [
          "Memory: channels; rate; GB/s",
          "内存：通道；速率；GB/s"
        ],
        [
          "Sockets / links",
          "插槽／互联"
        ],
        [
          "PCIe / CXL",
          "PCIe／CXL"
        ],
        [
          "TDP",
          "TDP"
        ],
        [
          "Vector / matrix ISA",
          "向量／矩阵 ISA"
        ]
      ],
      "rows": [
        {
          "id": "bdw",
          "values": [
            [
              "E5 v4 / 2699 v4",
              "E5 v4 / 2699 v4"
            ],
            [
              "Broadwell-EP",
              "Broadwell-EP"
            ],
            [
              "2016",
              "2016"
            ],
            [
              "Historical shipping",
              "历史已商用"
            ],
            [
              "Broadwell",
              "Broadwell"
            ],
            [
              "22 / 44",
              "22 / 44"
            ],
            [
              "14 nm",
              "14 nm"
            ],
            [
              "Monolithic; ring",
              "单裸片；环形"
            ],
            [
              "256 KB",
              "256 KB"
            ],
            [
              "55 MB inclusive",
              "55 MB 包含式"
            ],
            [
              "DDR4; 4; 2400; 76.8",
              "DDR4; 4; 2400; 76.8"
            ],
            [
              "2S; QPI 9.6 GT/s",
              "2S; QPI 9.6 GT/s"
            ],
            [
              "40 PCIe 3; CXL n/a",
              "40 PCIe 3; CXL n/a"
            ],
            [
              "145 W",
              "145 W"
            ],
            [
              "AVX2",
              "AVX2"
            ]
          ],
          "sources": [
            "P05",
            "P20"
          ]
        },
        {
          "id": "skl",
          "values": [
            [
              "1st / 8180",
              "1st / 8180"
            ],
            [
              "Skylake-SP",
              "Skylake-SP"
            ],
            [
              "2017",
              "2017"
            ],
            [
              "Historical shipping",
              "历史已商用"
            ],
            [
              "Skylake",
              "Skylake"
            ],
            [
              "28 / 56",
              "28 / 56"
            ],
            [
              "14 nm",
              "14 nm"
            ],
            [
              "Monolithic; mesh",
              "单裸片；网格"
            ],
            [
              "1 MB",
              "1 MB"
            ],
            [
              "38.5 MB non-inclusive",
              "38.5 MB 非包含式"
            ],
            [
              "DDR4; 6; 2666; ~128",
              "DDR4; 6; 2666; ~128"
            ],
            [
              "2/4/8S; 3 UPI 10.4 GT/s",
              "2/4/8S; 3 UPI 10.4 GT/s"
            ],
            [
              "48 PCIe 3; CXL n/a",
              "48 PCIe 3; CXL n/a"
            ],
            [
              "205 W",
              "205 W"
            ],
            [
              "AVX-512",
              "AVX-512"
            ]
          ],
          "sources": [
            "P05",
            "P06",
            "P21"
          ]
        },
        {
          "id": "clx",
          "values": [
            [
              "2nd / 8280",
              "2nd / 8280"
            ],
            [
              "Cascade Lake",
              "Cascade Lake"
            ],
            [
              "2019",
              "2019"
            ],
            [
              "Historical shipping",
              "历史已商用"
            ],
            [
              "Skylake-derived",
              "Skylake 衍生"
            ],
            [
              "28 / 56",
              "28 / 56"
            ],
            [
              "14 nm",
              "14 nm"
            ],
            [
              "Monolithic; mesh",
              "单裸片；网格"
            ],
            [
              "1 MB",
              "1 MB"
            ],
            [
              "38.5 MB",
              "38.5 MB"
            ],
            [
              "DDR4; 6; 2933; ~140.8",
              "DDR4; 6; 2933; ~140.8"
            ],
            [
              "2/4/8S; 3 UPI 10.4 GT/s",
              "2/4/8S; 3 UPI 10.4 GT/s"
            ],
            [
              "48 PCIe 3; CXL n/a",
              "48 PCIe 3; CXL n/a"
            ],
            [
              "205 W",
              "205 W"
            ],
            [
              "AVX-512; VNNI",
              "AVX-512; VNNI"
            ]
          ],
          "sources": [
            "P05",
            "C06",
            "P22"
          ]
        },
        {
          "id": "cpx",
          "values": [
            [
              "3rd / 8380HL",
              "3rd / 8380HL"
            ],
            [
              "Cooper Lake",
              "Cooper Lake"
            ],
            [
              "2020",
              "2020"
            ],
            [
              "Historical shipping",
              "历史已商用"
            ],
            [
              "Skylake-derived",
              "Skylake 衍生"
            ],
            [
              "28 / 56",
              "28 / 56"
            ],
            [
              "14 nm",
              "14 nm"
            ],
            [
              "Monolithic; scale-up",
              "单裸片；多路扩展"
            ],
            [
              "1 MB",
              "1 MB"
            ],
            [
              "38.5 MB",
              "38.5 MB"
            ],
            [
              "DDR4; 6; 3200; 153.6",
              "DDR4; 6; 3200; 153.6"
            ],
            [
              "4/8S; 6 UPI 10.4 GT/s",
              "4/8S; 6 UPI 10.4 GT/s"
            ],
            [
              "48 PCIe 3; CXL n/a",
              "48 PCIe 3; CXL n/a"
            ],
            [
              "250 W",
              "250 W"
            ],
            [
              "AVX-512; BF16; VNNI",
              "AVX-512; BF16; VNNI"
            ]
          ],
          "sources": [
            "P05",
            "P23"
          ]
        },
        {
          "id": "icl",
          "values": [
            [
              "3rd / 8380",
              "3rd / 8380"
            ],
            [
              "Ice Lake-SP",
              "Ice Lake-SP"
            ],
            [
              "2021",
              "2021"
            ],
            [
              "Historical shipping",
              "历史已商用"
            ],
            [
              "Sunny Cove",
              "Sunny Cove"
            ],
            [
              "40 / 80",
              "40 / 80"
            ],
            [
              "10 nm",
              "10 nm"
            ],
            [
              "Monolithic; mesh",
              "单裸片；网格"
            ],
            [
              "1.25 MB",
              "1.25 MB"
            ],
            [
              "60 MB",
              "60 MB"
            ],
            [
              "DDR4; 8; 3200; 204.8",
              "DDR4; 8; 3200; 204.8"
            ],
            [
              "2S; 3 UPI 11.2 GT/s",
              "2S; 3 UPI 11.2 GT/s"
            ],
            [
              "64 PCIe 4; CXL n/a",
              "64 PCIe 4; CXL n/a"
            ],
            [
              "270 W",
              "270 W"
            ],
            [
              "AVX-512; VNNI",
              "AVX-512; VNNI"
            ]
          ],
          "sources": [
            "P05",
            "P24"
          ]
        },
        {
          "id": "spr",
          "values": [
            [
              "4th / 8490H",
              "4th / 8490H"
            ],
            [
              "Sapphire Rapids",
              "Sapphire Rapids"
            ],
            [
              "2023",
              "2023"
            ],
            [
              "Historical shipping",
              "历史已商用"
            ],
            [
              "Golden Cove",
              "Golden Cove"
            ],
            [
              "60 / 120",
              "60 / 120"
            ],
            [
              "Intel 7",
              "Intel 7"
            ],
            [
              "4 compute tiles; EMIB",
              "4 个计算芯粒；EMIB"
            ],
            [
              "2 MB",
              "2 MB"
            ],
            [
              "112.5 MB",
              "112.5 MB"
            ],
            [
              "DDR5; 8; 4800; 307.2",
              "DDR5; 8; 4800; 307.2"
            ],
            [
              "up to 8S; 4 UPI 16 GT/s",
              "up to 8S; 4 UPI 16 GT/s"
            ],
            [
              "80 PCIe 5; CXL 1.1",
              "80 PCIe 5; CXL 1.1"
            ],
            [
              "350 W",
              "350 W"
            ],
            [
              "AVX-512; AMX INT8/BF16",
              "AVX-512; AMX INT8/BF16"
            ]
          ],
          "sources": [
            "P03",
            "P25",
            "C03"
          ]
        },
        {
          "id": "max",
          "values": [
            [
              "Xeon Max / 9480",
              "Xeon Max / 9480"
            ],
            [
              "Sapphire Rapids HBM",
              "Sapphire Rapids HBM"
            ],
            [
              "2023",
              "2023"
            ],
            [
              "Historical shipping",
              "历史已商用"
            ],
            [
              "Golden Cove",
              "Golden Cove"
            ],
            [
              "56 / 112",
              "56 / 112"
            ],
            [
              "Intel 7",
              "Intel 7"
            ],
            [
              "4 tiles + 4 HBM stacks; EMIB",
              "4 芯粒＋4 HBM 堆栈；EMIB"
            ],
            [
              "2 MB",
              "2 MB"
            ],
            [
              "112.5 MB",
              "112.5 MB"
            ],
            [
              "DDR5; 8; 4800; 307.2 + HBM2e 64 GB ~1000",
              "DDR5; 8; 4800; 307.2 + HBM2e 64 GB ~1000"
            ],
            [
              "2S; UPI 16 GT/s",
              "2S; UPI 16 GT/s"
            ],
            [
              "80 PCIe 5; CXL 1.1",
              "80 PCIe 5; CXL 1.1"
            ],
            [
              "350 W",
              "350 W"
            ],
            [
              "AVX-512; AMX INT8/BF16",
              "AVX-512; AMX INT8/BF16"
            ]
          ],
          "sources": [
            "P13",
            "P03"
          ]
        },
        {
          "id": "emr",
          "values": [
            [
              "5th / 8592+",
              "5th / 8592+"
            ],
            [
              "Emerald Rapids",
              "Emerald Rapids"
            ],
            [
              "2023-12",
              "2023-12"
            ],
            [
              "Historical shipping",
              "历史已商用"
            ],
            [
              "Raptor Cove",
              "Raptor Cove"
            ],
            [
              "64 / 128",
              "64 / 128"
            ],
            [
              "Intel 7",
              "Intel 7"
            ],
            [
              "2 tiles high-end; EMIB",
              "高端为 2 芯粒；EMIB"
            ],
            [
              "2 MB",
              "2 MB"
            ],
            [
              "320 MB",
              "320 MB"
            ],
            [
              "DDR5; 8; 5600; 358.4",
              "DDR5; 8; 5600; 358.4"
            ],
            [
              "2S; 4 UPI 20 GT/s",
              "2S; 4 UPI 20 GT/s"
            ],
            [
              "80 PCIe 5; CXL 1.1",
              "80 PCIe 5; CXL 1.1"
            ],
            [
              "350 W",
              "350 W"
            ],
            [
              "AVX-512; AMX INT8/BF16",
              "AVX-512; AMX INT8/BF16"
            ]
          ],
          "sources": [
            "C04",
            "P26"
          ]
        },
        {
          "id": "srf",
          "values": [
            [
              "6 E / 6780E",
              "6 E / 6780E"
            ],
            [
              "Sierra Forest",
              "Sierra Forest"
            ],
            [
              "2024-06",
              "2024-06"
            ],
            [
              "Shipping",
              "已商用"
            ],
            [
              "Crestmont",
              "Crestmont"
            ],
            [
              "144 / 144",
              "144 / 144"
            ],
            [
              "Intel 3 + Intel 7 I/O",
              "Intel 3 + Intel 7 I/O"
            ],
            [
              "Compute + 2 I/O; EMIB",
              "计算芯粒＋2 I/O；EMIB"
            ],
            [
              "4 MB / 4-core cluster",
              "4 MB／4 核簇"
            ],
            [
              "108 MB",
              "108 MB"
            ],
            [
              "DDR5; 8; 6400; 409.6",
              "DDR5; 8; 6400; 409.6"
            ],
            [
              "2S; UPI 24 GT/s",
              "2S; UPI 24 GT/s"
            ],
            [
              "88 PCIe 5; CXL 2.0; shared lane budget",
              "88 PCIe 5；CXL 2.0；共享通道预算"
            ],
            [
              "330 W",
              "330 W"
            ],
            [
              "AVX2; VNNI; no AMX",
              "AVX2; VNNI; 无 AMX"
            ]
          ],
          "sources": [
            "P17",
            "C12"
          ]
        },
        {
          "id": "gnr",
          "values": [
            [
              "6 P / 6980P",
              "6 P / 6980P"
            ],
            [
              "Granite Rapids",
              "Granite Rapids"
            ],
            [
              "2024-09",
              "2024-09"
            ],
            [
              "Shipping",
              "已商用"
            ],
            [
              "Redwood Cove",
              "Redwood Cove"
            ],
            [
              "128 / 256",
              "128 / 256"
            ],
            [
              "Intel 3 + Intel 7 I/O",
              "Intel 3 + Intel 7 I/O"
            ],
            [
              "3 compute + 2 I/O; EMIB",
              "3 计算＋2 I/O；EMIB"
            ],
            [
              "2 MB",
              "2 MB"
            ],
            [
              "504 MB",
              "504 MB"
            ],
            [
              "DDR5; 12; 6400; 614.4 / MRDIMM 8800; 844.8",
              "DDR5; 12; 6400; 614.4 / MRDIMM 8800; 844.8"
            ],
            [
              "2S; UPI 24 GT/s",
              "2S; UPI 24 GT/s"
            ],
            [
              "96 PCIe 5; CXL 2.0",
              "96 PCIe 5; CXL 2.0"
            ],
            [
              "500 W",
              "500 W"
            ],
            [
              "AVX-512; AMX INT8/BF16/FP16",
              "AVX-512; AMX INT8/BF16/FP16"
            ]
          ],
          "sources": [
            "P16",
            "P18",
            "C12"
          ]
        },
        {
          "id": "cwf",
          "values": [
            [
              "6+ / 6990E+",
              "6+ / 6990E+"
            ],
            [
              "Clearwater Forest",
              "Clearwater Forest"
            ],
            [
              "2026-06",
              "2026-06"
            ],
            [
              "Shipping",
              "已商用"
            ],
            [
              "Darkmont",
              "Darkmont"
            ],
            [
              "288 / 288",
              "288 / 288"
            ],
            [
              "Intel 18A compute; Intel 3 base; Intel 7 I/O",
              "Intel 18A 计算; Intel 3 基底; Intel 7 I/O"
            ],
            [
              "12 compute + 3 base + 2 I/O; 3D + EMIB",
              "12 计算＋3 基底＋2 I/O；3D＋EMIB"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "576 MB",
              "576 MB"
            ],
            [
              "DDR5; 12; 8000; 768",
              "DDR5; 12; 8000; 768"
            ],
            [
              "2S; link details n/d",
              "2S; 链路细节 n/d"
            ],
            [
              "96 PCIe 5; CXL allocation n/d",
              "96 PCIe 5; CXL 分配 n/d"
            ],
            [
              "450 W",
              "450 W"
            ],
            [
              "AVX2; no AMX",
              "AVX2; 无 AMX"
            ]
          ],
          "sources": [
            "P01",
            "P19",
            "E02",
            "E16",
            "P08",
            "P35"
          ]
        },
        {
          "id": "dmr",
          "values": [
            [
              "Next Xeon",
              "下一代 Xeon"
            ],
            [
              "Diamond Rapids",
              "Diamond Rapids"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Disclosed; GA n/d",
              "已披露；GA n/d"
            ],
            [
              "New performance core",
              "新性能核"
            ],
            [
              "256 / n/d",
              "256 / n/d"
            ],
            [
              "Intel 18A-P",
              "Intel 18A-P"
            ],
            [
              "Foveros Direct 3D; UCIe-S",
              "Foveros Direct 3D；UCIe-S"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "1.28 GB",
              "1.28 GB"
            ],
            [
              "16; 12800 MT/s; 1638.4 derived",
              "16; 12800 MT/s; 1638.4 推导值"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "128 PCIe 6; CXL 3.0",
              "128 PCIe 6; CXL 3.0"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "APX; enhanced AMX",
              "APX; 增强 AMX"
            ]
          ],
          "sources": [
            "E01"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3,
          4,
          5
        ],
        [
          0,
          6,
          7,
          8,
          9
        ],
        [
          0,
          10,
          11,
          12,
          13,
          14
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "accelerators": {
      "id": "accelerators",
      "title": [
        "Accelerator reference configurations",
        "加速器参考配置"
      ],
      "headers": [
        [
          "Product",
          "产品"
        ],
        [
          "Architecture",
          "架构"
        ],
        [
          "GA / milestone",
          "商用／里程碑"
        ],
        [
          "Status",
          "状态"
        ],
        [
          "Process",
          "工艺"
        ],
        [
          "Dies / packaging",
          "裸片／封装"
        ],
        [
          "Compute units",
          "计算单元"
        ],
        [
          "Dense BF16",
          "稠密 BF16"
        ],
        [
          "Dense FP8",
          "稠密 FP8"
        ],
        [
          "Dense FP6 / FP4",
          "稠密 FP6／FP4"
        ],
        [
          "FP64 vector / matrix",
          "FP64 向量／矩阵"
        ],
        [
          "Memory: type; stacks; GB; TB/s",
          "内存：类型；堆栈；GB；TB/s"
        ],
        [
          "LLC / SRAM",
          "末级缓存／SRAM"
        ],
        [
          "Scale-up: links; GB/s per direction; domain",
          "纵向扩展：链路；单向 GB/s；域"
        ],
        [
          "Host link",
          "主机连接"
        ],
        [
          "Power / cooling",
          "功耗／散热"
        ],
        [
          "Form factor",
          "形态"
        ]
      ],
      "rows": [
        {
          "id": "knl",
          "values": [
            [
              "Xeon Phi 7290",
              "Xeon Phi 7290"
            ],
            [
              "Knights Landing",
              "Knights Landing"
            ],
            [
              "2016",
              "2016"
            ],
            [
              "Historical shipping",
              "历史已商用"
            ],
            [
              "14 nm",
              "14 nm"
            ],
            [
              "CPU + on-package MCDRAM",
              "CPU＋封装内 MCDRAM"
            ],
            [
              "72 cores / 288 threads",
              "72 核心 / 288 线程"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "~3.46 TF / n/a",
              "~3.46 TF / n/a"
            ],
            [
              "MCDRAM; 8; 16; >0.4 measured STREAM; DDR4 separate",
              "MCDRAM；8；16；STREAM 实测 >0.4；另有 DDR4"
            ],
            [
              "36 MB distributed L2",
              "36 MB 分布式 L2"
            ],
            [
              "n/a; optional Omni-Path fabric",
              "n/a；可选 Omni-Path 网络"
            ],
            [
              "Self-hosted; PCIe 3",
              "自启动；PCIe 3"
            ],
            [
              "245 W",
              "245 W"
            ],
            [
              "Socketed processor",
              "插槽处理器"
            ]
          ],
          "sources": [
            "P28",
            "P05",
            "C13"
          ]
        },
        {
          "id": "gaudi1",
          "values": [
            [
              "Gaudi / HL-205",
              "Gaudi / HL-205"
            ],
            [
              "Gaudi",
              "Gaudi"
            ],
            [
              "2021 AWS DL1",
              "2021 AWS DL1"
            ],
            [
              "Historical shipping",
              "历史已商用"
            ],
            [
              "16 nm",
              "16 nm"
            ],
            [
              "1 compute die + HBM",
              "1 计算裸片＋HBM"
            ],
            [
              "8 TPC; MME",
              "8 TPC; MME"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "HBM2; n/d; 32; ~1",
              "HBM2；n/d；32；约 1"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "10 x 100GbE; 125 total; 8-device server",
              "10×100GbE；合计 125；8 芯片服务器"
            ],
            [
              "PCIe 4",
              "PCIe 4"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "OAM",
              "OAM"
            ]
          ],
          "sources": [
            "E14",
            "P30",
            "P37"
          ]
        },
        {
          "id": "gaudi2",
          "values": [
            [
              "Gaudi 2",
              "Gaudi 2"
            ],
            [
              "Gaudi 2",
              "Gaudi 2"
            ],
            [
              "2022",
              "2022"
            ],
            [
              "Historical shipping",
              "历史已商用"
            ],
            [
              "7 nm",
              "7 nm"
            ],
            [
              "1 compute die + HBM",
              "1 计算裸片＋HBM"
            ],
            [
              "24 TPC / 2 MME",
              "24 TPC / 2 MME"
            ],
            [
              "432 TF",
              "432 TF"
            ],
            [
              "865 TF",
              "865 TF"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "HBM2e; 6; 96; 2.46",
              "HBM2e; 6; 96; 2.46"
            ],
            [
              "48 MB SRAM",
              "48 MB SRAM"
            ],
            [
              "24 x 100GbE; 300 total; 8-device server",
              "24×100GbE；合计 300；8 芯片服务器"
            ],
            [
              "PCIe 4 x16",
              "PCIe 4 x16"
            ],
            [
              "600 W",
              "600 W"
            ],
            [
              "OAM",
              "OAM"
            ]
          ],
          "sources": [
            "P02",
            "P30",
            "P37"
          ]
        },
        {
          "id": "gaudi3",
          "values": [
            [
              "Gaudi 3 / HL-325L",
              "Gaudi 3 / HL-325L"
            ],
            [
              "Gaudi 3",
              "Gaudi 3"
            ],
            [
              "2024",
              "2024"
            ],
            [
              "Shipping",
              "已商用"
            ],
            [
              "5 nm",
              "5 nm"
            ],
            [
              "2 compute dies + HBM",
              "2 计算裸片＋HBM"
            ],
            [
              "64 TPC / 8 MME",
              "64 TPC / 8 MME"
            ],
            [
              "1678 TF",
              "1678 TF"
            ],
            [
              "1678 TF",
              "1678 TF"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "HBM2e; 8; 128; 3.7",
              "HBM2e; 8; 128; 3.7"
            ],
            [
              "96 MB SRAM",
              "96 MB SRAM"
            ],
            [
              "24 x 200GbE; 600 total; 8-device server",
              "24×200GbE；合计 600；8 芯片服务器"
            ],
            [
              "PCIe 5 x16",
              "PCIe 5 x16"
            ],
            [
              "Up to 900 W; air/liquid variants",
              "最高 900 W；风冷／液冷变体"
            ],
            [
              "OAM",
              "OAM"
            ]
          ],
          "sources": [
            "P02",
            "E05"
          ]
        },
        {
          "id": "pvc",
          "values": [
            [
              "GPU Max 1550",
              "GPU Max 1550"
            ],
            [
              "Ponte Vecchio / Xe-HPC",
              "Ponte Vecchio / Xe-HPC"
            ],
            [
              "2023",
              "2023"
            ],
            [
              "Historical shipping",
              "历史已商用"
            ],
            [
              "TSMC N5 compute; Intel 7 base; TSMC N7 link",
              "TSMC N5 计算; Intel 7 基底; TSMC N7 link"
            ],
            [
              "47-tile integration; EMIB + Foveros",
              "47 芯粒集成；EMIB＋Foveros"
            ],
            [
              "128 Xe cores / 1024 XMX",
              "128 Xe 核心 / 1024 XMX"
            ],
            [
              "839 TF",
              "839 TF"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "52 TF native; split n/d",
              "原生 52 TF；拆分 n/d"
            ],
            [
              "HBM2e; 8; 128; 3.2",
              "HBM2e; 8; 128; 3.2"
            ],
            [
              "408 MB L2",
              "408 MB L2"
            ],
            [
              "Xe Link; 318 on Lenovo reference; 4-GPU domain",
              "Xe Link；Lenovo 参考配置 318；4 GPU 域"
            ],
            [
              "PCIe 5 x16",
              "PCIe 5 x16"
            ],
            [
              "600 W; platform-dependent",
              "600 W；依平台"
            ],
            [
              "OAM",
              "OAM"
            ]
          ],
          "sources": [
            "C03",
            "P27",
            "P11"
          ]
        },
        {
          "id": "flex",
          "values": [
            [
              "GPU Flex 170",
              "GPU Flex 170"
            ],
            [
              "Xe-HPG",
              "Xe-HPG"
            ],
            [
              "2022",
              "2022"
            ],
            [
              "Historical shipping",
              "历史已商用"
            ],
            [
              "TSMC N6",
              "TSMC N6"
            ],
            [
              "Single GPU",
              "单 GPU"
            ],
            [
              "32 Xe cores",
              "32 Xe 核心"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "GDDR6; n/a; 16; 0.576",
              "GDDR6；n/a；16；0.576"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "PCIe 4 x16",
              "PCIe 4 x16"
            ],
            [
              "150 W; passive air",
              "150 W；被动风冷"
            ],
            [
              "PCIe",
              "PCIe"
            ]
          ],
          "sources": [
            "P29",
            "P11"
          ]
        },
        {
          "id": "crescent",
          "values": [
            [
              "Crescent Island",
              "Crescent Island"
            ],
            [
              "Xe3P",
              "Xe3P"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Disclosed; GA n/d",
              "已披露；GA n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "32 Xe cores / 256 XMX",
              "32 Xe 核心 / 256 XMX"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "LPDDR5X; n/a; up to 480; n/d",
              "LPDDR5X；n/a；最高 480；n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "PCIe; generation n/d",
              "PCIe; 代际 n/d"
            ],
            [
              "350 W; air",
              "350 W；风冷"
            ],
            [
              "PCIe",
              "PCIe"
            ]
          ],
          "sources": [
            "E01",
            "E03"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3,
          4,
          5
        ],
        [
          0,
          6,
          7,
          8,
          9,
          10
        ],
        [
          0,
          11,
          12,
          13
        ],
        [
          0,
          14,
          15,
          16
        ]
      ],
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF"
    },
    "network": {
      "id": "network",
      "title": [
        "Network and infrastructure devices",
        "网络与基础设施设备"
      ],
      "headers": [
        [
          "Product",
          "产品"
        ],
        [
          "GA / milestone",
          "商用／里程碑"
        ],
        [
          "Status",
          "状态"
        ],
        [
          "Class",
          "类别"
        ],
        [
          "Ports × speed",
          "端口×速率"
        ],
        [
          "SerDes",
          "SerDes"
        ],
        [
          "Host interface",
          "主机接口"
        ],
        [
          "Programmable engine",
          "可编程引擎"
        ],
        [
          "Embedded CPU",
          "嵌入式 CPU"
        ],
        [
          "On-card memory",
          "板载内存"
        ],
        [
          "Transport / RDMA",
          "传输／RDMA"
        ],
        [
          "Congestion control",
          "拥塞控制"
        ],
        [
          "Key offloads",
          "主要卸载"
        ],
        [
          "Power",
          "功耗"
        ]
      ],
      "rows": [
        {
          "id": "e810",
          "values": [
            [
              "E810",
              "E810"
            ],
            [
              "2019",
              "2019"
            ],
            [
              "Historical shipping",
              "历史已商用"
            ],
            [
              "Ethernet NIC",
              "Ethernet NIC"
            ],
            [
              "Up to 100GbE; card-dependent",
              "最高 100GbE；依板卡"
            ],
            [
              "25G NRZ",
              "25G NRZ"
            ],
            [
              "PCIe 4",
              "PCIe 4"
            ],
            [
              "DDP pipeline profiles",
              "DDP 流水线配置"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "iWARP / RoCEv2",
              "iWARP / RoCEv2"
            ],
            [
              "Protocol / driver-dependent",
              "依协议／驱动"
            ],
            [
              "Virtualization, RSS, timing",
              "虚拟化、RSS、定时"
            ],
            [
              "n/d",
              "n/d"
            ]
          ],
          "sources": [
            "P14"
          ]
        },
        {
          "id": "e830",
          "values": [
            [
              "E830-CQDA2",
              "E830-CQDA2"
            ],
            [
              "2025",
              "2025"
            ],
            [
              "Shipping",
              "已商用"
            ],
            [
              "Ethernet NIC",
              "Ethernet NIC"
            ],
            [
              "2 x 100GbE",
              "2 x 100GbE"
            ],
            [
              "50G PAM4",
              "50G PAM4"
            ],
            [
              "PCIe 5 x8 / PCIe 4 x16",
              "PCIe 5 x8 / PCIe 4 x16"
            ],
            [
              "DDP / packet classification",
              "DDP／报文分类"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Ethernet; RDMA SKU-dependent",
              "Ethernet; RDMA 依 SKU"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Packet processing, timing, telemetry",
              "报文处理、定时、遥测"
            ],
            [
              "n/d",
              "n/d"
            ]
          ],
          "sources": [
            "P15",
            "P14"
          ]
        },
        {
          "id": "e835",
          "values": [
            [
              "E835",
              "E835"
            ],
            [
              "2026-06",
              "2026-06"
            ],
            [
              "Shipping",
              "已商用"
            ],
            [
              "Ethernet NIC",
              "Ethernet NIC"
            ],
            [
              "1 x 200 / 2 x 100GbE; variants",
              "1×200／2×100GbE；多个变体"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Configurable ports / packet processing",
              "可配置端口／报文处理"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "iWARP + RoCEv2",
              "iWARP + RoCEv2"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "RDMA, timing, security",
              "RDMA、定时、安全"
            ],
            [
              "n/d",
              "n/d"
            ]
          ],
          "sources": [
            "E02",
            "P14"
          ]
        },
        {
          "id": "ipu",
          "values": [
            [
              "IPU E2100-CCQDA2",
              "IPU E2100-CCQDA2"
            ],
            [
              "2023–2024 documentation",
              "2023–2024 文档"
            ],
            [
              "Shipping",
              "已商用"
            ],
            [
              "ASIC IPU",
              "ASIC IPU"
            ],
            [
              "1 x 200 / 2 x 100GbE",
              "1 x 200 / 2 x 100GbE"
            ],
            [
              "50G PAM4 / 25G NRZ",
              "50G PAM4 / 25G NRZ"
            ],
            [
              "PCIe 4 x16",
              "PCIe 4 x16"
            ],
            [
              "P4 pipeline",
              "P4 pipeline"
            ],
            [
              "16 Arm Neoverse N1",
              "16 Arm Neoverse N1"
            ],
            [
              "48 GB LPDDR4x; 32 MB SLC",
              "48 GB LPDDR4x; 32 MB SLC"
            ],
            [
              "Ethernet; programmable storage transport",
              "以太网；可编程存储传输"
            ],
            [
              "Traffic shaping; implementation-specific",
              "流量整形；依实现"
            ],
            [
              "NVMe, IPsec, crypto, compression, isolation",
              "NVMe、IPsec、密码、压缩、隔离"
            ],
            [
              "n/d",
              "n/d"
            ]
          ],
          "sources": [
            "P10",
            "E15",
            "P32"
          ]
        },
        {
          "id": "gaudinic",
          "values": [
            [
              "Gaudi 3 integrated NIC",
              "Gaudi 3 integrated NIC"
            ],
            [
              "2024",
              "2024"
            ],
            [
              "Shipping",
              "已商用"
            ],
            [
              "On-accelerator fabric",
              "加速器内置网络"
            ],
            [
              "24 x 200GbE",
              "24 x 200GbE"
            ],
            [
              "48 x 112G PAM4",
              "48 x 112G PAM4"
            ],
            [
              "Internal to accelerator",
              "加速器内部"
            ],
            [
              "Communication engines",
              "通信引擎"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "Uses accelerator memory",
              "使用加速器内存"
            ],
            [
              "RoCE",
              "RoCE"
            ],
            [
              "Ethernet fabric configuration",
              "以太网网络配置"
            ],
            [
              "Device RDMA and collectives",
              "设备 RDMA 与集合通信"
            ],
            [
              "Included in accelerator power",
              "包含于加速器功耗"
            ]
          ],
          "sources": [
            "P02"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3,
          4,
          5,
          6
        ],
        [
          0,
          7,
          8,
          9,
          10
        ],
        [
          0,
          11,
          12,
          13
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "links": {
      "id": "links",
      "title": [
        "Separate bandwidth domains",
        "分离的带宽域"
      ],
      "headers": [
        [
          "Interconnect",
          "互联"
        ],
        [
          "Year / generation",
          "年份／代际"
        ],
        [
          "Lane rate",
          "通道速率"
        ],
        [
          "Lanes / link",
          "每链路通道"
        ],
        [
          "GB/s per link per direction",
          "每链路单向 GB/s"
        ],
        [
          "Links / device",
          "每设备链路"
        ],
        [
          "Topology",
          "拓扑"
        ],
        [
          "Domain limit",
          "域规模"
        ],
        [
          "Coherence / semantics",
          "一致性／语义"
        ]
      ],
      "rows": [
        {
          "id": "pcie3",
          "values": [
            [
              "PCIe 3",
              "PCIe 3"
            ],
            [
              "2010s",
              "2010s"
            ],
            [
              "8 GT/s",
              "8 GT/s"
            ],
            [
              "16",
              "16"
            ],
            [
              "15.75",
              "15.75"
            ],
            [
              "Platform-dependent",
              "依平台"
            ],
            [
              "Root / switch tree",
              "根／交换树"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "I/O; no general cache coherence",
              "I/O；无通用缓存一致性"
            ]
          ],
          "sources": [
            "P05"
          ]
        },
        {
          "id": "pcie4",
          "values": [
            [
              "PCIe 4",
              "PCIe 4"
            ],
            [
              "Ice Lake / Gaudi 2",
              "Ice Lake / Gaudi 2"
            ],
            [
              "16 GT/s",
              "16 GT/s"
            ],
            [
              "16",
              "16"
            ],
            [
              "31.51",
              "31.51"
            ],
            [
              "Platform-dependent",
              "依平台"
            ],
            [
              "Root / switch tree",
              "根／交换树"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "I/O DMA",
              "I/O DMA"
            ]
          ],
          "sources": [
            "P02",
            "P24"
          ]
        },
        {
          "id": "pcie5",
          "values": [
            [
              "PCIe 5",
              "PCIe 5"
            ],
            [
              "Sapphire / Gaudi 3",
              "Sapphire / Gaudi 3"
            ],
            [
              "32 GT/s",
              "32 GT/s"
            ],
            [
              "16",
              "16"
            ],
            [
              "63.02",
              "63.02"
            ],
            [
              "Platform-dependent",
              "依平台"
            ],
            [
              "Root / switch tree",
              "根／交换树"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "I/O; CXL is a separate protocol",
              "I/O；CXL 是另一协议"
            ]
          ],
          "sources": [
            "P02",
            "P03"
          ]
        },
        {
          "id": "cxl",
          "values": [
            [
              "CXL 1.1 → 2.0 → 3.0",
              "CXL 1.1 → 2.0 → 3.0"
            ],
            [
              "SPR → Xeon 6 → Diamond",
              "SPR → Xeon 6 → Diamond"
            ],
            [
              "PCIe PHY generation-dependent",
              "取决于 PCIe PHY 代际"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Shared physical lane budget",
              "共享物理通道预算"
            ],
            [
              "Direct / switched by version",
              "随版本支持直连／交换"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Cache / memory semantics by device type",
              "缓存／内存语义依设备类型"
            ]
          ],
          "sources": [
            "P03",
            "C12",
            "E01",
            "R04"
          ]
        },
        {
          "id": "gaudi",
          "values": [
            [
              "Gaudi 3 Ethernet",
              "Gaudi 3 Ethernet"
            ],
            [
              "2024",
              "2024"
            ],
            [
              "112G PAM4 SerDes",
              "112G PAM4 SerDes"
            ],
            [
              "2 per 200GbE",
              "2 每 200GbE"
            ],
            [
              "25",
              "25"
            ],
            [
              "24",
              "24"
            ],
            [
              "3 links × 7 peers + 3 external",
              "3 链路×7 对端＋3 外联"
            ],
            [
              "8 local",
              "8 本地"
            ],
            [
              "RDMA; not CPU cache coherence",
              "RDMA；非 CPU 缓存一致性"
            ]
          ],
          "sources": [
            "P02"
          ]
        },
        {
          "id": "xelink",
          "values": [
            [
              "Xe Link / Max 1550",
              "Xe Link / Max 1550"
            ],
            [
              "2023",
              "2023"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "System-wired GPU graph",
              "系统布线的 GPU 图"
            ],
            [
              "4 GPU Lenovo reference",
              "Lenovo 参考为 4 GPU"
            ],
            [
              "Peer GPU memory traffic",
              "对等 GPU 内存流量"
            ]
          ],
          "sources": [
            "P27"
          ]
        },
        {
          "id": "oci",
          "values": [
            [
              "Optical compute interconnect",
              "Optical 计算 interconnect"
            ],
            [
              "2024 demo",
              "2024 demo"
            ],
            [
              "32 Gb/s optical channel",
              "32 Gb/s optical channel"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "250 aggregate TX, derived",
              "合计发送 250，推导值"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "Optical chip-to-chip",
              "芯片间光连接"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Physical I/O demonstration, not a coherence protocol",
              "物理 I/O 演示，非一致性协议"
            ]
          ],
          "sources": [
            "E12"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3,
          4
        ],
        [
          0,
          5,
          6,
          7,
          8
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "systems": {
      "id": "systems",
      "title": [
        "Representative deployed or documented systems",
        "代表性部署与文档化系统"
      ],
      "headers": [
        [
          "Platform",
          "平台"
        ],
        [
          "Year / milestone",
          "年份／里程碑"
        ],
        [
          "CPU / accelerator count",
          "CPU／加速器数量"
        ],
        [
          "Scale-up domain",
          "纵向扩展域"
        ],
        [
          "Scale-out per accelerator",
          "每加速器横向带宽"
        ],
        [
          "Rack power",
          "机架功耗"
        ],
        [
          "Cooling",
          "散热"
        ]
      ],
      "rows": [
        {
          "id": "dl1",
          "values": [
            [
              "AWS DL1",
              "AWS DL1"
            ],
            [
              "2021 GA",
              "2021 GA"
            ],
            [
              "2 Xeon; 8 Gaudi",
              "2 Xeon；8 Gaudi"
            ],
            [
              "8 Gaudi",
              "8 Gaudi"
            ],
            [
              "400Gb/s instance ÷ 8 = 6.25 GB/s average; shared",
              "实例 400Gb/s÷8＝平均 6.25 GB/s；共享"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ]
          ],
          "sources": [
            "E14"
          ]
        },
        {
          "id": "aurora",
          "values": [
            [
              "Aurora",
              "Aurora"
            ],
            [
              "2023 installation; later user service",
              "2023 完成安装；随后提供用户服务"
            ],
            [
              "2 Xeon Max + 6 GPU Max / node",
              "每节点 2 Xeon Max＋6 GPU Max"
            ],
            [
              "6 GPU node; Xe Link topology",
              "6 GPU 节点；Xe Link 拓扑"
            ],
            [
              "8 x 200Gb/s NIC ÷ 6 = 33.3 GB/s average",
              "8×200Gb/s NIC÷6＝平均 33.3 GB/s"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Direct liquid",
              "直接液冷"
            ]
          ],
          "sources": [
            "P31"
          ]
        },
        {
          "id": "lenovo",
          "values": [
            [
              "Lenovo SD650-I V3",
              "Lenovo SD650-I V3"
            ],
            [
              "2023; withdrawn 2024",
              "2023; 停止营销 2024"
            ],
            [
              "Up to 2 Xeon + 4 GPU Max",
              "最高 2 Xeon＋4 GPU Max"
            ],
            [
              "4 GPU",
              "4 GPU"
            ],
            [
              "Adapter-dependent",
              "依适配器"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Direct water cooling",
              "直接水冷"
            ]
          ],
          "sources": [
            "P27"
          ]
        },
        {
          "id": "gaudi",
          "values": [
            [
              "Gaudi 3 HLB-325",
              "Gaudi 3 HLB-325"
            ],
            [
              "2024",
              "2024"
            ],
            [
              "Host CPUs + 8 Gaudi 3",
              "主机 CPU＋8 Gaudi 3"
            ],
            [
              "8 Gaudi",
              "8 Gaudi"
            ],
            [
              "3 x 200GbE = 75 GB/s one-way",
              "3×200GbE＝单向 75 GB/s"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Air / liquid variants",
              "风冷／液冷变体"
            ]
          ],
          "sources": [
            "P02"
          ]
        },
        {
          "id": "c3",
          "values": [
            [
              "Google C3",
              "Google C3"
            ],
            [
              "2023 GA",
              "2023 GA"
            ],
            [
              "Xeon 4th gen + custom IPU",
              "第四代 Xeon＋定制 IPU"
            ],
            [
              "CPU virtual machine",
              "CPU 虚拟机"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ]
          ],
          "sources": [
            "E15"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3
        ],
        [
          0,
          4,
          5,
          6
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "software": {
      "id": "software",
      "title": [
        "Software milestones and hardware relationship",
        "软件里程碑与硬件关系"
      ],
      "headers": [
        [
          "Stack / release",
          "软件栈／版本"
        ],
        [
          "Date / era",
          "日期／时期"
        ],
        [
          "Hardware enabled",
          "支持硬件"
        ],
        [
          "Key features / constraint",
          "主要功能／约束"
        ]
      ],
      "rows": [
        {
          "id": "cpu",
          "values": [
            [
              "oneDNN / CPU framework libraries",
              "oneDNN／CPU 框架库"
            ],
            [
              "2017–2026",
              "2017–2026"
            ],
            [
              "Xeon AVX-512 / VNNI / AMX",
              "Xeon AVX-512 / VNNI / AMX"
            ],
            [
              "ISA dispatch, packing and kernel selection; application must use enabled path",
              "ISA 分派、打包和内核选择；应用必须使用已启用路径"
            ]
          ],
          "sources": [
            "P03",
            "P05"
          ]
        },
        {
          "id": "oneapi",
          "values": [
            [
              "oneAPI / SYCL / Level Zero",
              "oneAPI / SYCL / Level Zero"
            ],
            [
              "2020s",
              "2020s"
            ],
            [
              "Xe GPU / CPU",
              "Xe GPU / CPU"
            ],
            [
              "Shared programming model; placement and device-specific tuning remain",
              "共享编程模型；仍需数据放置和设备特定调优"
            ]
          ],
          "sources": [
            "P11",
            "P31"
          ]
        },
        {
          "id": "gaudi",
          "values": [
            [
              "SynapseAI / Gaudi software 1.24",
              "SynapseAI / Gaudi software 1.24"
            ],
            [
              "2026 documentation",
              "2026 文档"
            ],
            [
              "Gaudi 2 / Gaudi 3",
              "Gaudi 2 / Gaudi 3"
            ],
            [
              "PyTorch integration, graph compilation, TPC kernels and HCCL",
              "PyTorch 集成、图编译、TPC 内核与 HCCL"
            ]
          ],
          "sources": [
            "P30",
            "P34"
          ]
        },
        {
          "id": "ipu",
          "values": [
            [
              "IPU SDK",
              "IPU SDK"
            ],
            [
              "2023–2024 documentation",
              "2023–2024 文档"
            ],
            [
              "E2100 IPU",
              "E2100 IPU"
            ],
            [
              "P4 pipeline, infrastructure services and host integration",
              "P4 流水线、基础设施服务与主机集成"
            ]
          ],
          "sources": [
            "P10"
          ]
        },
        {
          "id": "offload",
          "values": [
            [
              "DSA / IAA software interfaces",
              "DSA / IAA software interfaces"
            ],
            [
              "2023 onward",
              "2023 起"
            ],
            [
              "Xeon integrated engines",
              "Xeon 集成引擎"
            ],
            [
              "Work queues, shared virtual addressing and asynchronous completion; overhead matters",
              "工作队列、共享虚拟寻址和异步完成；需考虑开销"
            ]
          ],
          "sources": [
            "R02",
            "P03"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "ratios": {
      "id": "ratios",
      "title": [
        "Derived ratios from stated reference configurations",
        "由已列参考配置推导的配比"
      ],
      "headers": [
        [
          "Reference",
          "参考配置"
        ],
        [
          "DRAM GB/s per core",
          "每核 DRAM GB/s"
        ],
        [
          "L3 MB per core",
          "每核 L3 MB"
        ],
        [
          "Interpretation",
          "解释"
        ]
      ],
      "rows": [
        {
          "id": "bdw",
          "values": [
            [
              "Broadwell 2699 v4",
              "Broadwell 2699 v4"
            ],
            [
              "3.49",
              "3.49"
            ],
            [
              "2.50",
              "2.50"
            ],
            [
              "22 cores share four channels",
              "22 核共享四通道"
            ]
          ],
          "sources": [
            "P20"
          ]
        },
        {
          "id": "skl",
          "values": [
            [
              "Skylake 8180",
              "Skylake 8180"
            ],
            [
              "4.57",
              "4.57"
            ],
            [
              "1.375",
              "1.375"
            ],
            [
              "L2 grows; L3 changes inclusion policy",
              "L2 扩大；L3 包含策略改变"
            ]
          ],
          "sources": [
            "P21",
            "P06"
          ]
        },
        {
          "id": "spr",
          "values": [
            [
              "Sapphire 8490H",
              "Sapphire 8490H"
            ],
            [
              "5.12",
              "5.12"
            ],
            [
              "1.875",
              "1.875"
            ],
            [
              "AMX raises arithmetic demand",
              "AMX 提高计算供数需求"
            ]
          ],
          "sources": [
            "P03",
            "P25"
          ]
        },
        {
          "id": "emr",
          "values": [
            [
              "Emerald 8592+",
              "Emerald 8592+"
            ],
            [
              "5.60",
              "5.60"
            ],
            [
              "5.00",
              "5.00"
            ],
            [
              "Large LLC capacity increase",
              "LLC 容量大幅增加"
            ]
          ],
          "sources": [
            "P26"
          ]
        },
        {
          "id": "srf",
          "values": [
            [
              "Sierra 6780E",
              "Sierra 6780E"
            ],
            [
              "2.84",
              "2.84"
            ],
            [
              "0.75",
              "0.75"
            ],
            [
              "Density-oriented reference",
              "面向密度的参考配置"
            ]
          ],
          "sources": [
            "P17"
          ]
        },
        {
          "id": "gnr",
          "values": [
            [
              "Granite 6980P / MRDIMM",
              "Granite 6980P / MRDIMM"
            ],
            [
              "6.60",
              "6.60"
            ],
            [
              "3.9375",
              "3.9375"
            ],
            [
              "12 channels at 8800 MT/s",
              "12 通道、8800 MT/s"
            ]
          ],
          "sources": [
            "P16",
            "P18"
          ]
        },
        {
          "id": "cwf",
          "values": [
            [
              "Clearwater 6990E+",
              "Clearwater 6990E+"
            ],
            [
              "2.67",
              "2.67"
            ],
            [
              "2.00",
              "2.00"
            ],
            [
              "Double cores; more cache per core",
              "核心翻倍；每核缓存增多"
            ]
          ],
          "sources": [
            "P01",
            "P19"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "balance": {
      "id": "balance",
      "title": [
        "Accelerator balance, dense BF16 basis",
        "加速器配比：稠密 BF16 口径"
      ],
      "headers": [
        [
          "Device",
          "设备"
        ],
        [
          "HBM bytes/FLOP",
          "HBM 字节／FLOP"
        ],
        [
          "All-port network / HBM BW",
          "全端口网络／HBM 带宽"
        ],
        [
          "External BW / device",
          "每设备外部带宽"
        ],
        [
          "BF16 peak / device power",
          "BF16 峰值／设备功耗"
        ]
      ],
      "rows": [
        {
          "id": "g2",
          "values": [
            [
              "Gaudi 2",
              "Gaudi 2"
            ],
            [
              "0.00569",
              "0.00569"
            ],
            [
              "0.122",
              "0.122"
            ],
            [
              "37.5 GB/s, 3 x 100GbE allocation",
              "37.5 GB/s，分配 3×100GbE"
            ],
            [
              "0.720 TF/W at 600 W",
              "600 W 下 0.720 TF/W"
            ]
          ],
          "sources": [
            "P02",
            "P30"
          ]
        },
        {
          "id": "g3",
          "values": [
            [
              "Gaudi 3",
              "Gaudi 3"
            ],
            [
              "0.00221",
              "0.00221"
            ],
            [
              "0.162",
              "0.162"
            ],
            [
              "75 GB/s, 3 x 200GbE allocation",
              "75 GB/s，分配 3×200GbE"
            ],
            [
              "1.864 TF/W at 900 W",
              "900 W 下 1.864 TF/W"
            ]
          ],
          "sources": [
            "P02"
          ]
        },
        {
          "id": "pvc",
          "values": [
            [
              "GPU Max 1550",
              "GPU Max 1550"
            ],
            [
              "0.00381",
              "0.00381"
            ],
            [
              "0.0994 Xe Link / HBM, Lenovo basis",
              "0.0994 Xe Link／HBM，Lenovo 口径"
            ],
            [
              "System-dependent",
              "依系统"
            ],
            [
              "1.398 TF/W at 600 W",
              "600 W 下 1.398 TF/W"
            ]
          ],
          "sources": [
            "P27"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3,
          4
        ]
      ],
      "basis": "HBM bandwidth divided by dense BF16 FLOP/s; fabric per direction / HBM; peak/TDP is not measured energy efficiency"
    },
    "conferences": {
      "id": "conferences",
      "title": [
        "Conference-to-product index",
        "会议到产品索引"
      ],
      "headers": [
        [
          "Venue",
          "会议／活动"
        ],
        [
          "Year",
          "年份"
        ],
        [
          "Paper / talk / disclosure",
          "论文／演讲／披露"
        ],
        [
          "Presenter / authors",
          "报告人／作者"
        ],
        [
          "Product",
          "产品"
        ],
        [
          "Evidence type",
          "证据类型"
        ],
        [
          "Source",
          "来源"
        ]
      ],
      "rows": [
        {
          "id": "knl",
          "values": [
            [
              "Hot Chips",
              "Hot Chips"
            ],
            [
              "2015",
              "2015"
            ],
            [
              "Knights Landing",
              "Knights Landing"
            ],
            [
              "Avinash Sodani",
              "Avinash Sodani"
            ],
            [
              "Xeon Phi",
              "Xeon Phi"
            ],
            [
              "Product architecture",
              "产品架构"
            ],
            [
              "C13",
              "C13"
            ]
          ],
          "sources": [
            "C13"
          ]
        },
        {
          "id": "clx",
          "values": [
            [
              "Hot Chips",
              "Hot Chips"
            ],
            [
              "2018",
              "2018"
            ],
            [
              "Cascade Lake",
              "Cascade Lake"
            ],
            [
              "Akhilesh Kumar",
              "Akhilesh Kumar"
            ],
            [
              "Xeon 2nd gen",
              "Xeon 2nd gen"
            ],
            [
              "Architecture / VNNI / memory",
              "架构／VNNI／内存"
            ],
            [
              "C06",
              "C06"
            ]
          ],
          "sources": [
            "C06"
          ]
        },
        {
          "id": "nnp",
          "values": [
            [
              "Hot Chips",
              "Hot Chips"
            ],
            [
              "2019",
              "2019"
            ],
            [
              "Nervana; packaging; Optane",
              "Nervana; packaging; Optane"
            ],
            [
              "Intel",
              "Intel"
            ],
            [
              "NNP-T / NNP-I",
              "NNP-T / NNP-I"
            ],
            [
              "Official press release",
              "官方新闻稿"
            ],
            [
              "C14",
              "C14"
            ]
          ],
          "sources": [
            "C14"
          ]
        },
        {
          "id": "hpca",
          "values": [
            [
              "HPCA",
              "HPCA"
            ],
            [
              "2020",
              "2020"
            ],
            [
              "Persistent Memory and the Path to Being Comfortably NUMB",
              "Persistent Memory and the Path to Being Comfortably NUMB"
            ],
            [
              "Steven Swanson",
              "Steven Swanson"
            ],
            [
              "Optane context",
              "Optane 相关背景"
            ],
            [
              "Independent research keynote",
              "独立研究主题演讲"
            ],
            [
              "R05",
              "R05"
            ]
          ],
          "sources": [
            "R05"
          ]
        },
        {
          "id": "pvc",
          "values": [
            [
              "ISSCC",
              "ISSCC"
            ],
            [
              "2022",
              "2022"
            ],
            [
              "Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing",
              "Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing"
            ],
            [
              "W. Gomes et al.",
              "W. Gomes et al."
            ],
            [
              "Ponte Vecchio",
              "Ponte Vecchio"
            ],
            [
              "Implementation; paper 2.1 press kit",
              "实现；论文 2.1 新闻资料"
            ],
            [
              "C03",
              "C03"
            ]
          ],
          "sources": [
            "C03"
          ]
        },
        {
          "id": "spr",
          "values": [
            [
              "ISSCC",
              "ISSCC"
            ],
            [
              "2022",
              "2022"
            ],
            [
              "Sapphire Rapids: Next-Generation Xeon",
              "Sapphire Rapids: Next-Generation Xeon"
            ],
            [
              "Intel",
              "Intel"
            ],
            [
              "Sapphire Rapids",
              "Sapphire Rapids"
            ],
            [
              "Implementation; paper 2.2 press kit",
              "实现；论文 2.2 新闻资料"
            ],
            [
              "C03",
              "C03"
            ]
          ],
          "sources": [
            "C03"
          ]
        },
        {
          "id": "c3",
          "values": [
            [
              "Google Cloud Next",
              "Google Cloud Next"
            ],
            [
              "2022",
              "2022"
            ],
            [
              "C3 and custom Intel IPU",
              "C3 and custom Intel IPU"
            ],
            [
              "Google / Intel",
              "Google / Intel"
            ],
            [
              "Sapphire Rapids + IPU",
              "Sapphire Rapids + IPU"
            ],
            [
              "Preview; GA followed 2023",
              "预览；2023 年商用"
            ],
            [
              "E15",
              "E15"
            ]
          ],
          "sources": [
            "E15"
          ]
        },
        {
          "id": "gnr",
          "values": [
            [
              "Hot Chips",
              "Hot Chips"
            ],
            [
              "2023",
              "2023"
            ],
            [
              "Granite Rapids and Sierra Forest",
              "Granite Rapids and Sierra Forest"
            ],
            [
              "Intel",
              "Intel"
            ],
            [
              "Xeon 6",
              "Xeon 6"
            ],
            [
              "Architecture briefing slides",
              "架构介绍幻灯片"
            ],
            [
              "C12",
              "C12"
            ]
          ],
          "sources": [
            "C12"
          ]
        },
        {
          "id": "cxl",
          "values": [
            [
              "MICRO",
              "MICRO"
            ],
            [
              "2023",
              "2023"
            ],
            [
              "Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices",
              "Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices"
            ],
            [
              "Yan Sun et al.",
              "Yan Sun et al."
            ],
            [
              "Sapphire Rapids / CXL",
              "Sapphire Rapids / CXL"
            ],
            [
              "Real-device measurement",
              "真实设备测量"
            ],
            [
              "R04",
              "R04"
            ]
          ],
          "sources": [
            "R04"
          ]
        },
        {
          "id": "emr",
          "values": [
            [
              "ISSCC",
              "ISSCC"
            ],
            [
              "2024",
              "2024"
            ],
            [
              "Emerald Rapids: 5th-Generation Xeon Scalable",
              "Emerald Rapids: 5th-Generation Xeon Scalable"
            ],
            [
              "Ashley O. Munch et al.",
              "Ashley O. Munch et al."
            ],
            [
              "Emerald Rapids",
              "Emerald Rapids"
            ],
            [
              "Implementation; paper 2.3 press kit",
              "实现；论文 2.3 新闻资料"
            ],
            [
              "C04",
              "C04"
            ]
          ],
          "sources": [
            "C04"
          ]
        },
        {
          "id": "dsa",
          "values": [
            [
              "ASPLOS",
              "ASPLOS"
            ],
            [
              "2024",
              "2024"
            ],
            [
              "A Quantitative Analysis and Guidelines of Data Streaming Accelerator in Modern Intel Xeon Scalable Processors",
              "A Quantitative Analysis and Guidelines of Data Streaming Accelerator in Modern Intel Xeon Scalable Processors"
            ],
            [
              "Reese Kuper et al.",
              "Reese Kuper 等"
            ],
            [
              "DSA / Sapphire Rapids",
              "DSA / Sapphire Rapids"
            ],
            [
              "Measured offload behavior",
              "卸载行为测量"
            ],
            [
              "R02",
              "R02"
            ]
          ],
          "sources": [
            "R02"
          ]
        },
        {
          "id": "gaudi",
          "values": [
            [
              "Hot Chips",
              "Hot Chips"
            ],
            [
              "2024",
              "2024"
            ],
            [
              "Gaudi 3; Xeon 6; optical I/O",
              "Gaudi 3; Xeon 6; optical I/O"
            ],
            [
              "Intel",
              "Intel"
            ],
            [
              "Gaudi 3 / Xeon 6 / OCI",
              "Gaudi 3 / Xeon 6 / OCI"
            ],
            [
              "Architecture and demo summary",
              "架构与演示摘要"
            ],
            [
              "E13",
              "E13"
            ]
          ],
          "sources": [
            "E13"
          ]
        },
        {
          "id": "ofc",
          "values": [
            [
              "OFC",
              "OFC"
            ],
            [
              "2024",
              "2024"
            ],
            [
              "Integrated optical compute interconnect",
              "Integrated optical 计算 interconnect"
            ],
            [
              "Intel IPS",
              "Intel IPS"
            ],
            [
              "OCI chiplet",
              "OCI chiplet"
            ],
            [
              "Live technology demonstration",
              "实时技术演示"
            ],
            [
              "E12",
              "E12"
            ]
          ],
          "sources": [
            "E12"
          ]
        },
        {
          "id": "vision",
          "values": [
            [
              "Intel Vision",
              "Intel Vision"
            ],
            [
              "2024",
              "2024"
            ],
            [
              "Gaudi 3 architecture and open systems",
              "Gaudi 3 architecture and open systems"
            ],
            [
              "Intel",
              "Intel"
            ],
            [
              "Gaudi 3",
              "Gaudi 3"
            ],
            [
              "Product announcement",
              "产品公布"
            ],
            [
              "E20",
              "E20"
            ]
          ],
          "sources": [
            "E20"
          ]
        },
        {
          "id": "lia",
          "values": [
            [
              "ISCA",
              "ISCA"
            ],
            [
              "2025",
              "2025"
            ],
            [
              "LIA: cooperative AMX CPU-GPU computation and CXL offloading",
              "LIA: cooperative AMX CPU-GPU computation and CXL offloading"
            ],
            [
              "Hyungyo Kim et al.",
              "Hyungyo Kim 等"
            ],
            [
              "Sapphire / Granite Rapids",
              "Sapphire / Granite Rapids"
            ],
            [
              "Independent system research",
              "独立系统研究"
            ],
            [
              "R01",
              "R01"
            ]
          ],
          "sources": [
            "R01"
          ]
        },
        {
          "id": "cwf",
          "values": [
            [
              "Hot Chips / Tech Tour",
              "Hot Chips / Tech Tour"
            ],
            [
              "2025",
              "2025"
            ],
            [
              "Clearwater Forest",
              "Clearwater Forest"
            ],
            [
              "Intel",
              "Intel"
            ],
            [
              "Xeon 6+",
              "Xeon 6+"
            ],
            [
              "Architecture / packaging",
              "架构／封装"
            ],
            [
              "P08",
              "P08"
            ]
          ],
          "sources": [
            "P08"
          ]
        },
        {
          "id": "ocp",
          "values": [
            [
              "OCP Global Summit",
              "OCP Global Summit"
            ],
            [
              "2025",
              "2025"
            ],
            [
              "Crescent Island initial disclosure",
              "Crescent Island initial disclosure"
            ],
            [
              "Intel",
              "Intel"
            ],
            [
              "Crescent Island",
              "Crescent Island"
            ],
            [
              "Roadmap / sampling target",
              "路线图／送样目标"
            ],
            [
              "E03",
              "E03"
            ]
          ],
          "sources": [
            "E03"
          ]
        },
        {
          "id": "mwc",
          "values": [
            [
              "MWC",
              "MWC"
            ],
            [
              "2026",
              "2026"
            ],
            [
              "Xeon 6+ network and edge positioning",
              "Xeon 6+ network and edge positioning"
            ],
            [
              "Intel",
              "Intel"
            ],
            [
              "Clearwater Forest",
              "Clearwater Forest"
            ],
            [
              "Platform demonstration",
              "平台演示"
            ],
            [
              "E16",
              "E16"
            ]
          ],
          "sources": [
            "E16"
          ]
        },
        {
          "id": "computex",
          "values": [
            [
              "Computex",
              "Computex"
            ],
            [
              "2026",
              "2026"
            ],
            [
              "Xeon 6+ and E835 launch",
              "Xeon 6+ and E835 launch"
            ],
            [
              "Intel",
              "Intel"
            ],
            [
              "Clearwater / E835 / Crescent",
              "Clearwater / E835 / Crescent"
            ],
            [
              "Commercial launch / update",
              "商用发布／更新"
            ],
            [
              "E02",
              "E02"
            ]
          ],
          "sources": [
            "E02"
          ]
        },
        {
          "id": "hc26",
          "values": [
            [
              "Hot Chips",
              "Hot Chips"
            ],
            [
              "2026",
              "2026"
            ],
            [
              "Diamond Rapids and Crescent Island",
              "Diamond Rapids and Crescent Island"
            ],
            [
              "Intel",
              "Intel"
            ],
            [
              "Diamond / Crescent",
              "Diamond / Crescent"
            ],
            [
              "Architecture announcement",
              "架构公布"
            ],
            [
              "E01",
              "E01"
            ]
          ],
          "sources": [
            "E01"
          ]
        },
        {
          "id": "foundry",
          "values": [
            [
              "Foundry Direct Connect",
              "Foundry Direct Connect"
            ],
            [
              "2024–2025",
              "2024–2025"
            ],
            [
              "Process and packaging enablement",
              "Process and packaging enablement"
            ],
            [
              "Intel / EDA partners",
              "Intel / EDA partners"
            ],
            [
              "18A / EMIB / Foveros",
              "18A / EMIB / Foveros"
            ],
            [
              "Technology ecosystem",
              "技术生态"
            ],
            [
              "E19",
              "E19"
            ]
          ],
          "sources": [
            "E19"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3
        ],
        [
          0,
          4,
          5,
          6
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    }
  },
  "figures": {
    "era1": {
      "id": "era1",
      "title": [
        "2015–2016: host CPU and self-hosted many-core",
        "2015–2016：主机 CPU 与可自启动多核处理器"
      ],
      "nodes": [
        [
          "cpu",
          [
            "Broadwell Xeon\n22 cores / socket",
            "Broadwell Xeon\n每插槽 22 核"
          ],
          0,
          0
        ],
        [
          "ddr",
          [
            "Host DDR4\n4 channels",
            "主机 DDR4\n4 通道"
          ],
          1,
          0
        ],
        [
          "phi",
          [
            "Knights Landing\n72 cores; self-hosted",
            "Knights Landing\n72 核；可自启动"
          ],
          0,
          1
        ],
        [
          "mc",
          [
            "MCDRAM 16 GB\nlocal to Phi",
            "MCDRAM 16 GB\nPhi 本地内存"
          ],
          1,
          1
        ],
        [
          "fabric",
          [
            "HPC network\noptional Omni-Path",
            "HPC 网络\n可选 Omni-Path"
          ],
          0,
          2
        ],
        [
          "far",
          [
            "Phi DDR4\ncapacity tier",
            "Phi DDR4\n容量层"
          ],
          1,
          2
        ]
      ],
      "edges": [
        [
          "cpu",
          "ddr",
          "76.8 GB/s"
        ],
        [
          "phi",
          "mc",
          [
            "400+ GB/s class",
            "400+ GB/s 级"
          ]
        ],
        [
          "phi",
          "far",
          [
            "Separate DDR controllers",
            "独立 DDR 控制器"
          ]
        ],
        [
          "phi",
          "fabric",
          [
            "Network endpoint",
            "网络端点"
          ]
        ],
        [
          "cpu",
          "fabric",
          [
            "Server network adapter",
            "服务器网络适配器"
          ]
        ]
      ],
      "caption": [
        "Xeon and Phi are alternative node constructions here; the diagram does not imply Knights Landing is attached to Broadwell as a mandatory coprocessor.",
        "此处 Xeon 与 Phi 表示不同节点构造；图中不表示 Knights Landing 必须作为 Broadwell 的协处理器连接。"
      ]
    },
    "era2": {
      "id": "era2",
      "title": [
        "2019–2021: CPU plus Ethernet-connected AI devices",
        "2019–2021：CPU 与以太网互联 AI 设备"
      ],
      "nodes": [
        [
          "cpu",
          [
            "Cascade Lake host",
            "Cascade Lake 主机"
          ],
          0,
          0
        ],
        [
          "ddr",
          [
            "DDR4 / optional Optane",
            "DDR4／可选 Optane"
          ],
          1,
          0
        ],
        [
          "gpus",
          [
            "8 Gaudi devices\nAWS DL1 example",
            "8 颗 Gaudi\nAWS DL1 示例"
          ],
          0,
          1
        ],
        [
          "hbm",
          [
            "32 GB HBM per device",
            "每颗设备 32 GB HBM"
          ],
          1,
          1
        ],
        [
          "net",
          [
            "External network",
            "外部网络"
          ],
          0,
          2
        ],
        [
          "peer",
          [
            "Integrated Ethernet\npeer communication",
            "集成以太网\n对等通信"
          ],
          1,
          2
        ]
      ],
      "edges": [
        [
          "cpu",
          "ddr",
          [
            "Memory channels",
            "内存通道"
          ]
        ],
        [
          "cpu",
          "gpus",
          [
            "Host I/O path",
            "主机 I/O 路径"
          ]
        ],
        [
          "gpus",
          "hbm",
          [
            "Local memory",
            "本地内存"
          ]
        ],
        [
          "gpus",
          "peer",
          [
            "On-device RoCE ports",
            "片上 RoCE 端口"
          ]
        ],
        [
          "gpus",
          "net",
          [
            "DL1: 400 Gb/s instance",
            "DL1：实例 400 Gb/s"
          ]
        ]
      ],
      "caption": [
        "DL1’s external service bandwidth differs from Gaudi’s on-chip aggregate network port bandwidth. Optane is a CPU platform option, not Gaudi HBM.",
        "DL1 外部服务带宽不同于 Gaudi 片上全部网络端口带宽。Optane 属于 CPU 平台选项，并非 Gaudi HBM。"
      ]
    },
    "era3": {
      "id": "era3",
      "title": [
        "2023–2024: Aurora’s heterogeneous memory hierarchy",
        "2023–2024：Aurora 异构内存层次"
      ],
      "nodes": [
        [
          "cpu",
          [
            "2 Xeon Max / node",
            "每节点 2 Xeon Max"
          ],
          0,
          0
        ],
        [
          "ddr",
          [
            "CPU: HBM + DDR5",
            "CPU：HBM＋DDR5"
          ],
          1,
          0
        ],
        [
          "gpus",
          [
            "6 GPU Max / node\nXe Link peer graph",
            "每节点 6 GPU Max\nXe Link 对等拓扑"
          ],
          0,
          1
        ],
        [
          "hbm",
          [
            "128 GB HBM / GPU",
            "每 GPU 128 GB HBM"
          ],
          1,
          1
        ],
        [
          "net",
          [
            "8 Slingshot endpoints",
            "8 个 Slingshot 端点"
          ],
          0,
          2
        ],
        [
          "cluster",
          [
            "Dragonfly fabric",
            "Dragonfly 网络"
          ],
          1,
          2
        ]
      ],
      "edges": [
        [
          "cpu",
          "ddr",
          [
            "CPU memory tiers",
            "CPU 内存层"
          ]
        ],
        [
          "cpu",
          "gpus",
          "PCIe"
        ],
        [
          "gpus",
          "hbm",
          [
            "Device-local bandwidth",
            "设备本地带宽"
          ]
        ],
        [
          "gpus",
          "net",
          [
            "Topology / affinity matter",
            "取决于拓扑／亲和性"
          ]
        ],
        [
          "net",
          "cluster",
          "8 x 200 Gb/s"
        ]
      ],
      "caption": [
        "An average 33.3 GB/s scale-out budget per GPU follows from 8 × 200 Gb/s divided by six; it is not a uniform dedicated link allocation.",
        "8×200 Gb/s 除以六得到平均每 GPU 33.3 GB/s 横向预算，但这不是均匀的专用链路分配。"
      ]
    },
    "era4": {
      "id": "era4",
      "title": [
        "2024–2026: specialized compute and infrastructure paths",
        "2024–2026：分工明确的计算与基础设施路径"
      ],
      "nodes": [
        [
          "cpu",
          [
            "Xeon 6 / 6+\nP-core or E-core host",
            "Xeon 6／6+\nP 核或 E 核主机"
          ],
          0,
          0
        ],
        [
          "mem",
          [
            "DDR5 / MRDIMM\nCXL expansion by platform",
            "DDR5／MRDIMM\nCXL 扩展依平台"
          ],
          1,
          0
        ],
        [
          "gpus",
          [
            "8 Gaudi 3\n21 local ports / device",
            "8 颗 Gaudi 3\n每颗 21 个本地端口"
          ],
          0,
          1
        ],
        [
          "hbm",
          [
            "128 GB HBM2e / device\n3.7 TB/s",
            "每颗 128 GB HBM2e\n3.7 TB/s"
          ],
          1,
          1
        ],
        [
          "net",
          [
            "3 x 200GbE / Gaudi\nscale-out fabric",
            "每颗 Gaudi 3×200GbE\n横向扩展网络"
          ],
          0,
          2
        ],
        [
          "ipu",
          [
            "Host NIC / IPU\ninfrastructure services",
            "主机 NIC／IPU\n基础设施服务"
          ],
          1,
          2
        ]
      ],
      "edges": [
        [
          "cpu",
          "mem",
          [
            "Platform-dependent",
            "依平台"
          ]
        ],
        [
          "cpu",
          "gpus",
          "PCIe 5 x16"
        ],
        [
          "gpus",
          "hbm",
          [
            "Local HBM",
            "本地 HBM"
          ]
        ],
        [
          "gpus",
          "net",
          [
            "75 GB/s one-way / device",
            "每颗单向 75 GB/s"
          ]
        ],
        [
          "cpu",
          "ipu",
          [
            "Separate host I/O",
            "独立主机 I/O"
          ]
        ]
      ],
      "caption": [
        "This is a role diagram, not a claim of one mandatory OEM configuration. Crescent Island is a separate announced PCIe inference branch with LPDDR5X; Diamond Rapids is a disclosed future host platform.",
        "本图表示角色分工，并非唯一 OEM 配置。Crescent Island 是另行公布、采用 LPDDR5X 的 PCIe 推理分支；Diamond Rapids 是已披露的未来主机平台。"
      ]
    }
  },
  "claims": {
    "portfolio.cpu.0": {
      "value": "Host compute",
      "field": "Layer",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "E02",
        "P03"
      ],
      "disclosure_date": "2026",
      "status": "mixed",
      "scope": "cpu"
    },
    "portfolio.cpu.1": {
      "value": "Xeon Scalable / Xeon 6 / 6+",
      "field": "Families",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "E02",
        "P03"
      ],
      "disclosure_date": "2026",
      "status": "mixed",
      "scope": "cpu"
    },
    "portfolio.cpu.2": {
      "value": "General compute, AMX, orchestration",
      "field": "Architectural role",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "E02",
        "P03"
      ],
      "disclosure_date": "2026",
      "status": "mixed",
      "scope": "cpu"
    },
    "portfolio.cpu.3": {
      "value": "Diamond Rapids disclosed; GA not established",
      "field": "Status boundary",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "E02",
        "P03"
      ],
      "disclosure_date": "2026",
      "status": "mixed",
      "scope": "cpu"
    },
    "portfolio.accelerator.0": {
      "value": "Accelerators",
      "field": "Layer",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02",
        "C03",
        "E01",
        "E17"
      ],
      "disclosure_date": "2026",
      "status": "mixed",
      "scope": "accelerator"
    },
    "portfolio.accelerator.1": {
      "value": "Gaudi / GPU Max / Flex / Crescent Island",
      "field": "Families",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02",
        "C03",
        "E01",
        "E17"
      ],
      "disclosure_date": "2026",
      "status": "mixed",
      "scope": "accelerator"
    },
    "portfolio.accelerator.2": {
      "value": "Training, HPC, media and inference",
      "field": "Architectural role",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02",
        "C03",
        "E01",
        "E17"
      ],
      "disclosure_date": "2026",
      "status": "mixed",
      "scope": "accelerator"
    },
    "portfolio.accelerator.3": {
      "value": "Crescent Island announced; Falcon Shores internal only",
      "field": "Status boundary",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02",
        "C03",
        "E01",
        "E17"
      ],
      "disclosure_date": "2026",
      "status": "mixed",
      "scope": "accelerator"
    },
    "portfolio.network.0": {
      "value": "Network / infrastructure",
      "field": "Layer",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P10",
        "P14",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "network"
    },
    "portfolio.network.1": {
      "value": "E810 / E830 / E835; IPU E2000/E2100",
      "field": "Families",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P10",
        "P14",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "network"
    },
    "portfolio.network.2": {
      "value": "RDMA, packet processing, storage isolation",
      "field": "Architectural role",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P10",
        "P14",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "network"
    },
    "portfolio.network.3": {
      "value": "NIC and IPU are different device classes",
      "field": "Status boundary",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P10",
        "P14",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "network"
    },
    "portfolio.adjacent.0": {
      "value": "Adjacent technology",
      "field": "Layer",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11",
        "E12",
        "E17"
      ],
      "disclosure_date": "2026",
      "status": "mixed",
      "scope": "adjacent"
    },
    "portfolio.adjacent.1": {
      "value": "EMIB / Foveros / OCI / Altera / Optane",
      "field": "Families",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11",
        "E12",
        "E17"
      ],
      "disclosure_date": "2026",
      "status": "mixed",
      "scope": "adjacent"
    },
    "portfolio.adjacent.2": {
      "value": "Integration, optical links, programmable logic, memory",
      "field": "Architectural role",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11",
        "E12",
        "E17"
      ],
      "disclosure_date": "2026",
      "status": "mixed",
      "scope": "adjacent"
    },
    "portfolio.adjacent.3": {
      "value": "OCI demonstration; Altera 49% retained; Optane exited",
      "field": "Status boundary",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11",
        "E12",
        "E17"
      ],
      "disclosure_date": "2026",
      "status": "mixed",
      "scope": "adjacent"
    },
    "cpu.bdw.0": {
      "value": "E5 v4 / 2699 v4",
      "field": "Generation / reference SKU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P20"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "bdw"
    },
    "cpu.bdw.1": {
      "value": "Broadwell-EP",
      "field": "Codename",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P20"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "bdw"
    },
    "cpu.bdw.2": {
      "value": "2016",
      "field": "GA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P20"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "bdw"
    },
    "cpu.bdw.3": {
      "value": "Historical shipping",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P20"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "bdw"
    },
    "cpu.bdw.4": {
      "value": "Broadwell",
      "field": "Core µarch",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P20"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "bdw"
    },
    "cpu.bdw.5": {
      "value": "22 / 44",
      "field": "Cores / threads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P20"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "bdw"
    },
    "cpu.bdw.6": {
      "value": "14 nm",
      "field": "Process per die",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P20"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "bdw"
    },
    "cpu.bdw.7": {
      "value": "Monolithic; ring",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P20"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "bdw"
    },
    "cpu.bdw.8": {
      "value": "256 KB",
      "field": "L2 per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P20"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "bdw"
    },
    "cpu.bdw.9": {
      "value": "55 MB inclusive",
      "field": "L3 / domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P20"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "bdw"
    },
    "cpu.bdw.10": {
      "value": "DDR4; 4; 2400; 76.8",
      "field": "Memory: channels; rate; GB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P20"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "bdw"
    },
    "cpu.bdw.11": {
      "value": "2S; QPI 9.6 GT/s",
      "field": "Sockets / links",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P20"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "bdw"
    },
    "cpu.bdw.12": {
      "value": "40 PCIe 3; CXL n/a",
      "field": "PCIe / CXL",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P20"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "bdw"
    },
    "cpu.bdw.13": {
      "value": "145 W",
      "field": "TDP",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P20"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "bdw"
    },
    "cpu.bdw.14": {
      "value": "AVX2",
      "field": "Vector / matrix ISA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P20"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "bdw"
    },
    "cpu.skl.0": {
      "value": "1st / 8180",
      "field": "Generation / reference SKU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P06",
        "P21"
      ],
      "disclosure_date": "2017",
      "status": "historical shipping",
      "scope": "skl"
    },
    "cpu.skl.1": {
      "value": "Skylake-SP",
      "field": "Codename",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P06",
        "P21"
      ],
      "disclosure_date": "2017",
      "status": "historical shipping",
      "scope": "skl"
    },
    "cpu.skl.2": {
      "value": "2017",
      "field": "GA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P06",
        "P21"
      ],
      "disclosure_date": "2017",
      "status": "historical shipping",
      "scope": "skl"
    },
    "cpu.skl.3": {
      "value": "Historical shipping",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P06",
        "P21"
      ],
      "disclosure_date": "2017",
      "status": "historical shipping",
      "scope": "skl"
    },
    "cpu.skl.4": {
      "value": "Skylake",
      "field": "Core µarch",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P06",
        "P21"
      ],
      "disclosure_date": "2017",
      "status": "historical shipping",
      "scope": "skl"
    },
    "cpu.skl.5": {
      "value": "28 / 56",
      "field": "Cores / threads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P06",
        "P21"
      ],
      "disclosure_date": "2017",
      "status": "historical shipping",
      "scope": "skl"
    },
    "cpu.skl.6": {
      "value": "14 nm",
      "field": "Process per die",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P06",
        "P21"
      ],
      "disclosure_date": "2017",
      "status": "historical shipping",
      "scope": "skl"
    },
    "cpu.skl.7": {
      "value": "Monolithic; mesh",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P06",
        "P21"
      ],
      "disclosure_date": "2017",
      "status": "historical shipping",
      "scope": "skl"
    },
    "cpu.skl.8": {
      "value": "1 MB",
      "field": "L2 per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P06",
        "P21"
      ],
      "disclosure_date": "2017",
      "status": "historical shipping",
      "scope": "skl"
    },
    "cpu.skl.9": {
      "value": "38.5 MB non-inclusive",
      "field": "L3 / domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P06",
        "P21"
      ],
      "disclosure_date": "2017",
      "status": "historical shipping",
      "scope": "skl"
    },
    "cpu.skl.10": {
      "value": "DDR4; 6; 2666; ~128",
      "field": "Memory: channels; rate; GB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P06",
        "P21"
      ],
      "disclosure_date": "2017",
      "status": "historical shipping",
      "scope": "skl"
    },
    "cpu.skl.11": {
      "value": "2/4/8S; 3 UPI 10.4 GT/s",
      "field": "Sockets / links",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P06",
        "P21"
      ],
      "disclosure_date": "2017",
      "status": "historical shipping",
      "scope": "skl"
    },
    "cpu.skl.12": {
      "value": "48 PCIe 3; CXL n/a",
      "field": "PCIe / CXL",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P06",
        "P21"
      ],
      "disclosure_date": "2017",
      "status": "historical shipping",
      "scope": "skl"
    },
    "cpu.skl.13": {
      "value": "205 W",
      "field": "TDP",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P06",
        "P21"
      ],
      "disclosure_date": "2017",
      "status": "historical shipping",
      "scope": "skl"
    },
    "cpu.skl.14": {
      "value": "AVX-512",
      "field": "Vector / matrix ISA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P06",
        "P21"
      ],
      "disclosure_date": "2017",
      "status": "historical shipping",
      "scope": "skl"
    },
    "cpu.clx.0": {
      "value": "2nd / 8280",
      "field": "Generation / reference SKU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "C06",
        "P22"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "clx"
    },
    "cpu.clx.1": {
      "value": "Cascade Lake",
      "field": "Codename",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "C06",
        "P22"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "clx"
    },
    "cpu.clx.2": {
      "value": "2019",
      "field": "GA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "C06",
        "P22"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "clx"
    },
    "cpu.clx.3": {
      "value": "Historical shipping",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "C06",
        "P22"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "clx"
    },
    "cpu.clx.4": {
      "value": "Skylake-derived",
      "field": "Core µarch",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "C06",
        "P22"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "clx"
    },
    "cpu.clx.5": {
      "value": "28 / 56",
      "field": "Cores / threads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "C06",
        "P22"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "clx"
    },
    "cpu.clx.6": {
      "value": "14 nm",
      "field": "Process per die",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "C06",
        "P22"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "clx"
    },
    "cpu.clx.7": {
      "value": "Monolithic; mesh",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "C06",
        "P22"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "clx"
    },
    "cpu.clx.8": {
      "value": "1 MB",
      "field": "L2 per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "C06",
        "P22"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "clx"
    },
    "cpu.clx.9": {
      "value": "38.5 MB",
      "field": "L3 / domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "C06",
        "P22"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "clx"
    },
    "cpu.clx.10": {
      "value": "DDR4; 6; 2933; ~140.8",
      "field": "Memory: channels; rate; GB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "C06",
        "P22"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "clx"
    },
    "cpu.clx.11": {
      "value": "2/4/8S; 3 UPI 10.4 GT/s",
      "field": "Sockets / links",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "C06",
        "P22"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "clx"
    },
    "cpu.clx.12": {
      "value": "48 PCIe 3; CXL n/a",
      "field": "PCIe / CXL",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "C06",
        "P22"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "clx"
    },
    "cpu.clx.13": {
      "value": "205 W",
      "field": "TDP",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "C06",
        "P22"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "clx"
    },
    "cpu.clx.14": {
      "value": "AVX-512; VNNI",
      "field": "Vector / matrix ISA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "C06",
        "P22"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "clx"
    },
    "cpu.cpx.0": {
      "value": "3rd / 8380HL",
      "field": "Generation / reference SKU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P23"
      ],
      "disclosure_date": "2020",
      "status": "historical shipping",
      "scope": "cpx"
    },
    "cpu.cpx.1": {
      "value": "Cooper Lake",
      "field": "Codename",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P23"
      ],
      "disclosure_date": "2020",
      "status": "historical shipping",
      "scope": "cpx"
    },
    "cpu.cpx.2": {
      "value": "2020",
      "field": "GA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P23"
      ],
      "disclosure_date": "2020",
      "status": "historical shipping",
      "scope": "cpx"
    },
    "cpu.cpx.3": {
      "value": "Historical shipping",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P23"
      ],
      "disclosure_date": "2020",
      "status": "historical shipping",
      "scope": "cpx"
    },
    "cpu.cpx.4": {
      "value": "Skylake-derived",
      "field": "Core µarch",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P23"
      ],
      "disclosure_date": "2020",
      "status": "historical shipping",
      "scope": "cpx"
    },
    "cpu.cpx.5": {
      "value": "28 / 56",
      "field": "Cores / threads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P23"
      ],
      "disclosure_date": "2020",
      "status": "historical shipping",
      "scope": "cpx"
    },
    "cpu.cpx.6": {
      "value": "14 nm",
      "field": "Process per die",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P23"
      ],
      "disclosure_date": "2020",
      "status": "historical shipping",
      "scope": "cpx"
    },
    "cpu.cpx.7": {
      "value": "Monolithic; scale-up",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P23"
      ],
      "disclosure_date": "2020",
      "status": "historical shipping",
      "scope": "cpx"
    },
    "cpu.cpx.8": {
      "value": "1 MB",
      "field": "L2 per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P23"
      ],
      "disclosure_date": "2020",
      "status": "historical shipping",
      "scope": "cpx"
    },
    "cpu.cpx.9": {
      "value": "38.5 MB",
      "field": "L3 / domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P23"
      ],
      "disclosure_date": "2020",
      "status": "historical shipping",
      "scope": "cpx"
    },
    "cpu.cpx.10": {
      "value": "DDR4; 6; 3200; 153.6",
      "field": "Memory: channels; rate; GB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P23"
      ],
      "disclosure_date": "2020",
      "status": "historical shipping",
      "scope": "cpx"
    },
    "cpu.cpx.11": {
      "value": "4/8S; 6 UPI 10.4 GT/s",
      "field": "Sockets / links",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P23"
      ],
      "disclosure_date": "2020",
      "status": "historical shipping",
      "scope": "cpx"
    },
    "cpu.cpx.12": {
      "value": "48 PCIe 3; CXL n/a",
      "field": "PCIe / CXL",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P23"
      ],
      "disclosure_date": "2020",
      "status": "historical shipping",
      "scope": "cpx"
    },
    "cpu.cpx.13": {
      "value": "250 W",
      "field": "TDP",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P23"
      ],
      "disclosure_date": "2020",
      "status": "historical shipping",
      "scope": "cpx"
    },
    "cpu.cpx.14": {
      "value": "AVX-512; BF16; VNNI",
      "field": "Vector / matrix ISA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P23"
      ],
      "disclosure_date": "2020",
      "status": "historical shipping",
      "scope": "cpx"
    },
    "cpu.icl.0": {
      "value": "3rd / 8380",
      "field": "Generation / reference SKU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P24"
      ],
      "disclosure_date": "2021",
      "status": "historical shipping",
      "scope": "icl"
    },
    "cpu.icl.1": {
      "value": "Ice Lake-SP",
      "field": "Codename",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P24"
      ],
      "disclosure_date": "2021",
      "status": "historical shipping",
      "scope": "icl"
    },
    "cpu.icl.2": {
      "value": "2021",
      "field": "GA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P24"
      ],
      "disclosure_date": "2021",
      "status": "historical shipping",
      "scope": "icl"
    },
    "cpu.icl.3": {
      "value": "Historical shipping",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P24"
      ],
      "disclosure_date": "2021",
      "status": "historical shipping",
      "scope": "icl"
    },
    "cpu.icl.4": {
      "value": "Sunny Cove",
      "field": "Core µarch",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P24"
      ],
      "disclosure_date": "2021",
      "status": "historical shipping",
      "scope": "icl"
    },
    "cpu.icl.5": {
      "value": "40 / 80",
      "field": "Cores / threads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P24"
      ],
      "disclosure_date": "2021",
      "status": "historical shipping",
      "scope": "icl"
    },
    "cpu.icl.6": {
      "value": "10 nm",
      "field": "Process per die",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P24"
      ],
      "disclosure_date": "2021",
      "status": "historical shipping",
      "scope": "icl"
    },
    "cpu.icl.7": {
      "value": "Monolithic; mesh",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P24"
      ],
      "disclosure_date": "2021",
      "status": "historical shipping",
      "scope": "icl"
    },
    "cpu.icl.8": {
      "value": "1.25 MB",
      "field": "L2 per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P24"
      ],
      "disclosure_date": "2021",
      "status": "historical shipping",
      "scope": "icl"
    },
    "cpu.icl.9": {
      "value": "60 MB",
      "field": "L3 / domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P24"
      ],
      "disclosure_date": "2021",
      "status": "historical shipping",
      "scope": "icl"
    },
    "cpu.icl.10": {
      "value": "DDR4; 8; 3200; 204.8",
      "field": "Memory: channels; rate; GB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P24"
      ],
      "disclosure_date": "2021",
      "status": "historical shipping",
      "scope": "icl"
    },
    "cpu.icl.11": {
      "value": "2S; 3 UPI 11.2 GT/s",
      "field": "Sockets / links",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P24"
      ],
      "disclosure_date": "2021",
      "status": "historical shipping",
      "scope": "icl"
    },
    "cpu.icl.12": {
      "value": "64 PCIe 4; CXL n/a",
      "field": "PCIe / CXL",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P24"
      ],
      "disclosure_date": "2021",
      "status": "historical shipping",
      "scope": "icl"
    },
    "cpu.icl.13": {
      "value": "270 W",
      "field": "TDP",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P24"
      ],
      "disclosure_date": "2021",
      "status": "historical shipping",
      "scope": "icl"
    },
    "cpu.icl.14": {
      "value": "AVX-512; VNNI",
      "field": "Vector / matrix ISA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05",
        "P24"
      ],
      "disclosure_date": "2021",
      "status": "historical shipping",
      "scope": "icl"
    },
    "cpu.spr.0": {
      "value": "4th / 8490H",
      "field": "Generation / reference SKU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P25",
        "C03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "spr"
    },
    "cpu.spr.1": {
      "value": "Sapphire Rapids",
      "field": "Codename",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P25",
        "C03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "spr"
    },
    "cpu.spr.2": {
      "value": "2023",
      "field": "GA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P25",
        "C03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "spr"
    },
    "cpu.spr.3": {
      "value": "Historical shipping",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P25",
        "C03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "spr"
    },
    "cpu.spr.4": {
      "value": "Golden Cove",
      "field": "Core µarch",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P25",
        "C03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "spr"
    },
    "cpu.spr.5": {
      "value": "60 / 120",
      "field": "Cores / threads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P25",
        "C03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "spr"
    },
    "cpu.spr.6": {
      "value": "Intel 7",
      "field": "Process per die",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P25",
        "C03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "spr"
    },
    "cpu.spr.7": {
      "value": "4 compute tiles; EMIB",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P25",
        "C03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "spr"
    },
    "cpu.spr.8": {
      "value": "2 MB",
      "field": "L2 per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P25",
        "C03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "spr"
    },
    "cpu.spr.9": {
      "value": "112.5 MB",
      "field": "L3 / domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P25",
        "C03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "spr"
    },
    "cpu.spr.10": {
      "value": "DDR5; 8; 4800; 307.2",
      "field": "Memory: channels; rate; GB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P25",
        "C03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "spr"
    },
    "cpu.spr.11": {
      "value": "up to 8S; 4 UPI 16 GT/s",
      "field": "Sockets / links",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P25",
        "C03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "spr"
    },
    "cpu.spr.12": {
      "value": "80 PCIe 5; CXL 1.1",
      "field": "PCIe / CXL",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P25",
        "C03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "spr"
    },
    "cpu.spr.13": {
      "value": "350 W",
      "field": "TDP",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P25",
        "C03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "spr"
    },
    "cpu.spr.14": {
      "value": "AVX-512; AMX INT8/BF16",
      "field": "Vector / matrix ISA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P25",
        "C03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "spr"
    },
    "cpu.max.0": {
      "value": "Xeon Max / 9480",
      "field": "Generation / reference SKU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P13",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "max"
    },
    "cpu.max.1": {
      "value": "Sapphire Rapids HBM",
      "field": "Codename",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P13",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "max"
    },
    "cpu.max.2": {
      "value": "2023",
      "field": "GA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P13",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "max"
    },
    "cpu.max.3": {
      "value": "Historical shipping",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P13",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "max"
    },
    "cpu.max.4": {
      "value": "Golden Cove",
      "field": "Core µarch",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P13",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "max"
    },
    "cpu.max.5": {
      "value": "56 / 112",
      "field": "Cores / threads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P13",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "max"
    },
    "cpu.max.6": {
      "value": "Intel 7",
      "field": "Process per die",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P13",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "max"
    },
    "cpu.max.7": {
      "value": "4 tiles + 4 HBM stacks; EMIB",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P13",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "max"
    },
    "cpu.max.8": {
      "value": "2 MB",
      "field": "L2 per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P13",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "max"
    },
    "cpu.max.9": {
      "value": "112.5 MB",
      "field": "L3 / domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P13",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "max"
    },
    "cpu.max.10": {
      "value": "DDR5; 8; 4800; 307.2 + HBM2e 64 GB ~1000",
      "field": "Memory: channels; rate; GB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P13",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "max"
    },
    "cpu.max.11": {
      "value": "2S; UPI 16 GT/s",
      "field": "Sockets / links",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P13",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "max"
    },
    "cpu.max.12": {
      "value": "80 PCIe 5; CXL 1.1",
      "field": "PCIe / CXL",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P13",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "max"
    },
    "cpu.max.13": {
      "value": "350 W",
      "field": "TDP",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P13",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "max"
    },
    "cpu.max.14": {
      "value": "AVX-512; AMX INT8/BF16",
      "field": "Vector / matrix ISA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P13",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "max"
    },
    "cpu.emr.0": {
      "value": "5th / 8592+",
      "field": "Generation / reference SKU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04",
        "P26"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "emr"
    },
    "cpu.emr.1": {
      "value": "Emerald Rapids",
      "field": "Codename",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04",
        "P26"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "emr"
    },
    "cpu.emr.2": {
      "value": "2023-12",
      "field": "GA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04",
        "P26"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "emr"
    },
    "cpu.emr.3": {
      "value": "Historical shipping",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04",
        "P26"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "emr"
    },
    "cpu.emr.4": {
      "value": "Raptor Cove",
      "field": "Core µarch",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04",
        "P26"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "emr"
    },
    "cpu.emr.5": {
      "value": "64 / 128",
      "field": "Cores / threads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04",
        "P26"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "emr"
    },
    "cpu.emr.6": {
      "value": "Intel 7",
      "field": "Process per die",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04",
        "P26"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "emr"
    },
    "cpu.emr.7": {
      "value": "2 tiles high-end; EMIB",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04",
        "P26"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "emr"
    },
    "cpu.emr.8": {
      "value": "2 MB",
      "field": "L2 per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04",
        "P26"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "emr"
    },
    "cpu.emr.9": {
      "value": "320 MB",
      "field": "L3 / domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04",
        "P26"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "emr"
    },
    "cpu.emr.10": {
      "value": "DDR5; 8; 5600; 358.4",
      "field": "Memory: channels; rate; GB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04",
        "P26"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "emr"
    },
    "cpu.emr.11": {
      "value": "2S; 4 UPI 20 GT/s",
      "field": "Sockets / links",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04",
        "P26"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "emr"
    },
    "cpu.emr.12": {
      "value": "80 PCIe 5; CXL 1.1",
      "field": "PCIe / CXL",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04",
        "P26"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "emr"
    },
    "cpu.emr.13": {
      "value": "350 W",
      "field": "TDP",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04",
        "P26"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "emr"
    },
    "cpu.emr.14": {
      "value": "AVX-512; AMX INT8/BF16",
      "field": "Vector / matrix ISA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04",
        "P26"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "emr"
    },
    "cpu.srf.0": {
      "value": "6 E / 6780E",
      "field": "Generation / reference SKU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P17",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "srf"
    },
    "cpu.srf.1": {
      "value": "Sierra Forest",
      "field": "Codename",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P17",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "srf"
    },
    "cpu.srf.2": {
      "value": "2024-06",
      "field": "GA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P17",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "srf"
    },
    "cpu.srf.3": {
      "value": "Shipping",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P17",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "srf"
    },
    "cpu.srf.4": {
      "value": "Crestmont",
      "field": "Core µarch",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P17",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "srf"
    },
    "cpu.srf.5": {
      "value": "144 / 144",
      "field": "Cores / threads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P17",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "srf"
    },
    "cpu.srf.6": {
      "value": "Intel 3 + Intel 7 I/O",
      "field": "Process per die",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P17",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "srf"
    },
    "cpu.srf.7": {
      "value": "Compute + 2 I/O; EMIB",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P17",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "srf"
    },
    "cpu.srf.8": {
      "value": "4 MB / 4-core cluster",
      "field": "L2 per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P17",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "srf"
    },
    "cpu.srf.9": {
      "value": "108 MB",
      "field": "L3 / domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P17",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "srf"
    },
    "cpu.srf.10": {
      "value": "DDR5; 8; 6400; 409.6",
      "field": "Memory: channels; rate; GB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P17",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "srf"
    },
    "cpu.srf.11": {
      "value": "2S; UPI 24 GT/s",
      "field": "Sockets / links",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P17",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "srf"
    },
    "cpu.srf.12": {
      "value": "88 PCIe 5; CXL 2.0; shared lane budget",
      "field": "PCIe / CXL",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P17",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "srf"
    },
    "cpu.srf.13": {
      "value": "330 W",
      "field": "TDP",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P17",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "srf"
    },
    "cpu.srf.14": {
      "value": "AVX2; VNNI; no AMX",
      "field": "Vector / matrix ISA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P17",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "srf"
    },
    "cpu.gnr.0": {
      "value": "6 P / 6980P",
      "field": "Generation / reference SKU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P16",
        "P18",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gnr"
    },
    "cpu.gnr.1": {
      "value": "Granite Rapids",
      "field": "Codename",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P16",
        "P18",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gnr"
    },
    "cpu.gnr.2": {
      "value": "2024-09",
      "field": "GA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P16",
        "P18",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gnr"
    },
    "cpu.gnr.3": {
      "value": "Shipping",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P16",
        "P18",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gnr"
    },
    "cpu.gnr.4": {
      "value": "Redwood Cove",
      "field": "Core µarch",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P16",
        "P18",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gnr"
    },
    "cpu.gnr.5": {
      "value": "128 / 256",
      "field": "Cores / threads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P16",
        "P18",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gnr"
    },
    "cpu.gnr.6": {
      "value": "Intel 3 + Intel 7 I/O",
      "field": "Process per die",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P16",
        "P18",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gnr"
    },
    "cpu.gnr.7": {
      "value": "3 compute + 2 I/O; EMIB",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P16",
        "P18",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gnr"
    },
    "cpu.gnr.8": {
      "value": "2 MB",
      "field": "L2 per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P16",
        "P18",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gnr"
    },
    "cpu.gnr.9": {
      "value": "504 MB",
      "field": "L3 / domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P16",
        "P18",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gnr"
    },
    "cpu.gnr.10": {
      "value": "DDR5; 12; 6400; 614.4 / MRDIMM 8800; 844.8",
      "field": "Memory: channels; rate; GB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P16",
        "P18",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gnr"
    },
    "cpu.gnr.11": {
      "value": "2S; UPI 24 GT/s",
      "field": "Sockets / links",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P16",
        "P18",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gnr"
    },
    "cpu.gnr.12": {
      "value": "96 PCIe 5; CXL 2.0",
      "field": "PCIe / CXL",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P16",
        "P18",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gnr"
    },
    "cpu.gnr.13": {
      "value": "500 W",
      "field": "TDP",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P16",
        "P18",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gnr"
    },
    "cpu.gnr.14": {
      "value": "AVX-512; AMX INT8/BF16/FP16",
      "field": "Vector / matrix ISA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P16",
        "P18",
        "C12"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gnr"
    },
    "cpu.cwf.0": {
      "value": "6+ / 6990E+",
      "field": "Generation / reference SKU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "P19",
        "E02",
        "E16",
        "P08",
        "P35"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "cwf"
    },
    "cpu.cwf.1": {
      "value": "Clearwater Forest",
      "field": "Codename",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "P19",
        "E02",
        "E16",
        "P08",
        "P35"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "cwf"
    },
    "cpu.cwf.2": {
      "value": "2026-06",
      "field": "GA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "P19",
        "E02",
        "E16",
        "P08",
        "P35"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "cwf"
    },
    "cpu.cwf.3": {
      "value": "Shipping",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "P19",
        "E02",
        "E16",
        "P08",
        "P35"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "cwf"
    },
    "cpu.cwf.4": {
      "value": "Darkmont",
      "field": "Core µarch",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "P19",
        "E02",
        "E16",
        "P08",
        "P35"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "cwf"
    },
    "cpu.cwf.5": {
      "value": "288 / 288",
      "field": "Cores / threads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "P19",
        "E02",
        "E16",
        "P08",
        "P35"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "cwf"
    },
    "cpu.cwf.6": {
      "value": "Intel 18A compute; Intel 3 base; Intel 7 I/O",
      "field": "Process per die",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "P19",
        "E02",
        "E16",
        "P08",
        "P35"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "cwf"
    },
    "cpu.cwf.7": {
      "value": "12 compute + 3 base + 2 I/O; 3D + EMIB",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "P19",
        "E02",
        "E16",
        "P08",
        "P35"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "cwf"
    },
    "cpu.cwf.8": {
      "value": "n/d",
      "field": "L2 per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "P19",
        "E02",
        "E16",
        "P08",
        "P35"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "cwf"
    },
    "cpu.cwf.9": {
      "value": "576 MB",
      "field": "L3 / domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "P19",
        "E02",
        "E16",
        "P08",
        "P35"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "cwf"
    },
    "cpu.cwf.10": {
      "value": "DDR5; 12; 8000; 768",
      "field": "Memory: channels; rate; GB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "P19",
        "E02",
        "E16",
        "P08",
        "P35"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "cwf"
    },
    "cpu.cwf.11": {
      "value": "2S; link details n/d",
      "field": "Sockets / links",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "P19",
        "E02",
        "E16",
        "P08",
        "P35"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "cwf"
    },
    "cpu.cwf.12": {
      "value": "96 PCIe 5; CXL allocation n/d",
      "field": "PCIe / CXL",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "P19",
        "E02",
        "E16",
        "P08",
        "P35"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "cwf"
    },
    "cpu.cwf.13": {
      "value": "450 W",
      "field": "TDP",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "P19",
        "E02",
        "E16",
        "P08",
        "P35"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "cwf"
    },
    "cpu.cwf.14": {
      "value": "AVX2; no AMX",
      "field": "Vector / matrix ISA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "P19",
        "E02",
        "E16",
        "P08",
        "P35"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "cwf"
    },
    "cpu.dmr.0": {
      "value": "Next Xeon",
      "field": "Generation / reference SKU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "dmr"
    },
    "cpu.dmr.1": {
      "value": "Diamond Rapids",
      "field": "Codename",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "dmr"
    },
    "cpu.dmr.2": {
      "value": "n/d",
      "field": "GA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "dmr"
    },
    "cpu.dmr.3": {
      "value": "Disclosed; GA n/d",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "dmr"
    },
    "cpu.dmr.4": {
      "value": "New performance core",
      "field": "Core µarch",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "dmr"
    },
    "cpu.dmr.5": {
      "value": "256 / n/d",
      "field": "Cores / threads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "dmr"
    },
    "cpu.dmr.6": {
      "value": "Intel 18A-P",
      "field": "Process per die",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "dmr"
    },
    "cpu.dmr.7": {
      "value": "Foveros Direct 3D; UCIe-S",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "dmr"
    },
    "cpu.dmr.8": {
      "value": "n/d",
      "field": "L2 per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "dmr"
    },
    "cpu.dmr.9": {
      "value": "1.28 GB",
      "field": "L3 / domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "dmr"
    },
    "cpu.dmr.10": {
      "value": "16; 12800 MT/s; 1638.4 derived",
      "field": "Memory: channels; rate; GB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "dmr"
    },
    "cpu.dmr.11": {
      "value": "n/d",
      "field": "Sockets / links",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "dmr"
    },
    "cpu.dmr.12": {
      "value": "128 PCIe 6; CXL 3.0",
      "field": "PCIe / CXL",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "dmr"
    },
    "cpu.dmr.13": {
      "value": "n/d",
      "field": "TDP",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "dmr"
    },
    "cpu.dmr.14": {
      "value": "APX; enhanced AMX",
      "field": "Vector / matrix ISA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "dmr"
    },
    "accelerators.knl.0": {
      "value": "Xeon Phi 7290",
      "field": "Product",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P28",
        "P05",
        "C13"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "knl"
    },
    "accelerators.knl.1": {
      "value": "Knights Landing",
      "field": "Architecture",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P28",
        "P05",
        "C13"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "knl"
    },
    "accelerators.knl.2": {
      "value": "2016",
      "field": "GA / milestone",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P28",
        "P05",
        "C13"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "knl"
    },
    "accelerators.knl.3": {
      "value": "Historical shipping",
      "field": "Status",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P28",
        "P05",
        "C13"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "knl"
    },
    "accelerators.knl.4": {
      "value": "14 nm",
      "field": "Process",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P28",
        "P05",
        "C13"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "knl"
    },
    "accelerators.knl.5": {
      "value": "CPU + on-package MCDRAM",
      "field": "Dies / packaging",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P28",
        "P05",
        "C13"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "knl"
    },
    "accelerators.knl.6": {
      "value": "72 cores / 288 threads",
      "field": "Compute units",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P28",
        "P05",
        "C13"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "knl"
    },
    "accelerators.knl.7": {
      "value": "n/a",
      "field": "Dense BF16",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P28",
        "P05",
        "C13"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "knl"
    },
    "accelerators.knl.8": {
      "value": "n/a",
      "field": "Dense FP8",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P28",
        "P05",
        "C13"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "knl"
    },
    "accelerators.knl.9": {
      "value": "n/a",
      "field": "Dense FP6 / FP4",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P28",
        "P05",
        "C13"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "knl"
    },
    "accelerators.knl.10": {
      "value": "~3.46 TF / n/a",
      "field": "FP64 vector / matrix",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P28",
        "P05",
        "C13"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "knl"
    },
    "accelerators.knl.11": {
      "value": "MCDRAM; 8; 16; >0.4 measured STREAM; DDR4 separate",
      "field": "Memory: type; stacks; GB; TB/s",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P28",
        "P05",
        "C13"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "knl"
    },
    "accelerators.knl.12": {
      "value": "36 MB distributed L2",
      "field": "LLC / SRAM",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P28",
        "P05",
        "C13"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "knl"
    },
    "accelerators.knl.13": {
      "value": "n/a; optional Omni-Path fabric",
      "field": "Scale-up: links; GB/s per direction; domain",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P28",
        "P05",
        "C13"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "knl"
    },
    "accelerators.knl.14": {
      "value": "Self-hosted; PCIe 3",
      "field": "Host link",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P28",
        "P05",
        "C13"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "knl"
    },
    "accelerators.knl.15": {
      "value": "245 W",
      "field": "Power / cooling",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P28",
        "P05",
        "C13"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "knl"
    },
    "accelerators.knl.16": {
      "value": "Socketed processor",
      "field": "Form factor",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P28",
        "P05",
        "C13"
      ],
      "disclosure_date": "2016",
      "status": "historical shipping",
      "scope": "knl"
    },
    "accelerators.gaudi1.0": {
      "value": "Gaudi / HL-205",
      "field": "Product",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E14",
        "P30",
        "P37"
      ],
      "disclosure_date": "2019–2021",
      "status": "historical shipping",
      "scope": "gaudi1"
    },
    "accelerators.gaudi1.1": {
      "value": "Gaudi",
      "field": "Architecture",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E14",
        "P30",
        "P37"
      ],
      "disclosure_date": "2019–2021",
      "status": "historical shipping",
      "scope": "gaudi1"
    },
    "accelerators.gaudi1.2": {
      "value": "2021 AWS DL1",
      "field": "GA / milestone",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E14",
        "P30",
        "P37"
      ],
      "disclosure_date": "2019–2021",
      "status": "historical shipping",
      "scope": "gaudi1"
    },
    "accelerators.gaudi1.3": {
      "value": "Historical shipping",
      "field": "Status",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E14",
        "P30",
        "P37"
      ],
      "disclosure_date": "2019–2021",
      "status": "historical shipping",
      "scope": "gaudi1"
    },
    "accelerators.gaudi1.4": {
      "value": "16 nm",
      "field": "Process",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E14",
        "P30",
        "P37"
      ],
      "disclosure_date": "2019–2021",
      "status": "historical shipping",
      "scope": "gaudi1"
    },
    "accelerators.gaudi1.5": {
      "value": "1 compute die + HBM",
      "field": "Dies / packaging",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E14",
        "P30",
        "P37"
      ],
      "disclosure_date": "2019–2021",
      "status": "historical shipping",
      "scope": "gaudi1"
    },
    "accelerators.gaudi1.6": {
      "value": "8 TPC; MME",
      "field": "Compute units",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E14",
        "P30",
        "P37"
      ],
      "disclosure_date": "2019–2021",
      "status": "historical shipping",
      "scope": "gaudi1"
    },
    "accelerators.gaudi1.7": {
      "value": "n/d",
      "field": "Dense BF16",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E14",
        "P30",
        "P37"
      ],
      "disclosure_date": "2019–2021",
      "status": "historical shipping",
      "scope": "gaudi1"
    },
    "accelerators.gaudi1.8": {
      "value": "n/a",
      "field": "Dense FP8",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E14",
        "P30",
        "P37"
      ],
      "disclosure_date": "2019–2021",
      "status": "historical shipping",
      "scope": "gaudi1"
    },
    "accelerators.gaudi1.9": {
      "value": "n/a",
      "field": "Dense FP6 / FP4",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E14",
        "P30",
        "P37"
      ],
      "disclosure_date": "2019–2021",
      "status": "historical shipping",
      "scope": "gaudi1"
    },
    "accelerators.gaudi1.10": {
      "value": "n/a",
      "field": "FP64 vector / matrix",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E14",
        "P30",
        "P37"
      ],
      "disclosure_date": "2019–2021",
      "status": "historical shipping",
      "scope": "gaudi1"
    },
    "accelerators.gaudi1.11": {
      "value": "HBM2; n/d; 32; ~1",
      "field": "Memory: type; stacks; GB; TB/s",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E14",
        "P30",
        "P37"
      ],
      "disclosure_date": "2019–2021",
      "status": "historical shipping",
      "scope": "gaudi1"
    },
    "accelerators.gaudi1.12": {
      "value": "n/d",
      "field": "LLC / SRAM",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E14",
        "P30",
        "P37"
      ],
      "disclosure_date": "2019–2021",
      "status": "historical shipping",
      "scope": "gaudi1"
    },
    "accelerators.gaudi1.13": {
      "value": "10 x 100GbE; 125 total; 8-device server",
      "field": "Scale-up: links; GB/s per direction; domain",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E14",
        "P30",
        "P37"
      ],
      "disclosure_date": "2019–2021",
      "status": "historical shipping",
      "scope": "gaudi1"
    },
    "accelerators.gaudi1.14": {
      "value": "PCIe 4",
      "field": "Host link",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E14",
        "P30",
        "P37"
      ],
      "disclosure_date": "2019–2021",
      "status": "historical shipping",
      "scope": "gaudi1"
    },
    "accelerators.gaudi1.15": {
      "value": "n/d",
      "field": "Power / cooling",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E14",
        "P30",
        "P37"
      ],
      "disclosure_date": "2019–2021",
      "status": "historical shipping",
      "scope": "gaudi1"
    },
    "accelerators.gaudi1.16": {
      "value": "OAM",
      "field": "Form factor",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E14",
        "P30",
        "P37"
      ],
      "disclosure_date": "2019–2021",
      "status": "historical shipping",
      "scope": "gaudi1"
    },
    "accelerators.gaudi2.0": {
      "value": "Gaudi 2",
      "field": "Product",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "P30",
        "P37"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "gaudi2"
    },
    "accelerators.gaudi2.1": {
      "value": "Gaudi 2",
      "field": "Architecture",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "P30",
        "P37"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "gaudi2"
    },
    "accelerators.gaudi2.2": {
      "value": "2022",
      "field": "GA / milestone",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "P30",
        "P37"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "gaudi2"
    },
    "accelerators.gaudi2.3": {
      "value": "Historical shipping",
      "field": "Status",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "P30",
        "P37"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "gaudi2"
    },
    "accelerators.gaudi2.4": {
      "value": "7 nm",
      "field": "Process",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "P30",
        "P37"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "gaudi2"
    },
    "accelerators.gaudi2.5": {
      "value": "1 compute die + HBM",
      "field": "Dies / packaging",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "P30",
        "P37"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "gaudi2"
    },
    "accelerators.gaudi2.6": {
      "value": "24 TPC / 2 MME",
      "field": "Compute units",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "P30",
        "P37"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "gaudi2"
    },
    "accelerators.gaudi2.7": {
      "value": "432 TF",
      "field": "Dense BF16",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "P30",
        "P37"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "gaudi2"
    },
    "accelerators.gaudi2.8": {
      "value": "865 TF",
      "field": "Dense FP8",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "P30",
        "P37"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "gaudi2"
    },
    "accelerators.gaudi2.9": {
      "value": "n/a",
      "field": "Dense FP6 / FP4",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "P30",
        "P37"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "gaudi2"
    },
    "accelerators.gaudi2.10": {
      "value": "n/a",
      "field": "FP64 vector / matrix",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "P30",
        "P37"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "gaudi2"
    },
    "accelerators.gaudi2.11": {
      "value": "HBM2e; 6; 96; 2.46",
      "field": "Memory: type; stacks; GB; TB/s",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "P30",
        "P37"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "gaudi2"
    },
    "accelerators.gaudi2.12": {
      "value": "48 MB SRAM",
      "field": "LLC / SRAM",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "P30",
        "P37"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "gaudi2"
    },
    "accelerators.gaudi2.13": {
      "value": "24 x 100GbE; 300 total; 8-device server",
      "field": "Scale-up: links; GB/s per direction; domain",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "P30",
        "P37"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "gaudi2"
    },
    "accelerators.gaudi2.14": {
      "value": "PCIe 4 x16",
      "field": "Host link",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "P30",
        "P37"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "gaudi2"
    },
    "accelerators.gaudi2.15": {
      "value": "600 W",
      "field": "Power / cooling",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "P30",
        "P37"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "gaudi2"
    },
    "accelerators.gaudi2.16": {
      "value": "OAM",
      "field": "Form factor",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "P30",
        "P37"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "gaudi2"
    },
    "accelerators.gaudi3.0": {
      "value": "Gaudi 3 / HL-325L",
      "field": "Product",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "E05"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi3"
    },
    "accelerators.gaudi3.1": {
      "value": "Gaudi 3",
      "field": "Architecture",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "E05"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi3"
    },
    "accelerators.gaudi3.2": {
      "value": "2024",
      "field": "GA / milestone",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "E05"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi3"
    },
    "accelerators.gaudi3.3": {
      "value": "Shipping",
      "field": "Status",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "E05"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi3"
    },
    "accelerators.gaudi3.4": {
      "value": "5 nm",
      "field": "Process",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "E05"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi3"
    },
    "accelerators.gaudi3.5": {
      "value": "2 compute dies + HBM",
      "field": "Dies / packaging",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "E05"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi3"
    },
    "accelerators.gaudi3.6": {
      "value": "64 TPC / 8 MME",
      "field": "Compute units",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "E05"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi3"
    },
    "accelerators.gaudi3.7": {
      "value": "1678 TF",
      "field": "Dense BF16",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "E05"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi3"
    },
    "accelerators.gaudi3.8": {
      "value": "1678 TF",
      "field": "Dense FP8",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "E05"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi3"
    },
    "accelerators.gaudi3.9": {
      "value": "n/a",
      "field": "Dense FP6 / FP4",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "E05"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi3"
    },
    "accelerators.gaudi3.10": {
      "value": "n/a",
      "field": "FP64 vector / matrix",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "E05"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi3"
    },
    "accelerators.gaudi3.11": {
      "value": "HBM2e; 8; 128; 3.7",
      "field": "Memory: type; stacks; GB; TB/s",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "E05"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi3"
    },
    "accelerators.gaudi3.12": {
      "value": "96 MB SRAM",
      "field": "LLC / SRAM",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "E05"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi3"
    },
    "accelerators.gaudi3.13": {
      "value": "24 x 200GbE; 600 total; 8-device server",
      "field": "Scale-up: links; GB/s per direction; domain",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "E05"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi3"
    },
    "accelerators.gaudi3.14": {
      "value": "PCIe 5 x16",
      "field": "Host link",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "E05"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi3"
    },
    "accelerators.gaudi3.15": {
      "value": "Up to 900 W; air/liquid variants",
      "field": "Power / cooling",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "E05"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi3"
    },
    "accelerators.gaudi3.16": {
      "value": "OAM",
      "field": "Form factor",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P02",
        "E05"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi3"
    },
    "accelerators.pvc.0": {
      "value": "GPU Max 1550",
      "field": "Product",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "C03",
        "P27",
        "P11"
      ],
      "disclosure_date": "2022–2023",
      "status": "historical shipping",
      "scope": "pvc"
    },
    "accelerators.pvc.1": {
      "value": "Ponte Vecchio / Xe-HPC",
      "field": "Architecture",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "C03",
        "P27",
        "P11"
      ],
      "disclosure_date": "2022–2023",
      "status": "historical shipping",
      "scope": "pvc"
    },
    "accelerators.pvc.2": {
      "value": "2023",
      "field": "GA / milestone",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "C03",
        "P27",
        "P11"
      ],
      "disclosure_date": "2022–2023",
      "status": "historical shipping",
      "scope": "pvc"
    },
    "accelerators.pvc.3": {
      "value": "Historical shipping",
      "field": "Status",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "C03",
        "P27",
        "P11"
      ],
      "disclosure_date": "2022–2023",
      "status": "historical shipping",
      "scope": "pvc"
    },
    "accelerators.pvc.4": {
      "value": "TSMC N5 compute; Intel 7 base; TSMC N7 link",
      "field": "Process",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "C03",
        "P27",
        "P11"
      ],
      "disclosure_date": "2022–2023",
      "status": "historical shipping",
      "scope": "pvc"
    },
    "accelerators.pvc.5": {
      "value": "47-tile integration; EMIB + Foveros",
      "field": "Dies / packaging",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "C03",
        "P27",
        "P11"
      ],
      "disclosure_date": "2022–2023",
      "status": "historical shipping",
      "scope": "pvc"
    },
    "accelerators.pvc.6": {
      "value": "128 Xe cores / 1024 XMX",
      "field": "Compute units",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "C03",
        "P27",
        "P11"
      ],
      "disclosure_date": "2022–2023",
      "status": "historical shipping",
      "scope": "pvc"
    },
    "accelerators.pvc.7": {
      "value": "839 TF",
      "field": "Dense BF16",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "C03",
        "P27",
        "P11"
      ],
      "disclosure_date": "2022–2023",
      "status": "historical shipping",
      "scope": "pvc"
    },
    "accelerators.pvc.8": {
      "value": "n/a",
      "field": "Dense FP8",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "C03",
        "P27",
        "P11"
      ],
      "disclosure_date": "2022–2023",
      "status": "historical shipping",
      "scope": "pvc"
    },
    "accelerators.pvc.9": {
      "value": "n/a",
      "field": "Dense FP6 / FP4",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "C03",
        "P27",
        "P11"
      ],
      "disclosure_date": "2022–2023",
      "status": "historical shipping",
      "scope": "pvc"
    },
    "accelerators.pvc.10": {
      "value": "52 TF native; split n/d",
      "field": "FP64 vector / matrix",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "C03",
        "P27",
        "P11"
      ],
      "disclosure_date": "2022–2023",
      "status": "historical shipping",
      "scope": "pvc"
    },
    "accelerators.pvc.11": {
      "value": "HBM2e; 8; 128; 3.2",
      "field": "Memory: type; stacks; GB; TB/s",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "C03",
        "P27",
        "P11"
      ],
      "disclosure_date": "2022–2023",
      "status": "historical shipping",
      "scope": "pvc"
    },
    "accelerators.pvc.12": {
      "value": "408 MB L2",
      "field": "LLC / SRAM",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "C03",
        "P27",
        "P11"
      ],
      "disclosure_date": "2022–2023",
      "status": "historical shipping",
      "scope": "pvc"
    },
    "accelerators.pvc.13": {
      "value": "Xe Link; 318 on Lenovo reference; 4-GPU domain",
      "field": "Scale-up: links; GB/s per direction; domain",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "C03",
        "P27",
        "P11"
      ],
      "disclosure_date": "2022–2023",
      "status": "historical shipping",
      "scope": "pvc"
    },
    "accelerators.pvc.14": {
      "value": "PCIe 5 x16",
      "field": "Host link",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "C03",
        "P27",
        "P11"
      ],
      "disclosure_date": "2022–2023",
      "status": "historical shipping",
      "scope": "pvc"
    },
    "accelerators.pvc.15": {
      "value": "600 W; platform-dependent",
      "field": "Power / cooling",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "C03",
        "P27",
        "P11"
      ],
      "disclosure_date": "2022–2023",
      "status": "historical shipping",
      "scope": "pvc"
    },
    "accelerators.pvc.16": {
      "value": "OAM",
      "field": "Form factor",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "C03",
        "P27",
        "P11"
      ],
      "disclosure_date": "2022–2023",
      "status": "historical shipping",
      "scope": "pvc"
    },
    "accelerators.flex.0": {
      "value": "GPU Flex 170",
      "field": "Product",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P29",
        "P11"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "flex"
    },
    "accelerators.flex.1": {
      "value": "Xe-HPG",
      "field": "Architecture",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P29",
        "P11"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "flex"
    },
    "accelerators.flex.2": {
      "value": "2022",
      "field": "GA / milestone",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P29",
        "P11"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "flex"
    },
    "accelerators.flex.3": {
      "value": "Historical shipping",
      "field": "Status",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P29",
        "P11"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "flex"
    },
    "accelerators.flex.4": {
      "value": "TSMC N6",
      "field": "Process",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P29",
        "P11"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "flex"
    },
    "accelerators.flex.5": {
      "value": "Single GPU",
      "field": "Dies / packaging",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P29",
        "P11"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "flex"
    },
    "accelerators.flex.6": {
      "value": "32 Xe cores",
      "field": "Compute units",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P29",
        "P11"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "flex"
    },
    "accelerators.flex.7": {
      "value": "n/d",
      "field": "Dense BF16",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P29",
        "P11"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "flex"
    },
    "accelerators.flex.8": {
      "value": "n/a",
      "field": "Dense FP8",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P29",
        "P11"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "flex"
    },
    "accelerators.flex.9": {
      "value": "n/a",
      "field": "Dense FP6 / FP4",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P29",
        "P11"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "flex"
    },
    "accelerators.flex.10": {
      "value": "n/d",
      "field": "FP64 vector / matrix",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P29",
        "P11"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "flex"
    },
    "accelerators.flex.11": {
      "value": "GDDR6; n/a; 16; 0.576",
      "field": "Memory: type; stacks; GB; TB/s",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P29",
        "P11"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "flex"
    },
    "accelerators.flex.12": {
      "value": "n/d",
      "field": "LLC / SRAM",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P29",
        "P11"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "flex"
    },
    "accelerators.flex.13": {
      "value": "n/a",
      "field": "Scale-up: links; GB/s per direction; domain",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P29",
        "P11"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "flex"
    },
    "accelerators.flex.14": {
      "value": "PCIe 4 x16",
      "field": "Host link",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P29",
        "P11"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "flex"
    },
    "accelerators.flex.15": {
      "value": "150 W; passive air",
      "field": "Power / cooling",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P29",
        "P11"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "flex"
    },
    "accelerators.flex.16": {
      "value": "PCIe",
      "field": "Form factor",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "P29",
        "P11"
      ],
      "disclosure_date": "2022",
      "status": "historical shipping",
      "scope": "flex"
    },
    "accelerators.crescent.0": {
      "value": "Crescent Island",
      "field": "Product",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E01",
        "E03"
      ],
      "disclosure_date": "2025–2026",
      "status": "announced",
      "scope": "crescent"
    },
    "accelerators.crescent.1": {
      "value": "Xe3P",
      "field": "Architecture",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E01",
        "E03"
      ],
      "disclosure_date": "2025–2026",
      "status": "announced",
      "scope": "crescent"
    },
    "accelerators.crescent.2": {
      "value": "n/d",
      "field": "GA / milestone",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E01",
        "E03"
      ],
      "disclosure_date": "2025–2026",
      "status": "announced",
      "scope": "crescent"
    },
    "accelerators.crescent.3": {
      "value": "Disclosed; GA n/d",
      "field": "Status",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E01",
        "E03"
      ],
      "disclosure_date": "2025–2026",
      "status": "announced",
      "scope": "crescent"
    },
    "accelerators.crescent.4": {
      "value": "n/d",
      "field": "Process",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E01",
        "E03"
      ],
      "disclosure_date": "2025–2026",
      "status": "announced",
      "scope": "crescent"
    },
    "accelerators.crescent.5": {
      "value": "n/d",
      "field": "Dies / packaging",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E01",
        "E03"
      ],
      "disclosure_date": "2025–2026",
      "status": "announced",
      "scope": "crescent"
    },
    "accelerators.crescent.6": {
      "value": "32 Xe cores / 256 XMX",
      "field": "Compute units",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E01",
        "E03"
      ],
      "disclosure_date": "2025–2026",
      "status": "announced",
      "scope": "crescent"
    },
    "accelerators.crescent.7": {
      "value": "n/d",
      "field": "Dense BF16",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E01",
        "E03"
      ],
      "disclosure_date": "2025–2026",
      "status": "announced",
      "scope": "crescent"
    },
    "accelerators.crescent.8": {
      "value": "n/d",
      "field": "Dense FP8",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E01",
        "E03"
      ],
      "disclosure_date": "2025–2026",
      "status": "announced",
      "scope": "crescent"
    },
    "accelerators.crescent.9": {
      "value": "n/d",
      "field": "Dense FP6 / FP4",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E01",
        "E03"
      ],
      "disclosure_date": "2025–2026",
      "status": "announced",
      "scope": "crescent"
    },
    "accelerators.crescent.10": {
      "value": "n/d",
      "field": "FP64 vector / matrix",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E01",
        "E03"
      ],
      "disclosure_date": "2025–2026",
      "status": "announced",
      "scope": "crescent"
    },
    "accelerators.crescent.11": {
      "value": "LPDDR5X; n/a; up to 480; n/d",
      "field": "Memory: type; stacks; GB; TB/s",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E01",
        "E03"
      ],
      "disclosure_date": "2025–2026",
      "status": "announced",
      "scope": "crescent"
    },
    "accelerators.crescent.12": {
      "value": "n/d",
      "field": "LLC / SRAM",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E01",
        "E03"
      ],
      "disclosure_date": "2025–2026",
      "status": "announced",
      "scope": "crescent"
    },
    "accelerators.crescent.13": {
      "value": "n/d",
      "field": "Scale-up: links; GB/s per direction; domain",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E01",
        "E03"
      ],
      "disclosure_date": "2025–2026",
      "status": "announced",
      "scope": "crescent"
    },
    "accelerators.crescent.14": {
      "value": "PCIe; generation n/d",
      "field": "Host link",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E01",
        "E03"
      ],
      "disclosure_date": "2025–2026",
      "status": "announced",
      "scope": "crescent"
    },
    "accelerators.crescent.15": {
      "value": "350 W; air",
      "field": "Power / cooling",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E01",
        "E03"
      ],
      "disclosure_date": "2025–2026",
      "status": "announced",
      "scope": "crescent"
    },
    "accelerators.crescent.16": {
      "value": "PCIe",
      "field": "Form factor",
      "basis": "Per reference package/card; dense matrix peak; FMA=2; memory decimal TB/s; fabric GB/s per direction, all ports unless labelled; Gaudi 3 whitepaper revision 1678 TF",
      "source": [
        "E01",
        "E03"
      ],
      "disclosure_date": "2025–2026",
      "status": "announced",
      "scope": "crescent"
    },
    "network.e810.0": {
      "value": "E810",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "e810"
    },
    "network.e810.1": {
      "value": "2019",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "e810"
    },
    "network.e810.2": {
      "value": "Historical shipping",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "e810"
    },
    "network.e810.3": {
      "value": "Ethernet NIC",
      "field": "Class",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "e810"
    },
    "network.e810.4": {
      "value": "Up to 100GbE; card-dependent",
      "field": "Ports × speed",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "e810"
    },
    "network.e810.5": {
      "value": "25G NRZ",
      "field": "SerDes",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "e810"
    },
    "network.e810.6": {
      "value": "PCIe 4",
      "field": "Host interface",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "e810"
    },
    "network.e810.7": {
      "value": "DDP pipeline profiles",
      "field": "Programmable engine",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "e810"
    },
    "network.e810.8": {
      "value": "n/a",
      "field": "Embedded CPU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "e810"
    },
    "network.e810.9": {
      "value": "n/d",
      "field": "On-card memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "e810"
    },
    "network.e810.10": {
      "value": "iWARP / RoCEv2",
      "field": "Transport / RDMA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "e810"
    },
    "network.e810.11": {
      "value": "Protocol / driver-dependent",
      "field": "Congestion control",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "e810"
    },
    "network.e810.12": {
      "value": "Virtualization, RSS, timing",
      "field": "Key offloads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "e810"
    },
    "network.e810.13": {
      "value": "n/d",
      "field": "Power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14"
      ],
      "disclosure_date": "2019",
      "status": "historical shipping",
      "scope": "e810"
    },
    "network.e830.0": {
      "value": "E830-CQDA2",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "e830"
    },
    "network.e830.1": {
      "value": "2025",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "e830"
    },
    "network.e830.2": {
      "value": "Shipping",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "e830"
    },
    "network.e830.3": {
      "value": "Ethernet NIC",
      "field": "Class",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "e830"
    },
    "network.e830.4": {
      "value": "2 x 100GbE",
      "field": "Ports × speed",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "e830"
    },
    "network.e830.5": {
      "value": "50G PAM4",
      "field": "SerDes",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "e830"
    },
    "network.e830.6": {
      "value": "PCIe 5 x8 / PCIe 4 x16",
      "field": "Host interface",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "e830"
    },
    "network.e830.7": {
      "value": "DDP / packet classification",
      "field": "Programmable engine",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "e830"
    },
    "network.e830.8": {
      "value": "n/a",
      "field": "Embedded CPU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "e830"
    },
    "network.e830.9": {
      "value": "n/d",
      "field": "On-card memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "e830"
    },
    "network.e830.10": {
      "value": "Ethernet; RDMA SKU-dependent",
      "field": "Transport / RDMA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "e830"
    },
    "network.e830.11": {
      "value": "n/d",
      "field": "Congestion control",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "e830"
    },
    "network.e830.12": {
      "value": "Packet processing, timing, telemetry",
      "field": "Key offloads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "e830"
    },
    "network.e830.13": {
      "value": "n/d",
      "field": "Power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "e830"
    },
    "network.e835.0": {
      "value": "E835",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "e835"
    },
    "network.e835.1": {
      "value": "2026-06",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "e835"
    },
    "network.e835.2": {
      "value": "Shipping",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "e835"
    },
    "network.e835.3": {
      "value": "Ethernet NIC",
      "field": "Class",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "e835"
    },
    "network.e835.4": {
      "value": "1 x 200 / 2 x 100GbE; variants",
      "field": "Ports × speed",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "e835"
    },
    "network.e835.5": {
      "value": "n/d",
      "field": "SerDes",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "e835"
    },
    "network.e835.6": {
      "value": "n/d",
      "field": "Host interface",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "e835"
    },
    "network.e835.7": {
      "value": "Configurable ports / packet processing",
      "field": "Programmable engine",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "e835"
    },
    "network.e835.8": {
      "value": "n/a",
      "field": "Embedded CPU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "e835"
    },
    "network.e835.9": {
      "value": "n/d",
      "field": "On-card memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "e835"
    },
    "network.e835.10": {
      "value": "iWARP + RoCEv2",
      "field": "Transport / RDMA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "e835"
    },
    "network.e835.11": {
      "value": "n/d",
      "field": "Congestion control",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "e835"
    },
    "network.e835.12": {
      "value": "RDMA, timing, security",
      "field": "Key offloads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "e835"
    },
    "network.e835.13": {
      "value": "n/d",
      "field": "Power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "e835"
    },
    "network.ipu.0": {
      "value": "IPU E2100-CCQDA2",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P10",
        "E15",
        "P32"
      ],
      "disclosure_date": "2023–2024",
      "status": "shipping",
      "scope": "ipu"
    },
    "network.ipu.1": {
      "value": "2023–2024 documentation",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P10",
        "E15",
        "P32"
      ],
      "disclosure_date": "2023–2024",
      "status": "shipping",
      "scope": "ipu"
    },
    "network.ipu.2": {
      "value": "Shipping",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P10",
        "E15",
        "P32"
      ],
      "disclosure_date": "2023–2024",
      "status": "shipping",
      "scope": "ipu"
    },
    "network.ipu.3": {
      "value": "ASIC IPU",
      "field": "Class",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P10",
        "E15",
        "P32"
      ],
      "disclosure_date": "2023–2024",
      "status": "shipping",
      "scope": "ipu"
    },
    "network.ipu.4": {
      "value": "1 x 200 / 2 x 100GbE",
      "field": "Ports × speed",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P10",
        "E15",
        "P32"
      ],
      "disclosure_date": "2023–2024",
      "status": "shipping",
      "scope": "ipu"
    },
    "network.ipu.5": {
      "value": "50G PAM4 / 25G NRZ",
      "field": "SerDes",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P10",
        "E15",
        "P32"
      ],
      "disclosure_date": "2023–2024",
      "status": "shipping",
      "scope": "ipu"
    },
    "network.ipu.6": {
      "value": "PCIe 4 x16",
      "field": "Host interface",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P10",
        "E15",
        "P32"
      ],
      "disclosure_date": "2023–2024",
      "status": "shipping",
      "scope": "ipu"
    },
    "network.ipu.7": {
      "value": "P4 pipeline",
      "field": "Programmable engine",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P10",
        "E15",
        "P32"
      ],
      "disclosure_date": "2023–2024",
      "status": "shipping",
      "scope": "ipu"
    },
    "network.ipu.8": {
      "value": "16 Arm Neoverse N1",
      "field": "Embedded CPU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P10",
        "E15",
        "P32"
      ],
      "disclosure_date": "2023–2024",
      "status": "shipping",
      "scope": "ipu"
    },
    "network.ipu.9": {
      "value": "48 GB LPDDR4x; 32 MB SLC",
      "field": "On-card memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P10",
        "E15",
        "P32"
      ],
      "disclosure_date": "2023–2024",
      "status": "shipping",
      "scope": "ipu"
    },
    "network.ipu.10": {
      "value": "Ethernet; programmable storage transport",
      "field": "Transport / RDMA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P10",
        "E15",
        "P32"
      ],
      "disclosure_date": "2023–2024",
      "status": "shipping",
      "scope": "ipu"
    },
    "network.ipu.11": {
      "value": "Traffic shaping; implementation-specific",
      "field": "Congestion control",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P10",
        "E15",
        "P32"
      ],
      "disclosure_date": "2023–2024",
      "status": "shipping",
      "scope": "ipu"
    },
    "network.ipu.12": {
      "value": "NVMe, IPsec, crypto, compression, isolation",
      "field": "Key offloads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P10",
        "E15",
        "P32"
      ],
      "disclosure_date": "2023–2024",
      "status": "shipping",
      "scope": "ipu"
    },
    "network.ipu.13": {
      "value": "n/d",
      "field": "Power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P10",
        "E15",
        "P32"
      ],
      "disclosure_date": "2023–2024",
      "status": "shipping",
      "scope": "ipu"
    },
    "network.gaudinic.0": {
      "value": "Gaudi 3 integrated NIC",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudinic"
    },
    "network.gaudinic.1": {
      "value": "2024",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudinic"
    },
    "network.gaudinic.2": {
      "value": "Shipping",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudinic"
    },
    "network.gaudinic.3": {
      "value": "On-accelerator fabric",
      "field": "Class",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudinic"
    },
    "network.gaudinic.4": {
      "value": "24 x 200GbE",
      "field": "Ports × speed",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudinic"
    },
    "network.gaudinic.5": {
      "value": "48 x 112G PAM4",
      "field": "SerDes",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudinic"
    },
    "network.gaudinic.6": {
      "value": "Internal to accelerator",
      "field": "Host interface",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudinic"
    },
    "network.gaudinic.7": {
      "value": "Communication engines",
      "field": "Programmable engine",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudinic"
    },
    "network.gaudinic.8": {
      "value": "n/a",
      "field": "Embedded CPU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudinic"
    },
    "network.gaudinic.9": {
      "value": "Uses accelerator memory",
      "field": "On-card memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudinic"
    },
    "network.gaudinic.10": {
      "value": "RoCE",
      "field": "Transport / RDMA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudinic"
    },
    "network.gaudinic.11": {
      "value": "Ethernet fabric configuration",
      "field": "Congestion control",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudinic"
    },
    "network.gaudinic.12": {
      "value": "Device RDMA and collectives",
      "field": "Key offloads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudinic"
    },
    "network.gaudinic.13": {
      "value": "Included in accelerator power",
      "field": "Power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudinic"
    },
    "links.pcie3.0": {
      "value": "PCIe 3",
      "field": "Interconnect",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05"
      ],
      "disclosure_date": "2015",
      "status": "standard",
      "scope": "pcie3"
    },
    "links.pcie3.1": {
      "value": "2010s",
      "field": "Year / generation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05"
      ],
      "disclosure_date": "2015",
      "status": "standard",
      "scope": "pcie3"
    },
    "links.pcie3.2": {
      "value": "8 GT/s",
      "field": "Lane rate",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05"
      ],
      "disclosure_date": "2015",
      "status": "standard",
      "scope": "pcie3"
    },
    "links.pcie3.3": {
      "value": "16",
      "field": "Lanes / link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05"
      ],
      "disclosure_date": "2015",
      "status": "standard",
      "scope": "pcie3"
    },
    "links.pcie3.4": {
      "value": "15.75",
      "field": "GB/s per link per direction",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05"
      ],
      "disclosure_date": "2015",
      "status": "standard",
      "scope": "pcie3"
    },
    "links.pcie3.5": {
      "value": "Platform-dependent",
      "field": "Links / device",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05"
      ],
      "disclosure_date": "2015",
      "status": "standard",
      "scope": "pcie3"
    },
    "links.pcie3.6": {
      "value": "Root / switch tree",
      "field": "Topology",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05"
      ],
      "disclosure_date": "2015",
      "status": "standard",
      "scope": "pcie3"
    },
    "links.pcie3.7": {
      "value": "n/a",
      "field": "Domain limit",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05"
      ],
      "disclosure_date": "2015",
      "status": "standard",
      "scope": "pcie3"
    },
    "links.pcie3.8": {
      "value": "I/O; no general cache coherence",
      "field": "Coherence / semantics",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P05"
      ],
      "disclosure_date": "2015",
      "status": "standard",
      "scope": "pcie3"
    },
    "links.pcie4.0": {
      "value": "PCIe 4",
      "field": "Interconnect",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02",
        "P24"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "pcie4"
    },
    "links.pcie4.1": {
      "value": "Ice Lake / Gaudi 2",
      "field": "Year / generation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02",
        "P24"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "pcie4"
    },
    "links.pcie4.2": {
      "value": "16 GT/s",
      "field": "Lane rate",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02",
        "P24"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "pcie4"
    },
    "links.pcie4.3": {
      "value": "16",
      "field": "Lanes / link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02",
        "P24"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "pcie4"
    },
    "links.pcie4.4": {
      "value": "31.51",
      "field": "GB/s per link per direction",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02",
        "P24"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "pcie4"
    },
    "links.pcie4.5": {
      "value": "Platform-dependent",
      "field": "Links / device",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02",
        "P24"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "pcie4"
    },
    "links.pcie4.6": {
      "value": "Root / switch tree",
      "field": "Topology",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02",
        "P24"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "pcie4"
    },
    "links.pcie4.7": {
      "value": "n/a",
      "field": "Domain limit",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02",
        "P24"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "pcie4"
    },
    "links.pcie4.8": {
      "value": "I/O DMA",
      "field": "Coherence / semantics",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02",
        "P24"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "pcie4"
    },
    "links.pcie5.0": {
      "value": "PCIe 5",
      "field": "Interconnect",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "shipping",
      "scope": "pcie5"
    },
    "links.pcie5.1": {
      "value": "Sapphire / Gaudi 3",
      "field": "Year / generation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "shipping",
      "scope": "pcie5"
    },
    "links.pcie5.2": {
      "value": "32 GT/s",
      "field": "Lane rate",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "shipping",
      "scope": "pcie5"
    },
    "links.pcie5.3": {
      "value": "16",
      "field": "Lanes / link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "shipping",
      "scope": "pcie5"
    },
    "links.pcie5.4": {
      "value": "63.02",
      "field": "GB/s per link per direction",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "shipping",
      "scope": "pcie5"
    },
    "links.pcie5.5": {
      "value": "Platform-dependent",
      "field": "Links / device",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "shipping",
      "scope": "pcie5"
    },
    "links.pcie5.6": {
      "value": "Root / switch tree",
      "field": "Topology",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "shipping",
      "scope": "pcie5"
    },
    "links.pcie5.7": {
      "value": "n/a",
      "field": "Domain limit",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "shipping",
      "scope": "pcie5"
    },
    "links.pcie5.8": {
      "value": "I/O; CXL is a separate protocol",
      "field": "Coherence / semantics",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02",
        "P03"
      ],
      "disclosure_date": "2023",
      "status": "shipping",
      "scope": "pcie5"
    },
    "links.cxl.0": {
      "value": "CXL 1.1 → 2.0 → 3.0",
      "field": "Interconnect",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "C12",
        "E01",
        "R04"
      ],
      "disclosure_date": "2023–2026",
      "status": "mixed",
      "scope": "cxl"
    },
    "links.cxl.1": {
      "value": "SPR → Xeon 6 → Diamond",
      "field": "Year / generation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "C12",
        "E01",
        "R04"
      ],
      "disclosure_date": "2023–2026",
      "status": "mixed",
      "scope": "cxl"
    },
    "links.cxl.2": {
      "value": "PCIe PHY generation-dependent",
      "field": "Lane rate",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "C12",
        "E01",
        "R04"
      ],
      "disclosure_date": "2023–2026",
      "status": "mixed",
      "scope": "cxl"
    },
    "links.cxl.3": {
      "value": "n/d",
      "field": "Lanes / link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "C12",
        "E01",
        "R04"
      ],
      "disclosure_date": "2023–2026",
      "status": "mixed",
      "scope": "cxl"
    },
    "links.cxl.4": {
      "value": "n/d",
      "field": "GB/s per link per direction",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "C12",
        "E01",
        "R04"
      ],
      "disclosure_date": "2023–2026",
      "status": "mixed",
      "scope": "cxl"
    },
    "links.cxl.5": {
      "value": "Shared physical lane budget",
      "field": "Links / device",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "C12",
        "E01",
        "R04"
      ],
      "disclosure_date": "2023–2026",
      "status": "mixed",
      "scope": "cxl"
    },
    "links.cxl.6": {
      "value": "Direct / switched by version",
      "field": "Topology",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "C12",
        "E01",
        "R04"
      ],
      "disclosure_date": "2023–2026",
      "status": "mixed",
      "scope": "cxl"
    },
    "links.cxl.7": {
      "value": "n/d",
      "field": "Domain limit",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "C12",
        "E01",
        "R04"
      ],
      "disclosure_date": "2023–2026",
      "status": "mixed",
      "scope": "cxl"
    },
    "links.cxl.8": {
      "value": "Cache / memory semantics by device type",
      "field": "Coherence / semantics",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "C12",
        "E01",
        "R04"
      ],
      "disclosure_date": "2023–2026",
      "status": "mixed",
      "scope": "cxl"
    },
    "links.gaudi.0": {
      "value": "Gaudi 3 Ethernet",
      "field": "Interconnect",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi"
    },
    "links.gaudi.1": {
      "value": "2024",
      "field": "Year / generation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi"
    },
    "links.gaudi.2": {
      "value": "112G PAM4 SerDes",
      "field": "Lane rate",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi"
    },
    "links.gaudi.3": {
      "value": "2 per 200GbE",
      "field": "Lanes / link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi"
    },
    "links.gaudi.4": {
      "value": "25",
      "field": "GB/s per link per direction",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi"
    },
    "links.gaudi.5": {
      "value": "24",
      "field": "Links / device",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi"
    },
    "links.gaudi.6": {
      "value": "3 links × 7 peers + 3 external",
      "field": "Topology",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi"
    },
    "links.gaudi.7": {
      "value": "8 local",
      "field": "Domain limit",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi"
    },
    "links.gaudi.8": {
      "value": "RDMA; not CPU cache coherence",
      "field": "Coherence / semantics",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi"
    },
    "links.xelink.0": {
      "value": "Xe Link / Max 1550",
      "field": "Interconnect",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P27"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "xelink"
    },
    "links.xelink.1": {
      "value": "2023",
      "field": "Year / generation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P27"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "xelink"
    },
    "links.xelink.2": {
      "value": "n/d",
      "field": "Lane rate",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P27"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "xelink"
    },
    "links.xelink.3": {
      "value": "n/d",
      "field": "Lanes / link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P27"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "xelink"
    },
    "links.xelink.4": {
      "value": "n/d",
      "field": "GB/s per link per direction",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P27"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "xelink"
    },
    "links.xelink.5": {
      "value": "n/d",
      "field": "Links / device",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P27"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "xelink"
    },
    "links.xelink.6": {
      "value": "System-wired GPU graph",
      "field": "Topology",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P27"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "xelink"
    },
    "links.xelink.7": {
      "value": "4 GPU Lenovo reference",
      "field": "Domain limit",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P27"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "xelink"
    },
    "links.xelink.8": {
      "value": "Peer GPU memory traffic",
      "field": "Coherence / semantics",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P27"
      ],
      "disclosure_date": "2023",
      "status": "historical shipping",
      "scope": "xelink"
    },
    "links.oci.0": {
      "value": "Optical compute interconnect",
      "field": "Interconnect",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E12"
      ],
      "disclosure_date": "2024",
      "status": "demonstration",
      "scope": "oci"
    },
    "links.oci.1": {
      "value": "2024 demo",
      "field": "Year / generation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E12"
      ],
      "disclosure_date": "2024",
      "status": "demonstration",
      "scope": "oci"
    },
    "links.oci.2": {
      "value": "32 Gb/s optical channel",
      "field": "Lane rate",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E12"
      ],
      "disclosure_date": "2024",
      "status": "demonstration",
      "scope": "oci"
    },
    "links.oci.3": {
      "value": "n/a",
      "field": "Lanes / link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E12"
      ],
      "disclosure_date": "2024",
      "status": "demonstration",
      "scope": "oci"
    },
    "links.oci.4": {
      "value": "250 aggregate TX, derived",
      "field": "GB/s per link per direction",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E12"
      ],
      "disclosure_date": "2024",
      "status": "demonstration",
      "scope": "oci"
    },
    "links.oci.5": {
      "value": "n/a",
      "field": "Links / device",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E12"
      ],
      "disclosure_date": "2024",
      "status": "demonstration",
      "scope": "oci"
    },
    "links.oci.6": {
      "value": "Optical chip-to-chip",
      "field": "Topology",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E12"
      ],
      "disclosure_date": "2024",
      "status": "demonstration",
      "scope": "oci"
    },
    "links.oci.7": {
      "value": "n/d",
      "field": "Domain limit",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E12"
      ],
      "disclosure_date": "2024",
      "status": "demonstration",
      "scope": "oci"
    },
    "links.oci.8": {
      "value": "Physical I/O demonstration, not a coherence protocol",
      "field": "Coherence / semantics",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E12"
      ],
      "disclosure_date": "2024",
      "status": "demonstration",
      "scope": "oci"
    },
    "systems.dl1.0": {
      "value": "AWS DL1",
      "field": "Platform",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E14"
      ],
      "disclosure_date": "2021",
      "status": "GA",
      "scope": "dl1"
    },
    "systems.dl1.1": {
      "value": "2021 GA",
      "field": "Year / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E14"
      ],
      "disclosure_date": "2021",
      "status": "GA",
      "scope": "dl1"
    },
    "systems.dl1.2": {
      "value": "2 Xeon; 8 Gaudi",
      "field": "CPU / accelerator count",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E14"
      ],
      "disclosure_date": "2021",
      "status": "GA",
      "scope": "dl1"
    },
    "systems.dl1.3": {
      "value": "8 Gaudi",
      "field": "Scale-up domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E14"
      ],
      "disclosure_date": "2021",
      "status": "GA",
      "scope": "dl1"
    },
    "systems.dl1.4": {
      "value": "400Gb/s instance ÷ 8 = 6.25 GB/s average; shared",
      "field": "Scale-out per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E14"
      ],
      "disclosure_date": "2021",
      "status": "GA",
      "scope": "dl1"
    },
    "systems.dl1.5": {
      "value": "n/d",
      "field": "Rack power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E14"
      ],
      "disclosure_date": "2021",
      "status": "GA",
      "scope": "dl1"
    },
    "systems.dl1.6": {
      "value": "n/d",
      "field": "Cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E14"
      ],
      "disclosure_date": "2021",
      "status": "GA",
      "scope": "dl1"
    },
    "systems.aurora.0": {
      "value": "Aurora",
      "field": "Platform",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P31"
      ],
      "disclosure_date": "2023–2025",
      "status": "deployed",
      "scope": "aurora"
    },
    "systems.aurora.1": {
      "value": "2023 installation; later user service",
      "field": "Year / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P31"
      ],
      "disclosure_date": "2023–2025",
      "status": "deployed",
      "scope": "aurora"
    },
    "systems.aurora.2": {
      "value": "2 Xeon Max + 6 GPU Max / node",
      "field": "CPU / accelerator count",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P31"
      ],
      "disclosure_date": "2023–2025",
      "status": "deployed",
      "scope": "aurora"
    },
    "systems.aurora.3": {
      "value": "6 GPU node; Xe Link topology",
      "field": "Scale-up domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P31"
      ],
      "disclosure_date": "2023–2025",
      "status": "deployed",
      "scope": "aurora"
    },
    "systems.aurora.4": {
      "value": "8 x 200Gb/s NIC ÷ 6 = 33.3 GB/s average",
      "field": "Scale-out per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P31"
      ],
      "disclosure_date": "2023–2025",
      "status": "deployed",
      "scope": "aurora"
    },
    "systems.aurora.5": {
      "value": "n/d",
      "field": "Rack power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P31"
      ],
      "disclosure_date": "2023–2025",
      "status": "deployed",
      "scope": "aurora"
    },
    "systems.aurora.6": {
      "value": "Direct liquid",
      "field": "Cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P31"
      ],
      "disclosure_date": "2023–2025",
      "status": "deployed",
      "scope": "aurora"
    },
    "systems.lenovo.0": {
      "value": "Lenovo SD650-I V3",
      "field": "Platform",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P27"
      ],
      "disclosure_date": "2024",
      "status": "withdrawn",
      "scope": "lenovo"
    },
    "systems.lenovo.1": {
      "value": "2023; withdrawn 2024",
      "field": "Year / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P27"
      ],
      "disclosure_date": "2024",
      "status": "withdrawn",
      "scope": "lenovo"
    },
    "systems.lenovo.2": {
      "value": "Up to 2 Xeon + 4 GPU Max",
      "field": "CPU / accelerator count",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P27"
      ],
      "disclosure_date": "2024",
      "status": "withdrawn",
      "scope": "lenovo"
    },
    "systems.lenovo.3": {
      "value": "4 GPU",
      "field": "Scale-up domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P27"
      ],
      "disclosure_date": "2024",
      "status": "withdrawn",
      "scope": "lenovo"
    },
    "systems.lenovo.4": {
      "value": "Adapter-dependent",
      "field": "Scale-out per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P27"
      ],
      "disclosure_date": "2024",
      "status": "withdrawn",
      "scope": "lenovo"
    },
    "systems.lenovo.5": {
      "value": "n/d",
      "field": "Rack power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P27"
      ],
      "disclosure_date": "2024",
      "status": "withdrawn",
      "scope": "lenovo"
    },
    "systems.lenovo.6": {
      "value": "Direct water cooling",
      "field": "Cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P27"
      ],
      "disclosure_date": "2024",
      "status": "withdrawn",
      "scope": "lenovo"
    },
    "systems.gaudi.0": {
      "value": "Gaudi 3 HLB-325",
      "field": "Platform",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi"
    },
    "systems.gaudi.1": {
      "value": "2024",
      "field": "Year / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi"
    },
    "systems.gaudi.2": {
      "value": "Host CPUs + 8 Gaudi 3",
      "field": "CPU / accelerator count",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi"
    },
    "systems.gaudi.3": {
      "value": "8 Gaudi",
      "field": "Scale-up domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi"
    },
    "systems.gaudi.4": {
      "value": "3 x 200GbE = 75 GB/s one-way",
      "field": "Scale-out per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi"
    },
    "systems.gaudi.5": {
      "value": "n/d",
      "field": "Rack power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi"
    },
    "systems.gaudi.6": {
      "value": "Air / liquid variants",
      "field": "Cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "gaudi"
    },
    "systems.c3.0": {
      "value": "Google C3",
      "field": "Platform",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E15"
      ],
      "disclosure_date": "2023",
      "status": "GA",
      "scope": "c3"
    },
    "systems.c3.1": {
      "value": "2023 GA",
      "field": "Year / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E15"
      ],
      "disclosure_date": "2023",
      "status": "GA",
      "scope": "c3"
    },
    "systems.c3.2": {
      "value": "Xeon 4th gen + custom IPU",
      "field": "CPU / accelerator count",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E15"
      ],
      "disclosure_date": "2023",
      "status": "GA",
      "scope": "c3"
    },
    "systems.c3.3": {
      "value": "CPU virtual machine",
      "field": "Scale-up domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E15"
      ],
      "disclosure_date": "2023",
      "status": "GA",
      "scope": "c3"
    },
    "systems.c3.4": {
      "value": "n/a",
      "field": "Scale-out per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E15"
      ],
      "disclosure_date": "2023",
      "status": "GA",
      "scope": "c3"
    },
    "systems.c3.5": {
      "value": "n/d",
      "field": "Rack power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E15"
      ],
      "disclosure_date": "2023",
      "status": "GA",
      "scope": "c3"
    },
    "systems.c3.6": {
      "value": "n/d",
      "field": "Cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E15"
      ],
      "disclosure_date": "2023",
      "status": "GA",
      "scope": "c3"
    },
    "software.cpu.0": {
      "value": "oneDNN / CPU framework libraries",
      "field": "Stack / release",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P05"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "cpu"
    },
    "software.cpu.1": {
      "value": "2017–2026",
      "field": "Date / era",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P05"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "cpu"
    },
    "software.cpu.2": {
      "value": "Xeon AVX-512 / VNNI / AMX",
      "field": "Hardware enabled",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P05"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "cpu"
    },
    "software.cpu.3": {
      "value": "ISA dispatch, packing and kernel selection; application must use enabled path",
      "field": "Key features / constraint",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P05"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "cpu"
    },
    "software.oneapi.0": {
      "value": "oneAPI / SYCL / Level Zero",
      "field": "Stack / release",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P11",
        "P31"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "oneapi"
    },
    "software.oneapi.1": {
      "value": "2020s",
      "field": "Date / era",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P11",
        "P31"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "oneapi"
    },
    "software.oneapi.2": {
      "value": "Xe GPU / CPU",
      "field": "Hardware enabled",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P11",
        "P31"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "oneapi"
    },
    "software.oneapi.3": {
      "value": "Shared programming model; placement and device-specific tuning remain",
      "field": "Key features / constraint",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P11",
        "P31"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "oneapi"
    },
    "software.gaudi.0": {
      "value": "SynapseAI / Gaudi software 1.24",
      "field": "Stack / release",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P30",
        "P34"
      ],
      "disclosure_date": "2026",
      "status": "documented",
      "scope": "gaudi"
    },
    "software.gaudi.1": {
      "value": "2026 documentation",
      "field": "Date / era",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P30",
        "P34"
      ],
      "disclosure_date": "2026",
      "status": "documented",
      "scope": "gaudi"
    },
    "software.gaudi.2": {
      "value": "Gaudi 2 / Gaudi 3",
      "field": "Hardware enabled",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P30",
        "P34"
      ],
      "disclosure_date": "2026",
      "status": "documented",
      "scope": "gaudi"
    },
    "software.gaudi.3": {
      "value": "PyTorch integration, graph compilation, TPC kernels and HCCL",
      "field": "Key features / constraint",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P30",
        "P34"
      ],
      "disclosure_date": "2026",
      "status": "documented",
      "scope": "gaudi"
    },
    "software.ipu.0": {
      "value": "IPU SDK",
      "field": "Stack / release",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P10"
      ],
      "disclosure_date": "2024",
      "status": "documented",
      "scope": "ipu"
    },
    "software.ipu.1": {
      "value": "2023–2024 documentation",
      "field": "Date / era",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P10"
      ],
      "disclosure_date": "2024",
      "status": "documented",
      "scope": "ipu"
    },
    "software.ipu.2": {
      "value": "E2100 IPU",
      "field": "Hardware enabled",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P10"
      ],
      "disclosure_date": "2024",
      "status": "documented",
      "scope": "ipu"
    },
    "software.ipu.3": {
      "value": "P4 pipeline, infrastructure services and host integration",
      "field": "Key features / constraint",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P10"
      ],
      "disclosure_date": "2024",
      "status": "documented",
      "scope": "ipu"
    },
    "software.offload.0": {
      "value": "DSA / IAA software interfaces",
      "field": "Stack / release",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "P03"
      ],
      "disclosure_date": "2023–2024",
      "status": "available",
      "scope": "offload"
    },
    "software.offload.1": {
      "value": "2023 onward",
      "field": "Date / era",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "P03"
      ],
      "disclosure_date": "2023–2024",
      "status": "available",
      "scope": "offload"
    },
    "software.offload.2": {
      "value": "Xeon integrated engines",
      "field": "Hardware enabled",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "P03"
      ],
      "disclosure_date": "2023–2024",
      "status": "available",
      "scope": "offload"
    },
    "software.offload.3": {
      "value": "Work queues, shared virtual addressing and asynchronous completion; overhead matters",
      "field": "Key features / constraint",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "P03"
      ],
      "disclosure_date": "2023–2024",
      "status": "available",
      "scope": "offload"
    },
    "ratios.bdw.0": {
      "value": "Broadwell 2699 v4",
      "field": "Reference",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P20"
      ],
      "disclosure_date": "2016",
      "status": "derived",
      "scope": "bdw"
    },
    "ratios.bdw.1": {
      "value": "3.49",
      "field": "DRAM GB/s per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P20"
      ],
      "disclosure_date": "2016",
      "status": "derived",
      "scope": "bdw"
    },
    "ratios.bdw.2": {
      "value": "2.50",
      "field": "L3 MB per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P20"
      ],
      "disclosure_date": "2016",
      "status": "derived",
      "scope": "bdw"
    },
    "ratios.bdw.3": {
      "value": "22 cores share four channels",
      "field": "Interpretation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P20"
      ],
      "disclosure_date": "2016",
      "status": "derived",
      "scope": "bdw"
    },
    "ratios.skl.0": {
      "value": "Skylake 8180",
      "field": "Reference",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P21",
        "P06"
      ],
      "disclosure_date": "2017",
      "status": "derived",
      "scope": "skl"
    },
    "ratios.skl.1": {
      "value": "4.57",
      "field": "DRAM GB/s per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P21",
        "P06"
      ],
      "disclosure_date": "2017",
      "status": "derived",
      "scope": "skl"
    },
    "ratios.skl.2": {
      "value": "1.375",
      "field": "L3 MB per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P21",
        "P06"
      ],
      "disclosure_date": "2017",
      "status": "derived",
      "scope": "skl"
    },
    "ratios.skl.3": {
      "value": "L2 grows; L3 changes inclusion policy",
      "field": "Interpretation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P21",
        "P06"
      ],
      "disclosure_date": "2017",
      "status": "derived",
      "scope": "skl"
    },
    "ratios.spr.0": {
      "value": "Sapphire 8490H",
      "field": "Reference",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P25"
      ],
      "disclosure_date": "2023",
      "status": "derived",
      "scope": "spr"
    },
    "ratios.spr.1": {
      "value": "5.12",
      "field": "DRAM GB/s per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P25"
      ],
      "disclosure_date": "2023",
      "status": "derived",
      "scope": "spr"
    },
    "ratios.spr.2": {
      "value": "1.875",
      "field": "L3 MB per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P25"
      ],
      "disclosure_date": "2023",
      "status": "derived",
      "scope": "spr"
    },
    "ratios.spr.3": {
      "value": "AMX raises arithmetic demand",
      "field": "Interpretation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03",
        "P25"
      ],
      "disclosure_date": "2023",
      "status": "derived",
      "scope": "spr"
    },
    "ratios.emr.0": {
      "value": "Emerald 8592+",
      "field": "Reference",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P26"
      ],
      "disclosure_date": "2023",
      "status": "derived",
      "scope": "emr"
    },
    "ratios.emr.1": {
      "value": "5.60",
      "field": "DRAM GB/s per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P26"
      ],
      "disclosure_date": "2023",
      "status": "derived",
      "scope": "emr"
    },
    "ratios.emr.2": {
      "value": "5.00",
      "field": "L3 MB per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P26"
      ],
      "disclosure_date": "2023",
      "status": "derived",
      "scope": "emr"
    },
    "ratios.emr.3": {
      "value": "Large LLC capacity increase",
      "field": "Interpretation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P26"
      ],
      "disclosure_date": "2023",
      "status": "derived",
      "scope": "emr"
    },
    "ratios.srf.0": {
      "value": "Sierra 6780E",
      "field": "Reference",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P17"
      ],
      "disclosure_date": "2024",
      "status": "derived",
      "scope": "srf"
    },
    "ratios.srf.1": {
      "value": "2.84",
      "field": "DRAM GB/s per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P17"
      ],
      "disclosure_date": "2024",
      "status": "derived",
      "scope": "srf"
    },
    "ratios.srf.2": {
      "value": "0.75",
      "field": "L3 MB per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P17"
      ],
      "disclosure_date": "2024",
      "status": "derived",
      "scope": "srf"
    },
    "ratios.srf.3": {
      "value": "Density-oriented reference",
      "field": "Interpretation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P17"
      ],
      "disclosure_date": "2024",
      "status": "derived",
      "scope": "srf"
    },
    "ratios.gnr.0": {
      "value": "Granite 6980P / MRDIMM",
      "field": "Reference",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P16",
        "P18"
      ],
      "disclosure_date": "2024",
      "status": "derived",
      "scope": "gnr"
    },
    "ratios.gnr.1": {
      "value": "6.60",
      "field": "DRAM GB/s per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P16",
        "P18"
      ],
      "disclosure_date": "2024",
      "status": "derived",
      "scope": "gnr"
    },
    "ratios.gnr.2": {
      "value": "3.9375",
      "field": "L3 MB per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P16",
        "P18"
      ],
      "disclosure_date": "2024",
      "status": "derived",
      "scope": "gnr"
    },
    "ratios.gnr.3": {
      "value": "12 channels at 8800 MT/s",
      "field": "Interpretation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P16",
        "P18"
      ],
      "disclosure_date": "2024",
      "status": "derived",
      "scope": "gnr"
    },
    "ratios.cwf.0": {
      "value": "Clearwater 6990E+",
      "field": "Reference",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "P19"
      ],
      "disclosure_date": "2026",
      "status": "derived",
      "scope": "cwf"
    },
    "ratios.cwf.1": {
      "value": "2.67",
      "field": "DRAM GB/s per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "P19"
      ],
      "disclosure_date": "2026",
      "status": "derived",
      "scope": "cwf"
    },
    "ratios.cwf.2": {
      "value": "2.00",
      "field": "L3 MB per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "P19"
      ],
      "disclosure_date": "2026",
      "status": "derived",
      "scope": "cwf"
    },
    "ratios.cwf.3": {
      "value": "Double cores; more cache per core",
      "field": "Interpretation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "P19"
      ],
      "disclosure_date": "2026",
      "status": "derived",
      "scope": "cwf"
    },
    "balance.g2.0": {
      "value": "Gaudi 2",
      "field": "Device",
      "basis": "HBM bandwidth divided by dense BF16 FLOP/s; fabric per direction / HBM; peak/TDP is not measured energy efficiency",
      "source": [
        "P02",
        "P30"
      ],
      "disclosure_date": "2022",
      "status": "derived peak",
      "scope": "g2"
    },
    "balance.g2.1": {
      "value": "0.00569",
      "field": "HBM bytes/FLOP",
      "basis": "HBM bandwidth divided by dense BF16 FLOP/s; fabric per direction / HBM; peak/TDP is not measured energy efficiency",
      "source": [
        "P02",
        "P30"
      ],
      "disclosure_date": "2022",
      "status": "derived peak",
      "scope": "g2"
    },
    "balance.g2.2": {
      "value": "0.122",
      "field": "All-port network / HBM BW",
      "basis": "HBM bandwidth divided by dense BF16 FLOP/s; fabric per direction / HBM; peak/TDP is not measured energy efficiency",
      "source": [
        "P02",
        "P30"
      ],
      "disclosure_date": "2022",
      "status": "derived peak",
      "scope": "g2"
    },
    "balance.g2.3": {
      "value": "37.5 GB/s, 3 x 100GbE allocation",
      "field": "External BW / device",
      "basis": "HBM bandwidth divided by dense BF16 FLOP/s; fabric per direction / HBM; peak/TDP is not measured energy efficiency",
      "source": [
        "P02",
        "P30"
      ],
      "disclosure_date": "2022",
      "status": "derived peak",
      "scope": "g2"
    },
    "balance.g2.4": {
      "value": "0.720 TF/W at 600 W",
      "field": "BF16 peak / device power",
      "basis": "HBM bandwidth divided by dense BF16 FLOP/s; fabric per direction / HBM; peak/TDP is not measured energy efficiency",
      "source": [
        "P02",
        "P30"
      ],
      "disclosure_date": "2022",
      "status": "derived peak",
      "scope": "g2"
    },
    "balance.g3.0": {
      "value": "Gaudi 3",
      "field": "Device",
      "basis": "HBM bandwidth divided by dense BF16 FLOP/s; fabric per direction / HBM; peak/TDP is not measured energy efficiency",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "derived peak",
      "scope": "g3"
    },
    "balance.g3.1": {
      "value": "0.00221",
      "field": "HBM bytes/FLOP",
      "basis": "HBM bandwidth divided by dense BF16 FLOP/s; fabric per direction / HBM; peak/TDP is not measured energy efficiency",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "derived peak",
      "scope": "g3"
    },
    "balance.g3.2": {
      "value": "0.162",
      "field": "All-port network / HBM BW",
      "basis": "HBM bandwidth divided by dense BF16 FLOP/s; fabric per direction / HBM; peak/TDP is not measured energy efficiency",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "derived peak",
      "scope": "g3"
    },
    "balance.g3.3": {
      "value": "75 GB/s, 3 x 200GbE allocation",
      "field": "External BW / device",
      "basis": "HBM bandwidth divided by dense BF16 FLOP/s; fabric per direction / HBM; peak/TDP is not measured energy efficiency",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "derived peak",
      "scope": "g3"
    },
    "balance.g3.4": {
      "value": "1.864 TF/W at 900 W",
      "field": "BF16 peak / device power",
      "basis": "HBM bandwidth divided by dense BF16 FLOP/s; fabric per direction / HBM; peak/TDP is not measured energy efficiency",
      "source": [
        "P02"
      ],
      "disclosure_date": "2024",
      "status": "derived peak",
      "scope": "g3"
    },
    "balance.pvc.0": {
      "value": "GPU Max 1550",
      "field": "Device",
      "basis": "HBM bandwidth divided by dense BF16 FLOP/s; fabric per direction / HBM; peak/TDP is not measured energy efficiency",
      "source": [
        "P27"
      ],
      "disclosure_date": "2023",
      "status": "derived peak",
      "scope": "pvc"
    },
    "balance.pvc.1": {
      "value": "0.00381",
      "field": "HBM bytes/FLOP",
      "basis": "HBM bandwidth divided by dense BF16 FLOP/s; fabric per direction / HBM; peak/TDP is not measured energy efficiency",
      "source": [
        "P27"
      ],
      "disclosure_date": "2023",
      "status": "derived peak",
      "scope": "pvc"
    },
    "balance.pvc.2": {
      "value": "0.0994 Xe Link / HBM, Lenovo basis",
      "field": "All-port network / HBM BW",
      "basis": "HBM bandwidth divided by dense BF16 FLOP/s; fabric per direction / HBM; peak/TDP is not measured energy efficiency",
      "source": [
        "P27"
      ],
      "disclosure_date": "2023",
      "status": "derived peak",
      "scope": "pvc"
    },
    "balance.pvc.3": {
      "value": "System-dependent",
      "field": "External BW / device",
      "basis": "HBM bandwidth divided by dense BF16 FLOP/s; fabric per direction / HBM; peak/TDP is not measured energy efficiency",
      "source": [
        "P27"
      ],
      "disclosure_date": "2023",
      "status": "derived peak",
      "scope": "pvc"
    },
    "balance.pvc.4": {
      "value": "1.398 TF/W at 600 W",
      "field": "BF16 peak / device power",
      "basis": "HBM bandwidth divided by dense BF16 FLOP/s; fabric per direction / HBM; peak/TDP is not measured energy efficiency",
      "source": [
        "P27"
      ],
      "disclosure_date": "2023",
      "status": "derived peak",
      "scope": "pvc"
    },
    "conferences.knl.0": {
      "value": "Hot Chips",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C13"
      ],
      "disclosure_date": "2015",
      "status": "disclosure",
      "scope": "knl"
    },
    "conferences.knl.1": {
      "value": "2015",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C13"
      ],
      "disclosure_date": "2015",
      "status": "disclosure",
      "scope": "knl"
    },
    "conferences.knl.2": {
      "value": "Knights Landing",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C13"
      ],
      "disclosure_date": "2015",
      "status": "disclosure",
      "scope": "knl"
    },
    "conferences.knl.3": {
      "value": "Avinash Sodani",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C13"
      ],
      "disclosure_date": "2015",
      "status": "disclosure",
      "scope": "knl"
    },
    "conferences.knl.4": {
      "value": "Xeon Phi",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C13"
      ],
      "disclosure_date": "2015",
      "status": "disclosure",
      "scope": "knl"
    },
    "conferences.knl.5": {
      "value": "Product architecture",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C13"
      ],
      "disclosure_date": "2015",
      "status": "disclosure",
      "scope": "knl"
    },
    "conferences.knl.6": {
      "value": "C13",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C13"
      ],
      "disclosure_date": "2015",
      "status": "disclosure",
      "scope": "knl"
    },
    "conferences.clx.0": {
      "value": "Hot Chips",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C06"
      ],
      "disclosure_date": "2018",
      "status": "disclosure",
      "scope": "clx"
    },
    "conferences.clx.1": {
      "value": "2018",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C06"
      ],
      "disclosure_date": "2018",
      "status": "disclosure",
      "scope": "clx"
    },
    "conferences.clx.2": {
      "value": "Cascade Lake",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C06"
      ],
      "disclosure_date": "2018",
      "status": "disclosure",
      "scope": "clx"
    },
    "conferences.clx.3": {
      "value": "Akhilesh Kumar",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C06"
      ],
      "disclosure_date": "2018",
      "status": "disclosure",
      "scope": "clx"
    },
    "conferences.clx.4": {
      "value": "Xeon 2nd gen",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C06"
      ],
      "disclosure_date": "2018",
      "status": "disclosure",
      "scope": "clx"
    },
    "conferences.clx.5": {
      "value": "Architecture / VNNI / memory",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C06"
      ],
      "disclosure_date": "2018",
      "status": "disclosure",
      "scope": "clx"
    },
    "conferences.clx.6": {
      "value": "C06",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C06"
      ],
      "disclosure_date": "2018",
      "status": "disclosure",
      "scope": "clx"
    },
    "conferences.nnp.0": {
      "value": "Hot Chips",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C14"
      ],
      "disclosure_date": "2019",
      "status": "disclosure",
      "scope": "nnp"
    },
    "conferences.nnp.1": {
      "value": "2019",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C14"
      ],
      "disclosure_date": "2019",
      "status": "disclosure",
      "scope": "nnp"
    },
    "conferences.nnp.2": {
      "value": "Nervana; packaging; Optane",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C14"
      ],
      "disclosure_date": "2019",
      "status": "disclosure",
      "scope": "nnp"
    },
    "conferences.nnp.3": {
      "value": "Intel",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C14"
      ],
      "disclosure_date": "2019",
      "status": "disclosure",
      "scope": "nnp"
    },
    "conferences.nnp.4": {
      "value": "NNP-T / NNP-I",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C14"
      ],
      "disclosure_date": "2019",
      "status": "disclosure",
      "scope": "nnp"
    },
    "conferences.nnp.5": {
      "value": "Official press release",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C14"
      ],
      "disclosure_date": "2019",
      "status": "disclosure",
      "scope": "nnp"
    },
    "conferences.nnp.6": {
      "value": "C14",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C14"
      ],
      "disclosure_date": "2019",
      "status": "disclosure",
      "scope": "nnp"
    },
    "conferences.hpca.0": {
      "value": "HPCA",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R05"
      ],
      "disclosure_date": "2020",
      "status": "research",
      "scope": "hpca"
    },
    "conferences.hpca.1": {
      "value": "2020",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R05"
      ],
      "disclosure_date": "2020",
      "status": "research",
      "scope": "hpca"
    },
    "conferences.hpca.2": {
      "value": "Persistent Memory and the Path to Being Comfortably NUMB",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R05"
      ],
      "disclosure_date": "2020",
      "status": "research",
      "scope": "hpca"
    },
    "conferences.hpca.3": {
      "value": "Steven Swanson",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R05"
      ],
      "disclosure_date": "2020",
      "status": "research",
      "scope": "hpca"
    },
    "conferences.hpca.4": {
      "value": "Optane context",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R05"
      ],
      "disclosure_date": "2020",
      "status": "research",
      "scope": "hpca"
    },
    "conferences.hpca.5": {
      "value": "Independent research keynote",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R05"
      ],
      "disclosure_date": "2020",
      "status": "research",
      "scope": "hpca"
    },
    "conferences.hpca.6": {
      "value": "R05",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R05"
      ],
      "disclosure_date": "2020",
      "status": "research",
      "scope": "hpca"
    },
    "conferences.pvc.0": {
      "value": "ISSCC",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03"
      ],
      "disclosure_date": "2022",
      "status": "implementation",
      "scope": "pvc"
    },
    "conferences.pvc.1": {
      "value": "2022",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03"
      ],
      "disclosure_date": "2022",
      "status": "implementation",
      "scope": "pvc"
    },
    "conferences.pvc.2": {
      "value": "Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03"
      ],
      "disclosure_date": "2022",
      "status": "implementation",
      "scope": "pvc"
    },
    "conferences.pvc.3": {
      "value": "W. Gomes et al.",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03"
      ],
      "disclosure_date": "2022",
      "status": "implementation",
      "scope": "pvc"
    },
    "conferences.pvc.4": {
      "value": "Ponte Vecchio",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03"
      ],
      "disclosure_date": "2022",
      "status": "implementation",
      "scope": "pvc"
    },
    "conferences.pvc.5": {
      "value": "Implementation; paper 2.1 press kit",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03"
      ],
      "disclosure_date": "2022",
      "status": "implementation",
      "scope": "pvc"
    },
    "conferences.pvc.6": {
      "value": "C03",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03"
      ],
      "disclosure_date": "2022",
      "status": "implementation",
      "scope": "pvc"
    },
    "conferences.spr.0": {
      "value": "ISSCC",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03"
      ],
      "disclosure_date": "2022",
      "status": "implementation",
      "scope": "spr"
    },
    "conferences.spr.1": {
      "value": "2022",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03"
      ],
      "disclosure_date": "2022",
      "status": "implementation",
      "scope": "spr"
    },
    "conferences.spr.2": {
      "value": "Sapphire Rapids: Next-Generation Xeon",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03"
      ],
      "disclosure_date": "2022",
      "status": "implementation",
      "scope": "spr"
    },
    "conferences.spr.3": {
      "value": "Intel",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03"
      ],
      "disclosure_date": "2022",
      "status": "implementation",
      "scope": "spr"
    },
    "conferences.spr.4": {
      "value": "Sapphire Rapids",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03"
      ],
      "disclosure_date": "2022",
      "status": "implementation",
      "scope": "spr"
    },
    "conferences.spr.5": {
      "value": "Implementation; paper 2.2 press kit",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03"
      ],
      "disclosure_date": "2022",
      "status": "implementation",
      "scope": "spr"
    },
    "conferences.spr.6": {
      "value": "C03",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03"
      ],
      "disclosure_date": "2022",
      "status": "implementation",
      "scope": "spr"
    },
    "conferences.c3.0": {
      "value": "Google Cloud Next",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E15"
      ],
      "disclosure_date": "2022",
      "status": "deployment",
      "scope": "c3"
    },
    "conferences.c3.1": {
      "value": "2022",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E15"
      ],
      "disclosure_date": "2022",
      "status": "deployment",
      "scope": "c3"
    },
    "conferences.c3.2": {
      "value": "C3 and custom Intel IPU",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E15"
      ],
      "disclosure_date": "2022",
      "status": "deployment",
      "scope": "c3"
    },
    "conferences.c3.3": {
      "value": "Google / Intel",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E15"
      ],
      "disclosure_date": "2022",
      "status": "deployment",
      "scope": "c3"
    },
    "conferences.c3.4": {
      "value": "Sapphire Rapids + IPU",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E15"
      ],
      "disclosure_date": "2022",
      "status": "deployment",
      "scope": "c3"
    },
    "conferences.c3.5": {
      "value": "Preview; GA followed 2023",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E15"
      ],
      "disclosure_date": "2022",
      "status": "deployment",
      "scope": "c3"
    },
    "conferences.c3.6": {
      "value": "E15",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E15"
      ],
      "disclosure_date": "2022",
      "status": "deployment",
      "scope": "c3"
    },
    "conferences.gnr.0": {
      "value": "Hot Chips",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C12"
      ],
      "disclosure_date": "2023",
      "status": "disclosure",
      "scope": "gnr"
    },
    "conferences.gnr.1": {
      "value": "2023",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C12"
      ],
      "disclosure_date": "2023",
      "status": "disclosure",
      "scope": "gnr"
    },
    "conferences.gnr.2": {
      "value": "Granite Rapids and Sierra Forest",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C12"
      ],
      "disclosure_date": "2023",
      "status": "disclosure",
      "scope": "gnr"
    },
    "conferences.gnr.3": {
      "value": "Intel",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C12"
      ],
      "disclosure_date": "2023",
      "status": "disclosure",
      "scope": "gnr"
    },
    "conferences.gnr.4": {
      "value": "Xeon 6",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C12"
      ],
      "disclosure_date": "2023",
      "status": "disclosure",
      "scope": "gnr"
    },
    "conferences.gnr.5": {
      "value": "Architecture briefing slides",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C12"
      ],
      "disclosure_date": "2023",
      "status": "disclosure",
      "scope": "gnr"
    },
    "conferences.gnr.6": {
      "value": "C12",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C12"
      ],
      "disclosure_date": "2023",
      "status": "disclosure",
      "scope": "gnr"
    },
    "conferences.cxl.0": {
      "value": "MICRO",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R04"
      ],
      "disclosure_date": "2023",
      "status": "research",
      "scope": "cxl"
    },
    "conferences.cxl.1": {
      "value": "2023",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R04"
      ],
      "disclosure_date": "2023",
      "status": "research",
      "scope": "cxl"
    },
    "conferences.cxl.2": {
      "value": "Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R04"
      ],
      "disclosure_date": "2023",
      "status": "research",
      "scope": "cxl"
    },
    "conferences.cxl.3": {
      "value": "Yan Sun et al.",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R04"
      ],
      "disclosure_date": "2023",
      "status": "research",
      "scope": "cxl"
    },
    "conferences.cxl.4": {
      "value": "Sapphire Rapids / CXL",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R04"
      ],
      "disclosure_date": "2023",
      "status": "research",
      "scope": "cxl"
    },
    "conferences.cxl.5": {
      "value": "Real-device measurement",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R04"
      ],
      "disclosure_date": "2023",
      "status": "research",
      "scope": "cxl"
    },
    "conferences.cxl.6": {
      "value": "R04",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R04"
      ],
      "disclosure_date": "2023",
      "status": "research",
      "scope": "cxl"
    },
    "conferences.emr.0": {
      "value": "ISSCC",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04"
      ],
      "disclosure_date": "2024",
      "status": "implementation",
      "scope": "emr"
    },
    "conferences.emr.1": {
      "value": "2024",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04"
      ],
      "disclosure_date": "2024",
      "status": "implementation",
      "scope": "emr"
    },
    "conferences.emr.2": {
      "value": "Emerald Rapids: 5th-Generation Xeon Scalable",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04"
      ],
      "disclosure_date": "2024",
      "status": "implementation",
      "scope": "emr"
    },
    "conferences.emr.3": {
      "value": "Ashley O. Munch et al.",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04"
      ],
      "disclosure_date": "2024",
      "status": "implementation",
      "scope": "emr"
    },
    "conferences.emr.4": {
      "value": "Emerald Rapids",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04"
      ],
      "disclosure_date": "2024",
      "status": "implementation",
      "scope": "emr"
    },
    "conferences.emr.5": {
      "value": "Implementation; paper 2.3 press kit",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04"
      ],
      "disclosure_date": "2024",
      "status": "implementation",
      "scope": "emr"
    },
    "conferences.emr.6": {
      "value": "C04",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04"
      ],
      "disclosure_date": "2024",
      "status": "implementation",
      "scope": "emr"
    },
    "conferences.dsa.0": {
      "value": "ASPLOS",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02"
      ],
      "disclosure_date": "2024",
      "status": "research",
      "scope": "dsa"
    },
    "conferences.dsa.1": {
      "value": "2024",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02"
      ],
      "disclosure_date": "2024",
      "status": "research",
      "scope": "dsa"
    },
    "conferences.dsa.2": {
      "value": "A Quantitative Analysis and Guidelines of Data Streaming Accelerator in Modern Intel Xeon Scalable Processors",
      "field": "Paper / talk / disclosure",
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      "source": [
        "R02"
      ],
      "disclosure_date": "2024",
      "status": "research",
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    },
    "conferences.dsa.3": {
      "value": "Reese Kuper et al.",
      "field": "Presenter / authors",
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      "source": [
        "R02"
      ],
      "disclosure_date": "2024",
      "status": "research",
      "scope": "dsa"
    },
    "conferences.dsa.4": {
      "value": "DSA / Sapphire Rapids",
      "field": "Product",
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      "source": [
        "R02"
      ],
      "disclosure_date": "2024",
      "status": "research",
      "scope": "dsa"
    },
    "conferences.dsa.5": {
      "value": "Measured offload behavior",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02"
      ],
      "disclosure_date": "2024",
      "status": "research",
      "scope": "dsa"
    },
    "conferences.dsa.6": {
      "value": "R02",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02"
      ],
      "disclosure_date": "2024",
      "status": "research",
      "scope": "dsa"
    },
    "conferences.gaudi.0": {
      "value": "Hot Chips",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2024",
      "status": "disclosure",
      "scope": "gaudi"
    },
    "conferences.gaudi.1": {
      "value": "2024",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2024",
      "status": "disclosure",
      "scope": "gaudi"
    },
    "conferences.gaudi.2": {
      "value": "Gaudi 3; Xeon 6; optical I/O",
      "field": "Paper / talk / disclosure",
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      "source": [
        "E13"
      ],
      "disclosure_date": "2024",
      "status": "disclosure",
      "scope": "gaudi"
    },
    "conferences.gaudi.3": {
      "value": "Intel",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2024",
      "status": "disclosure",
      "scope": "gaudi"
    },
    "conferences.gaudi.4": {
      "value": "Gaudi 3 / Xeon 6 / OCI",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2024",
      "status": "disclosure",
      "scope": "gaudi"
    },
    "conferences.gaudi.5": {
      "value": "Architecture and demo summary",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2024",
      "status": "disclosure",
      "scope": "gaudi"
    },
    "conferences.gaudi.6": {
      "value": "E13",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2024",
      "status": "disclosure",
      "scope": "gaudi"
    },
    "conferences.ofc.0": {
      "value": "OFC",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E12"
      ],
      "disclosure_date": "2024",
      "status": "demo",
      "scope": "ofc"
    },
    "conferences.ofc.1": {
      "value": "2024",
      "field": "Year",
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      "source": [
        "E12"
      ],
      "disclosure_date": "2024",
      "status": "demo",
      "scope": "ofc"
    },
    "conferences.ofc.2": {
      "value": "Integrated optical compute interconnect",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E12"
      ],
      "disclosure_date": "2024",
      "status": "demo",
      "scope": "ofc"
    },
    "conferences.ofc.3": {
      "value": "Intel IPS",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E12"
      ],
      "disclosure_date": "2024",
      "status": "demo",
      "scope": "ofc"
    },
    "conferences.ofc.4": {
      "value": "OCI chiplet",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E12"
      ],
      "disclosure_date": "2024",
      "status": "demo",
      "scope": "ofc"
    },
    "conferences.ofc.5": {
      "value": "Live technology demonstration",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E12"
      ],
      "disclosure_date": "2024",
      "status": "demo",
      "scope": "ofc"
    },
    "conferences.ofc.6": {
      "value": "E12",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E12"
      ],
      "disclosure_date": "2024",
      "status": "demo",
      "scope": "ofc"
    },
    "conferences.vision.0": {
      "value": "Intel Vision",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E20"
      ],
      "disclosure_date": "2024",
      "status": "announcement",
      "scope": "vision"
    },
    "conferences.vision.1": {
      "value": "2024",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E20"
      ],
      "disclosure_date": "2024",
      "status": "announcement",
      "scope": "vision"
    },
    "conferences.vision.2": {
      "value": "Gaudi 3 architecture and open systems",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E20"
      ],
      "disclosure_date": "2024",
      "status": "announcement",
      "scope": "vision"
    },
    "conferences.vision.3": {
      "value": "Intel",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E20"
      ],
      "disclosure_date": "2024",
      "status": "announcement",
      "scope": "vision"
    },
    "conferences.vision.4": {
      "value": "Gaudi 3",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E20"
      ],
      "disclosure_date": "2024",
      "status": "announcement",
      "scope": "vision"
    },
    "conferences.vision.5": {
      "value": "Product announcement",
      "field": "Evidence type",
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      "source": [
        "E20"
      ],
      "disclosure_date": "2024",
      "status": "announcement",
      "scope": "vision"
    },
    "conferences.vision.6": {
      "value": "E20",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E20"
      ],
      "disclosure_date": "2024",
      "status": "announcement",
      "scope": "vision"
    },
    "conferences.lia.0": {
      "value": "ISCA",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R01"
      ],
      "disclosure_date": "2025",
      "status": "research",
      "scope": "lia"
    },
    "conferences.lia.1": {
      "value": "2025",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R01"
      ],
      "disclosure_date": "2025",
      "status": "research",
      "scope": "lia"
    },
    "conferences.lia.2": {
      "value": "LIA: cooperative AMX CPU-GPU computation and CXL offloading",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R01"
      ],
      "disclosure_date": "2025",
      "status": "research",
      "scope": "lia"
    },
    "conferences.lia.3": {
      "value": "Hyungyo Kim et al.",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R01"
      ],
      "disclosure_date": "2025",
      "status": "research",
      "scope": "lia"
    },
    "conferences.lia.4": {
      "value": "Sapphire / Granite Rapids",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R01"
      ],
      "disclosure_date": "2025",
      "status": "research",
      "scope": "lia"
    },
    "conferences.lia.5": {
      "value": "Independent system research",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R01"
      ],
      "disclosure_date": "2025",
      "status": "research",
      "scope": "lia"
    },
    "conferences.lia.6": {
      "value": "R01",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R01"
      ],
      "disclosure_date": "2025",
      "status": "research",
      "scope": "lia"
    },
    "conferences.cwf.0": {
      "value": "Hot Chips / Tech Tour",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P08"
      ],
      "disclosure_date": "2025",
      "status": "disclosure",
      "scope": "cwf"
    },
    "conferences.cwf.1": {
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      "field": "Year",
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      "source": [
        "P08"
      ],
      "disclosure_date": "2025",
      "status": "disclosure",
      "scope": "cwf"
    },
    "conferences.cwf.2": {
      "value": "Clearwater Forest",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P08"
      ],
      "disclosure_date": "2025",
      "status": "disclosure",
      "scope": "cwf"
    },
    "conferences.cwf.3": {
      "value": "Intel",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P08"
      ],
      "disclosure_date": "2025",
      "status": "disclosure",
      "scope": "cwf"
    },
    "conferences.cwf.4": {
      "value": "Xeon 6+",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P08"
      ],
      "disclosure_date": "2025",
      "status": "disclosure",
      "scope": "cwf"
    },
    "conferences.cwf.5": {
      "value": "Architecture / packaging",
      "field": "Evidence type",
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      "source": [
        "P08"
      ],
      "disclosure_date": "2025",
      "status": "disclosure",
      "scope": "cwf"
    },
    "conferences.cwf.6": {
      "value": "P08",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P08"
      ],
      "disclosure_date": "2025",
      "status": "disclosure",
      "scope": "cwf"
    },
    "conferences.ocp.0": {
      "value": "OCP Global Summit",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03"
      ],
      "disclosure_date": "2025",
      "status": "announcement",
      "scope": "ocp"
    },
    "conferences.ocp.1": {
      "value": "2025",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03"
      ],
      "disclosure_date": "2025",
      "status": "announcement",
      "scope": "ocp"
    },
    "conferences.ocp.2": {
      "value": "Crescent Island initial disclosure",
      "field": "Paper / talk / disclosure",
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      "source": [
        "E03"
      ],
      "disclosure_date": "2025",
      "status": "announcement",
      "scope": "ocp"
    },
    "conferences.ocp.3": {
      "value": "Intel",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03"
      ],
      "disclosure_date": "2025",
      "status": "announcement",
      "scope": "ocp"
    },
    "conferences.ocp.4": {
      "value": "Crescent Island",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03"
      ],
      "disclosure_date": "2025",
      "status": "announcement",
      "scope": "ocp"
    },
    "conferences.ocp.5": {
      "value": "Roadmap / sampling target",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03"
      ],
      "disclosure_date": "2025",
      "status": "announcement",
      "scope": "ocp"
    },
    "conferences.ocp.6": {
      "value": "E03",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03"
      ],
      "disclosure_date": "2025",
      "status": "announcement",
      "scope": "ocp"
    },
    "conferences.mwc.0": {
      "value": "MWC",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E16"
      ],
      "disclosure_date": "2026",
      "status": "demo",
      "scope": "mwc"
    },
    "conferences.mwc.1": {
      "value": "2026",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E16"
      ],
      "disclosure_date": "2026",
      "status": "demo",
      "scope": "mwc"
    },
    "conferences.mwc.2": {
      "value": "Xeon 6+ network and edge positioning",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E16"
      ],
      "disclosure_date": "2026",
      "status": "demo",
      "scope": "mwc"
    },
    "conferences.mwc.3": {
      "value": "Intel",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E16"
      ],
      "disclosure_date": "2026",
      "status": "demo",
      "scope": "mwc"
    },
    "conferences.mwc.4": {
      "value": "Clearwater Forest",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E16"
      ],
      "disclosure_date": "2026",
      "status": "demo",
      "scope": "mwc"
    },
    "conferences.mwc.5": {
      "value": "Platform demonstration",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E16"
      ],
      "disclosure_date": "2026",
      "status": "demo",
      "scope": "mwc"
    },
    "conferences.mwc.6": {
      "value": "E16",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E16"
      ],
      "disclosure_date": "2026",
      "status": "demo",
      "scope": "mwc"
    },
    "conferences.computex.0": {
      "value": "Computex",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "launch",
      "scope": "computex"
    },
    "conferences.computex.1": {
      "value": "2026",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "launch",
      "scope": "computex"
    },
    "conferences.computex.2": {
      "value": "Xeon 6+ and E835 launch",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "launch",
      "scope": "computex"
    },
    "conferences.computex.3": {
      "value": "Intel",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "launch",
      "scope": "computex"
    },
    "conferences.computex.4": {
      "value": "Clearwater / E835 / Crescent",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "launch",
      "scope": "computex"
    },
    "conferences.computex.5": {
      "value": "Commercial launch / update",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "launch",
      "scope": "computex"
    },
    "conferences.computex.6": {
      "value": "E02",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "launch",
      "scope": "computex"
    },
    "conferences.hc26.0": {
      "value": "Hot Chips",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "disclosure",
      "scope": "hc26"
    },
    "conferences.hc26.1": {
      "value": "2026",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "disclosure",
      "scope": "hc26"
    },
    "conferences.hc26.2": {
      "value": "Diamond Rapids and Crescent Island",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "disclosure",
      "scope": "hc26"
    },
    "conferences.hc26.3": {
      "value": "Intel",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "disclosure",
      "scope": "hc26"
    },
    "conferences.hc26.4": {
      "value": "Diamond / Crescent",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "disclosure",
      "scope": "hc26"
    },
    "conferences.hc26.5": {
      "value": "Architecture announcement",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "disclosure",
      "scope": "hc26"
    },
    "conferences.hc26.6": {
      "value": "E01",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026",
      "status": "disclosure",
      "scope": "hc26"
    },
    "conferences.foundry.0": {
      "value": "Foundry Direct Connect",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E19"
      ],
      "disclosure_date": "2025",
      "status": "technology",
      "scope": "foundry"
    },
    "conferences.foundry.1": {
      "value": "2024–2025",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E19"
      ],
      "disclosure_date": "2025",
      "status": "technology",
      "scope": "foundry"
    },
    "conferences.foundry.2": {
      "value": "Process and packaging enablement",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E19"
      ],
      "disclosure_date": "2025",
      "status": "technology",
      "scope": "foundry"
    },
    "conferences.foundry.3": {
      "value": "Intel / EDA partners",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E19"
      ],
      "disclosure_date": "2025",
      "status": "technology",
      "scope": "foundry"
    },
    "conferences.foundry.4": {
      "value": "18A / EMIB / Foveros",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
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