{ "vendor": "Hygon", "cutoff": "2026-09-28", "sections": [ { "id": "01", "title": [ "Scope and executive synthesis", "研究范围与核心结论" ], "blocks": [ { "id": "01.scope", "type": "prose", "text": [ "Company: Hygon Information Technology (688041). Period: 2015–28 September 2026. Deep coverage: C86 server CPUs and Deep Computing Units (DCUs); proportional coverage: workstation derivatives, HSL, systems and software. Networking is covered as an integration layer; no separately documented Hygon merchant DPU or AI NIC family was identified. Latest fully reviewed company technical disclosure: the interim report published on 14 August 2026; the event index includes HAIC 2025 and IHEP 2025. The cutoff does not imply a verified presentation at every 2026 conference.", "研究对象为海光信息技术股份有限公司（688041）。时间范围：2015 年至 2026 年 9 月 28 日。深度覆盖 C86 服务器 CPU 与深算 DCU；按相关性覆盖工作站衍生产品、HSL、系统及软件。网络作为系统集成层纳入；本次未查到具有独立技术资料的海光自有商用 DPU 或 AI 网卡产品线。完整审阅的最新公司技术披露为 2026 年 8 月 14 日发布的半年度报告；活动索引覆盖 HAIC 2025 和 IHEP 2025。研究截止日期不代表已核实海光在所有 2026 年会议上的报告。" ], "sources": [ "E01", "E05", "C02" ] }, { "id": "01.arc", "type": "prose", "text": [ "Hygon evolved from a licensed x86 starting point into a CPU–accelerator platform. The durable architectural choices are software continuity on the host, general-purpose parallel execution on the DCU, and increasingly explicit investment in the connections between them. The CPU progression is visible in commercial platforms: the second-generation 7200 family offered up to 32 cores, eight DDR4 channels and PCIe 3.0; fourth-generation C86 platforms support up to 64 cores per socket, DDR5 and PCIe 5.0. The important transition is a better host for memory and I/O intensive work, not simply a larger core count.", "海光从获得授权的 x86 技术起点，发展为 CPU 与加速器协同的平台。贯穿其中的架构选择是主机软件的连续性、DCU 的通用并行执行能力，以及不断加强的双芯互联。商用平台呈现出明确的 CPU 演进：第二代 7200 系列最高 32 核、八通道 DDR4 和 PCIe 3.0；第四代 C86 平台最高每颗 64 核，并支持 DDR5 与 PCIe 5.0。关键变化是更能承担内存与 I/O 密集型任务的主机平台，而不仅是核心数量增长。" ], "sources": [ "E03", "P04" ] }, { "id": "01.dcu", "type": "prose", "text": [ "The DCU history has firmer commercial milestones than public peak-performance tables. Deep Computing No. 1 entered commercial use in 2021; No. 2 was sold to commercial customers in 2023; No. 3 entered commercial use in 2025. Z100 and K100/K100-AI are useful board-level identities in software and deployment records, but public material does not provide a sufficiently consistent one-to-one mapping from every board name to each silicon generation. This report preserves both naming systems without silently joining them.", "DCU 的商业化时间线比公开峰值性能表更完整：深算一号于 2021 年实现商业化，深算二号于 2023 年销售给商业客户，深算三号于 2025 年实现商业化。Z100、K100／K100-AI 是软件与部署资料中有用的板卡标识，但公开资料不足以把所有板卡名称与芯片代际建立一致的一一对应关系。本报告保留两套命名，不擅自合并。" ], "sources": [ "E03", "E11", "E05", "E02", "C02" ] }, { "id": "01.system", "type": "prose", "text": [ "HSL makes the platform strategy concrete: Hygon opened its system-interconnect initiative in September 2025 and released the HSL 1.0 specification at HAIC that December. The engineering objective is tighter CPU–xPU integration with ecosystem partners. Physical bandwidth, switch radix and a maximum coherent domain are separate implementation questions; the reviewed public disclosures do not establish a normalized specification for them.", "HSL 使平台战略更加具体：海光于 2025 年 9 月开放系统互联方案，并在同年 12 月 HAIC 发布 HSL 1.0 规范，目标是与生态伙伴实现更紧密的 CPU–xPU 集成。物理带宽、交换芯片端口数和最大一致性域属于进一步的实现问题；已审阅的公开披露尚不足以建立这些参数的统一规格表。" ], "sources": [ "E05" ] }, { "id": "headline", "type": "table", "table": "headline" } ] }, { "id": "02", "title": [ "Evidence and numerical conventions", "证据与数值口径" ], "blocks": [ { "id": "02.method", "type": "prose", "text": [ "The report combines issuer technical disclosures, OEM documentation, upstream software records, deployment presentations and peer-reviewed research. Product facts and experimental configurations remain separate. A research paper can establish the topology of its tested Dhyana system or the scheduling model of its DCU; it cannot establish the implementation of every later Hygon product. The conference audit found useful systems evidence and related research, but no verified generation-by-generation Hygon product sequence at Hot Chips or ISSCC. Missing circuit details are retained as disclosure gaps.", "报告综合公司技术披露、整机文档、上游软件记录、部署报告及同行评审研究。产品事实与实验配置分别处理。论文能够说明所测 Dhyana 系统的拓扑或 DCU 的调度模型，但不能据此确定所有后续海光产品的实现。本次会议检索取得了有价值的系统资料和相关研究，但未核实到海光在 Hot Chips 或 ISSCC 上逐代披露产品的完整序列。缺失的电路细节保留为披露缺口。" ], "sources": [ "E03", "P04", "P05", "C02", "R01", "R02" ] }, { "id": "02.units", "type": "prose", "text": [ "n/d means not established by the reviewed public sources; n/a means not applicable. Bandwidth uses decimal GB/s and TB/s. DDR peak equals channels × transfer rate × 8 bytes, excluding ECC bits and protocol effects. PCIe examples are encoding-adjusted link ceilings before packet overhead. FLOP/s values are dense only when explicitly established; FP16 does not automatically establish BF16 throughput. A quoted accelerator interconnect aggregate is not divided into a one-way figure unless directionality is known.", "n/d 表示已审阅公开资料未能确定；n/a 表示不适用。带宽采用十进制 GB/s、TB/s。DDR 峰值按通道数×传输速率×8 字节计算，不计 ECC 位和协议影响。PCIe 示例是扣除编码开销后、尚未扣除分组开销的链路上限。只有明确依据时才填写稠密 FLOP/s；FP16 不能自动等同于 BF16。加速器互联的聚合值如未说明方向，不能直接折算为单向值。" ], "sources": [ "E03" ] }, { "id": "02.status", "type": "prose", "text": [ "Dates distinguish design start, production and observed commercial availability. For products without a dated general-availability announcement, a deployment establishes availability by that date rather than an exact launch day. R&D disclosures of XCD/MID partitioning, HIG virtualization, stacked-cache IP or PCIe 6.0 readiness are not retroactively attached to a shipping SKU. References are consolidated at the end, with a section-to-source map and a shared claims dataset.", "日期分别记录研发启动、量产及已观察到的商业可用性。产品若没有带日期的正式商用公告，部署记录只能证明当时已可获取，不能替代精确发布日期。XCD／MID 划分、HIG 虚拟化、堆叠缓存 IP 或 PCIe 6.0 储备等研发披露，不倒推为某个已上市 SKU 的规格。参考资料集中置于文末，附章节来源映射及共享事实数据。" ], "sources": [ "E01", "E04", "C02" ] } ] }, { "id": "03", "title": [ "CPU lineage: 2015–2018 and Dhyana", "CPU 技术起点：2015–2018 与 Dhyana" ], "blocks": [ { "id": "03.origin", "type": "prose", "text": [ "AMD announced the THATIC joint venture in April 2016, licensing processor and SoC technology for server products in China. Hygon’s prospectus dates first-generation design work to March 2016 and production to April 2018. The upstream 2018 Dhyana enablement patch identifies the first generation as originating from AMD technology and introduces the Hygon Family 18h identity. That is a firm lineage anchor; it is not a license to label subsequent Hygon generations Zen 2, Zen 3 or Zen 4.", "AMD 于 2016 年 4 月宣布与 THATIC 的合资安排，为中国服务器产品授权处理器及 SoC 技术。海光招股书记载，第一代产品于 2016 年 3 月启动设计，2018 年 4 月量产。2018 年上游 Dhyana 支持补丁明确第一代来自 AMD 技术，并引入 Hygon Family 18h 标识。这构成可靠的技术谱系起点，但不能据此把后续海光产品标成 Zen 2、Zen 3 或 Zen 4。" ], "sources": [ "E06", "E03", "P05" ] }, { "id": "03.topology", "type": "prose", "text": [ "A Journal of Software study describes a 32-core Dhyana package built from four dies, each with two four-core CCXs. Each core has private 64 KB instruction and 32 KB data L1 caches and 512 KB L2; four cores share 8 MB L3. This produces 64 MB aggregate L3, with locality organized around the CCX rather than a uniform 64 MB cache. The study reports a 14 nm implementation, two-way SMT and AVX/AVX2 support on its platform.", "《软件学报》研究描述了一个 32 核 Dhyana 封装：四个裸片，每个裸片含两个四核 CCX。每核独享 64 KB 指令 L1、32 KB 数据 L1 和 512 KB L2；四核共享 8 MB L3。因此总 L3 为 64 MB，但访问局部性以 CCX 为单位，不能视为均匀的 64 MB 缓存。论文记录的平台采用 14 nm 工艺，支持双线程 SMT 和 AVX／AVX2。" ], "sources": [ "R02" ] }, { "id": "03.meaning", "type": "prose", "text": [ "The consequence is software-visible locality. Thread placement, first-touch allocation and the placement of accelerator buffers matter because computation can be close to one die’s memory or traverse the package fabric. HygonBLIS research demonstrates why host-side kernels remain relevant in a heterogeneous solver: improving the CPU portion changes load balance and panel work even when the accelerator performs most arithmetic. This is an application result on a specific system, not a universal IPC claim.", "这种结构使局部性直接影响软件：线程绑定、首次触碰内存分配及加速器缓冲区位置，决定数据是就近访问还是经过封装内互联。HygonBLIS 研究说明了异构求解器中优化主机算子的价值：即使大部分运算由加速器完成，CPU 端优化仍会改变负载均衡和面板处理效率。这是特定系统上的应用结果，不是普遍的 IPC 结论。" ], "sources": [ "R02" ] } ] }, { "id": "04", "title": [ "Generation 2: the 7200 / 5200 / 3200 platform", "第二代：7200／5200／3200 平台" ], "blocks": [ { "id": "04.identity", "type": "prose", "text": [ "Generation 2 entered production in January 2020. Its market tiers make the design economics clear: 7200 targets large servers, 5200 smaller servers and workstations, and 3200 workstation or edge roles. These are tiers within a generation, not three successive architectures. The 7200 family supports up to 32 cores/64 threads, eight DDR4-2666 channels and 128 PCIe 3.0 lanes. The lanes can serve PCIe, storage or coherent processor connections, so 128 should not be read as a guaranteed count of externally free lanes in every multi-socket board.", "第二代于 2020 年 1 月量产。其市场分层体现了设计上的经济性：7200 面向高端服务器，5200 面向较小规模服务器及工作站，3200 面向工作站或边缘场景。这是同一代内的档次划分，不是三种连续演进的架构。7200 最高支持 32 核／64 线程、八通道 DDR4-2666 和 128 条 PCIe 3.0 通道。通道可用于 PCIe、存储或处理器一致性互联，因此不能把 128 理解为所有多路主板都能对外提供的可用通道数。" ], "sources": [ "E03" ] }, { "id": "04.balance", "type": "prose", "text": [ "The scaled-down families preserve a roughly balanced memory interface at their maximum core counts: 5200 pairs 16 cores with four channels; 3200 pairs eight with two. At DDR4-2666, all three yield a derived 5.332 GB/s per core. The prospectus specifies 512 KB L2 per core and tier-dependent L3 capacity. This gives architects a useful baseline for bandwidth-sensitive work, although sustained bandwidth depends on NUMA locality, DIMM population and access pattern.", "较低档产品在最大核心数下保持了近似一致的内存配比：5200 为 16 核配四通道，3200 为八核配双通道。按 DDR4-2666 推算，三档均为每核 5.332 GB/s。招股书明确每核 L2 为 512 KB，L3 容量随档次变化。这为带宽敏感型工作负载提供了比较基线，但持续带宽还取决于 NUMA 局部性、DIMM 配置和访问模式。" ], "sources": [ "E03" ] }, { "id": "04.security", "type": "prose", "text": [ "The platform also includes a security processor, secure boot, domestic cryptographic algorithms and trusted-computing support. These are part of the processor’s platform value in enterprise deployment. They do not establish equivalence to any particular AMD SEV generation, and the exact security mode must be checked against processor, firmware and hypervisor versions.", "平台还集成安全处理器、安全启动、国密算法及可信计算支持，这些能力构成企业部署中的平台价值。它们不能直接等同于某一代 AMD SEV；实际安全模式仍须按处理器、固件和虚拟机监控器版本核对。" ], "sources": [ "E03" ] } ] }, { "id": "05", "title": [ "Generation 3: platform renewal before the DDR5 transition", "第三代：DDR5 之前的平台更新" ], "blocks": [ { "id": "05.ship", "type": "prose", "text": [ "Hygon’s June 2022 launch presented the third-generation CPU and a CPU–DCU heterogeneous platform. The 2022 annual report records small-volume sales that year. H3C’s R4930 G5 documentation supports second- and third-generation CPUs, up to 32 cores per processor, up to 32 DDR4 DIMMs per two-socket server and platform rates up to 3200 MT/s. PCIe slots are listed as 4.0/3.0, so exact capability is configuration-dependent.", "海光于 2022 年 6 月发布第三代 CPU，并展示 CPU–DCU 异构平台。2022 年年报记录了当年的小批量销售。新华三 R4930 G5 文档覆盖第二、第三代处理器，最高每颗 32 核，双路服务器最多 32 根 DDR4 DIMM，平台内存速率最高 3200 MT/s；PCIe 插槽标为 4.0／3.0，具体能力取决于配置。" ], "sources": [ "C03", "E07", "P07" ] }, { "id": "05.change", "type": "prose", "text": [ "The available evidence supports a platform-level transition rather than a complete reconstructed core block diagram. Higher memory transfer rates can raise the bandwidth ceiling without more cores, while a newer PCIe path reduces the host-transfer bottleneck for DCUs and fast NICs. Public documents reviewed here do not establish a generation-wide ROB size, front-end width, vector datapath width or complete cache-sharing map. The report therefore does not borrow those values from contemporary AMD cores.", "现有证据能够说明平台层面的更新，尚不能完整重建核心框图。内存传输速率提高，可以在核心数不增加时提高带宽上限；更新的 PCIe 通路则有助于缓解 DCU 和高速网卡的主机传输瓶颈。已审阅资料未确定本代统一的 ROB 大小、前端宽度、向量数据通路宽度或完整缓存共享关系，因此不借用同期 AMD 核心参数补齐。" ], "sources": [ "P07", "E07" ] } ] }, { "id": "06", "title": [ "Generation 4 and the current host platform", "第四代与当前主机平台" ], "blocks": [ { "id": "06.spec", "type": "prose", "text": [ "H3C’s R4930 G7 is a concrete fourth-generation reference. Its C86-4G processors reach 64 cores per socket with SMT, up to 2.7 GHz and a listed maximum processor power of 400 W. The two-socket server reaches 128 physical cores, supports 24 DDR5 DIMM slots at up to 5600 MT/s depending on CPU, and offers up to ten PCIe 5.0 slots. The 128-core number belongs to the two-socket system.", "新华三 R4930 G7 是具体的第四代参考平台。其 C86-4G 处理器最高每颗 64 核并支持 SMT，最高主频 2.7 GHz，列明的处理器最大功率为 400 W。双路整机最高 128 个物理核心，提供 24 个 DDR5 DIMM 插槽，速率依 CPU 最高达 5600 MT/s，并最多提供十个 PCIe 5.0 插槽。128 核属于双路整机口径。" ], "sources": [ "P04" ] }, { "id": "06.consequence", "type": "prose", "text": [ "The simultaneous increase in core count, memory generation and I/O generation changes the host’s budget. More CPU threads can feed data pipelines, but they also compete for memory and power. DDR5 DIMM-slot count alone does not prove the number of independently active channels or DIMMs per channel; a defensible per-core bandwidth comparison needs the channel map. Likewise, a count of PCIe slots does not establish lanes per socket or nonblocking connectivity among accelerators and NICs.", "核心数、内存代际与 I/O 代际同步提升，改变了主机资源配比。更多 CPU 线程可以供给数据流水线，也会竞争内存与功率预算。仅凭 DDR5 插槽数量，不能确定独立活跃通道数或每通道 DIMM 数；严谨的每核带宽比较需要通道拓扑。同样，PCIe 插槽数量也不能说明每颗 CPU 的通道数，或加速器与网卡之间是否具有无阻塞连接。" ], "sources": [ "P04" ] }, { "id": "06.roadmap", "type": "prose", "text": [ "Later CPU development is discussed in company disclosures, but this source set does not establish general availability for a named fifth-generation server product. It is retained as a roadmap entry. The current technical direction includes larger and better-managed caches, stronger branch prediction, modular chiplets, security and coherent I/O. These are documented development themes; shipping feature attribution still requires a SKU-level document.", "公司披露涉及后续 CPU 研发，但本次资料未能确定具名第五代服务器产品的正式商用状态，因此保留为路线图项。当前技术方向包括更大的缓存与更好的管理算法、分支预测优化、模块化芯粒、安全及一致性 I/O。这些属于已披露的研发方向，具体已上市功能仍需 SKU 级文档确认。" ], "sources": [ "E07", "E04", "E01", "E12" ] } ] }, { "id": "07", "title": [ "CPU generation comparison", "CPU 代际对照" ], "blocks": [ { "id": "cpu", "type": "table", "table": "cpu" } ] }, { "id": "08", "title": [ "Workstation and edge derivatives", "工作站与边缘衍生产品" ], "blocks": [ { "id": "08.tier", "type": "prose", "text": [ "The 3000 and 5000 families matter because they expose how the server technology is scaled into smaller packages and platforms. In the second generation, the 5200 family has eight or sixteen cores, four DDR4 channels and 64 PCIe 3.0 lanes; the 3200 has four or eight cores, two channels and 32 lanes. Typical power ranges in the prospectus are 90–135 W and 45–105 W, respectively. These products extend the same software environment into workstation, edge and smaller-server deployments.", "3000 与 5000 系列体现服务器技术如何缩放到较小的封装及平台。第二代 5200 配八核或十六核、四通道 DDR4、64 条 PCIe 3.0 通道；3200 配四核或八核、双通道 DDR4、32 条 PCIe 3.0 通道。招股书列出的典型功耗分别为 90–135 W 和 45–105 W。这些产品把同一软件环境扩展到工作站、边缘及较小规模服务器。" ], "sources": [ "E03" ] }, { "id": "08.reuse", "type": "prose", "text": [ "The reuse advantage is compatibility and deployment tooling; the trade-off is less memory capacity and fewer attachment lanes. A workstation board using the same CPU family is not automatically an equivalent AI host: slot power, firmware support, memory population and NIC placement still constrain the system. No separate Hygon consumer graphics architecture is needed to explain the DCU line in the evidence reviewed here.", "复用优势主要体现在兼容性与部署工具，代价是内存容量及连接通道减少。使用同系列 CPU 的工作站主板，不会自动成为等效的 AI 主机：插槽供电、固件支持、内存配置及网卡位置仍会限制系统。本次证据中，无需引入独立的海光消费级图形架构来解释 DCU 产品线。" ], "sources": [ "E03", "E04" ] } ] }, { "id": "09", "title": [ "Deep Computing No. 1: the 2021 accelerator baseline", "深算一号：2021 年加速器基线" ], "blocks": [ { "id": "09.spec", "type": "prose", "text": [ "The IPO prospectus supplies an unusually concrete first-generation reference: 7 nm FinFET, 64 compute units containing 4,096 processing elements, 32 GB HBM2 on a 4,096-bit interface, 1,024 GB/s memory bandwidth, a 350 W TDP and PCIe 4.0 x16. It quotes two xGMI links and up to 184 GB/s, without a clear direction convention. That figure is preserved as an unnormalized vendor aggregate, not entered as a one-way bandwidth.", "招股书为第一代提供了较为完整的参考配置：7 nm FinFET、64 个计算单元及 4,096 个处理单元、4,096 位接口的 32 GB HBM2、1,024 GB/s 内存带宽、350 W TDP，以及 PCIe 4.0 x16。资料列出两条 xGMI 链路和最高 184 GB/s，但未明确方向口径。因此报告保留该原始聚合值，不把它写成单向带宽。" ], "sources": [ "E03" ] }, { "id": "09.execution", "type": "prose", "text": [ "The peer-reviewed depthwise-convolution study documents a 64-CU DCU with four SIMD16 units per CU, 64-thread wavefronts and 64 KB of shared memory per CU. Its kernel analysis explains the main portability issue: CUDA-like source structure can survive a move to HIP, but launch geometry, register use and shared-memory tiling must be retuned for the target. These observations apply to the tested device, not every later DCU.", "深度可分离卷积论文描述了所测 64-CU DCU：每个 CU 有四组 SIMD16，采用 64 线程波前，每个 CU 配 64 KB 共享内存。其算子分析揭示了迁移的核心问题：类似 CUDA 的源代码结构可以迁到 HIP，但启动配置、寄存器使用和共享内存分块仍需针对目标硬件重新调优。这些结论针对测试设备，不扩展为所有后续 DCU 的统一规格。" ], "sources": [ "R01" ] }, { "id": "09.software", "type": "prose", "text": [ "The first commercial generation established a practical software foothold. Baidu documented PaddlePaddle validation on Hygon 7000 CPUs and Z100 DCUs in 2021. Paddle Inference’s build guide subsequently identifies a Z100 configuration using ROCm 4.0.1 and source compilation. This is evidence of framework enablement and the software lineage; it does not make Z100 binary-compatible with NVIDIA CUDA or make the chip identical to an AMD accelerator.", "第一代商业产品建立了可用的软件基础。百度于 2021 年记录飞桨在海光 7000 CPU 和 Z100 DCU 上的验证；后续 Paddle Inference 编译文档列明 Z100 使用 ROCm 4.0.1，并通过源码构建。这证明框架支持与软件技术来源，不能据此认定 Z100 与 NVIDIA CUDA 二进制兼容，或与某款 AMD 加速器相同。" ], "sources": [ "E02", "P03" ] } ] }, { "id": "10", "title": [ "Deep Computing No. 2 and K100-class deployments", "深算二号与 K100 系列部署" ], "blocks": [ { "id": "10.milestone", "type": "prose", "text": [ "In November 2023 Hygon confirmed that Deep Computing No. 2 had been sold to commercial customers. Its statement describes general-purpose parallel computation with floating-point and integer support, but does not supply a complete dense-throughput and memory table. Claims of a broad performance uplift cannot be substituted for BF16, FP8 or FP64 rates without the workload and numerical format.", "2023 年 11 月，海光确认深算二号已向商业客户销售。公司将其描述为支持浮点及整型运算的通用并行计算产品，但未给出完整的稠密算力与内存规格表。泛化的性能提升描述，在缺少工作负载和数值格式时，不能代替 BF16、FP8 或 FP64 的具体速率。" ], "sources": [ "E11" ] }, { "id": "10.boards", "type": "prose", "text": [ "K100 and K100-AI appear in real research and system deployments. IHEP’s August 2025 presentation records six eight-card K100-AI servers, with 64 GB per PCIe card. Southeast University also documents a 64 GB, 400 W K100 AI card in a Hygon 7491 system. These establish useful board capacities and deployment scale. They do not establish a universal K100-AI peak compute rate, memory technology, or an authoritative mapping to Deep Computing No. 2 versus No. 3.", "K100 与 K100-AI 已出现在实际研究及系统部署中。高能所 2025 年 8 月报告记录了六台八卡 K100-AI 服务器，每张 PCIe 卡为 64 GB。东南大学设备资料也记录了搭载海光 7491 的系统以及 64 GB、400 W K100 AI 卡。这些资料确定了具体板卡容量与部署规模，但不足以建立适用于全部 K100-AI 的峰值算力、显存类型，或其与深算二号、三号的权威对应关系。" ], "sources": [ "C02", "P08" ] }, { "id": "10.bottleneck", "type": "prose", "text": [ "The architectural question shifts from whether an application runs to how much of the available system it uses. Eight cards increase aggregate memory capacity, but tensor parallelism also adds communication and synchronization. Capacity divided across devices is not automatically a coherent shared memory pool. Model placement must account for per-card capacity, replication, collective traffic and host staging. Deployment records are therefore more useful than multiplying an uncertain card peak by eight.", "架构问题从应用能否运行，转向能利用多少系统资源。八张卡提高了总显存容量，但张量并行也引入通信与同步。分布在多卡上的容量，不会自动成为缓存一致的共享内存池。模型部署必须考虑每卡容量、数据复制、集合通信和主机中转，因此实际部署记录比把不确定的单卡峰值乘以八更有价值。" ], "sources": [ "C02" ] } ] }, { "id": "11", "title": [ "Deep Computing No. 3 and implementation direction", "深算三号与实现技术方向" ], "blocks": [ { "id": "11.commercial", "type": "prose", "text": [ "Hygon’s review of 2025 states that Deep Computing No. 3 entered commercial use during that year. This advances the product timeline, but the public documents reviewed do not disclose enough silicon-level detail to reconstruct its compute-unit count, die count, HBM organization, dense BF16/FP8 rates or board power. The generation is included as shipping, while those fields remain n/d. The report does not use unverified KW-series aliases to fill them.", "海光对 2025 年的回顾明确深算三号在当年实现商业化。这推进了产品时间线，但已审阅公开资料尚不足以重建其计算单元数量、裸片数、HBM 组织、稠密 BF16／FP8 算力或板卡功耗。因此本代记为已商用，相关参数保留 n/d，不使用未经核实的 KW 系列别名补齐。" ], "sources": [ "E05" ] }, { "id": "11.implementation", "type": "prose", "text": [ "The 2026 interim report describes physically separated compute chiplets (XCD) and memory/I/O chiplets (MID), high-speed die-to-die interfaces, HIG resource partitioning, distributed SDMA and work on CPU–DCU security. It also records 2.5D packaging and 3D integration development. These disclosures show where the implementation effort is moving: separate compute scaling from I/O, isolate shared accelerator resources, and reduce movement across heterogeneous components. Their exact mapping to a commercial DCU generation is not disclosed.", "2026 年半年度报告描述了物理分离的计算芯粒 XCD 与内存／I/O 芯粒 MID、高速裸片互联、HIG 资源划分、分布式 SDMA，以及 CPU–DCU 安全协同，并披露 2.5D 封装和 3D 集成研发。这些信息表明实现重点正转向计算与 I/O 的独立扩展、共享加速器资源隔离，以及减少异构部件间的数据搬运；其与具体商业 DCU 代际的对应尚未披露。" ], "sources": [ "E01" ] }, { "id": "11.tradeoff", "type": "prose", "text": [ "Interpretation: separating compute and memory/I/O can allow different blocks to evolve at different rates, but introduces a die-to-die bandwidth and power budget. Resource partitioning can improve consolidation, yet usable isolation depends on scheduling, memory bandwidth, cache and DMA behavior together. Without package topology and measured partition behavior, neither the chiplet label nor a virtualization feature name is sufficient to estimate application scaling.", "架构解读：把计算与内存／I/O 分离，可使不同模块按各自节奏演进，但会引入裸片互联的带宽和功率预算。资源划分有助于提高共享利用率，实际隔离能力却取决于调度、内存带宽、缓存及 DMA 的共同表现。缺少封装拓扑和分区实测时，仅凭芯粒化或虚拟化功能名称，无法估计应用扩展效率。" ], "sources": [ "E01" ] }, { "id": "11.next", "type": "prose", "text": [ "An April 2026 investor question asked about CPU No. 5 and DCU No. 4. Hygon answered that CPU and DCU development and customer validation were proceeding according to plan, without confirming launch or delivery of either named item. This report therefore does not promote the proposed fourth DCU generation to shipping status.", "2026 年 4 月，有投资者询问海光五号 CPU 与深算四号 DCU 的发布及交付进展。公司回答称 CPU、DCU 正按规划推进研发与客户验证，未确认上述具名产品已发布或交付。因此本报告不把拟议的第四代 DCU 提升为已商用状态。" ], "sources": [ "E12" ] } ] }, { "id": "12", "title": [ "Accelerator comparison and software-visible identities", "加速器对照与软件可见型号" ], "blocks": [ { "id": "accelerator", "type": "table", "table": "accelerator" } ] }, { "id": "13", "title": [ "HSL, xGMI and the networking boundary", "HSL、xGMI 与网络产品边界" ], "blocks": [ { "id": "13.layers", "type": "prose", "text": [ "Three links must be kept distinct. PCIe connects a DCU to its host root complex. The first-generation prospectus names xGMI for DCU peer connections. HSL is the later CPU–xPU system-interconnect initiative, opened with ecosystem partners. Sharing a high-level purpose does not establish an identical wire protocol, coherence model or physical lane rate among these links.", "必须区分三类连接：PCIe 将 DCU 接到主机根复合体；第一代招股书用 xGMI 描述 DCU 对等互联；HSL 则是后续面向 CPU–xPU、与生态伙伴共同开放的系统互联方案。用途相近，并不意味着它们具有相同的线协议、一致性模型或物理通道速率。" ], "sources": [ "E03", "E05" ] }, { "id": "13.open", "type": "prose", "text": [ "The HSL 1.0 release includes a protocol stack, IP reference design and instruction-set material according to the company’s 2025 review. Openness here is an ecosystem design and licensing proposition; it does not by itself establish membership in UALink, UEC or CXL compliance programs. Actual coherence, DMA reachability and interoperability need to be established for each implementation.", "公司 2025 年回顾说明，HSL 1.0 开放内容包括协议栈、IP 参考设计和指令集材料。这里的开放首先是生态设计与授权安排，不能自动等同于参与 UALink、UEC，或通过 CXL 一致性测试。每种实现的缓存一致性、DMA 可达性及互操作性仍需分别核实。" ], "sources": [ "E05" ] }, { "id": "interconnect", "type": "table", "table": "interconnect" }, { "id": "13.network", "type": "prose", "text": [ "No merchant Hygon DPU, programmable SmartNIC or AI NIC with a separate model and datasheet was identified. The supported system boundary is third-party networking: H3C provides PCIe network-adapter attachment and an OCP option on the G5 platform. Port speeds, RDMA behavior, collective traffic placement and congestion control therefore belong to the selected NIC and fabric, not to the Hygon CPU or DCU merely because they share a server. The same applies to storage controllers and optics.", "本次未查到具备独立型号和数据手册的海光商用 DPU、可编程 SmartNIC 或 AI 网卡。可以核实的是第三方网络集成：新华三平台支持 PCIe 网卡，G5 另提供 OCP 选项。端口速率、RDMA 行为、集合通信流量路径及拥塞控制，因而属于所选网卡和网络，而不会仅因与海光 CPU／DCU 同机就成为海光芯片能力。存储控制器与光模块同理。" ], "sources": [ "P04", "P07" ] }, { "id": "network", "type": "table", "table": "network" } ] }, { "id": "14", "title": [ "Systems: commercial hosts and eight-card deployments", "系统：商用主机与八卡部署" ], "blocks": [ { "id": "14.system", "type": "prose", "text": [ "The system evidence spans two useful scales. OEM host specifications establish socket count, memory generation, I/O expansion and processor power. IHEP establishes an operational multi-node DCU installation and its application work. A six-node installation with eight accelerators per node proves a deployment configuration, but does not prove a 48-device hardware scale-up domain. Network topology, collective implementation and measured scaling must be provided separately.", "系统证据覆盖两种有用尺度：整机规格确定插槽数、内存代际、I/O 扩展和处理器功率；高能所资料则确定多节点 DCU 部署及其应用工作。六节点、每节点八卡的集群证明一种部署配置，不能证明存在 48 设备的硬件纵向扩展域。网络拓扑、集合通信实现和扩展实测仍需单独提供。" ], "sources": [ "P04", "P07", "C02" ] }, { "id": "systems", "type": "table", "table": "systems" }, { "id": "14.power", "type": "prose", "text": [ "Power must be budgeted at the same scope as capacity. Eight 400 W cards would alone require a derived 3.2 kW, but that calculation is an illustrative configuration using P08’s card power, not a measured IHEP node rating. CPU packages, DIMMs, NICs, fans and power-conversion losses add to the node budget. Neither card TDP nor processor maximum power establishes rack power or liquid-cooling requirements.", "功率预算必须与容量采用相同范围。若采用八张 400 W 卡，仅板卡就需推算 3.2 kW，但这是使用 P08 单卡功率的示例配置，不是高能所节点的实测额定功率。CPU、DIMM、网卡、风扇和电源转换损耗还需另计。板卡 TDP 或处理器最大功率，都不能直接确定机架功率或液冷要求。" ], "sources": [ "P08", "C02" ] } ] }, { "id": "15", "title": [ "Software: from ROCm/HIP enablement to DTK", "软件：从 ROCm／HIP 支持到 DTK" ], "blocks": [ { "id": "15.layers", "type": "prose", "text": [ "DTK is the software foundation for Hygon’s accelerator ecosystem. The useful abstraction is a stack: driver and runtime, compiler and programming model, mathematical and neural-network kernels, framework integration, and application serving. Paddle’s early Z100 instructions expose the ROCm/HIP foundation; later company disclosures describe DTK, application components and model-adaptation work. A framework importing successfully is only the first stage: operator coverage, numerical behavior and distributed execution determine whether production workloads are practical.", "DTK 是海光加速器生态的软件基础。应按层次理解：驱动与运行时、编译器及编程模型、数学与神经网络算子、框架集成，以及应用服务。飞桨早期 Z100 文档展示了 ROCm／HIP 基础，后续公司披露则覆盖 DTK、应用组件和模型适配。框架能够成功加载只是第一步；算子覆盖、数值行为与分布式执行能力，才决定生产负载是否实用。" ], "sources": [ "P03", "P09", "E04" ] }, { "id": "15.portability", "type": "prose", "text": [ "HIP can preserve much of a CUDA-style host/device programming structure. It does not preserve every library ABI, inline PTX fragment, warp-level assumption or kernel tuning choice. The convolution studies give concrete reasons to revisit data reuse, occupancy and memory tiling. The 2025 diverse-precision paper’s abstract reports separate FP16 and FP32 results and end-to-end network effects; this is application optimization evidence, not a chip peak-throughput specification.", "HIP 可以保留大量 CUDA 风格的主机／设备编程结构，但不会保留所有库 ABI、内联 PTX、warp 级假设或算子调优参数。卷积研究提供了重新优化数据复用、占用率和内存分块的具体依据。2025 年不同精度卷积论文的摘要分别报告 FP16、FP32 及端到端网络效果；这些是应用优化证据，不是芯片峰值算力规格。" ], "sources": [ "R01", "R03", "P03" ] }, { "id": "15.security", "type": "prose", "text": [ "The security trajectory extends from host secure boot and encryption toward CPU–DCU coordinated protection. CSV 3.0 and HIG appear in the 2026 technical disclosures. For deployment, the important distinction is between a named capability and a verified isolation boundary: attestation, trusted firmware, memory protection, DMA access and partition scheduling all need compatible versions. HYGON-AI’s public repositories include DAS adaptations of vLLM, SGLang, Mooncake and Megatron-LM. Their descriptions use the HCU hardware label; this is recorded as a software-visible identity without inventing a mapping to a new silicon generation.", "安全能力从主机安全启动与加密，扩展到 CPU–DCU 协同保护。CSV 3.0 与 HIG 出现在 2026 年技术披露中。部署时应区分功能名称与已验证的隔离边界：证明机制、可信固件、内存保护、DMA 访问和分区调度都需要兼容版本。HYGON-AI 公开仓库包括 vLLM、SGLang、Mooncake 和 Megatron-LM 的 DAS 适配。仓库描述使用 HCU 硬件名称；报告将其记录为软件可见标识，不据此虚构新的芯片代际映射。" ], "sources": [ "E01", "P10" ] }, { "id": "software", "type": "table", "table": "software" } ] }, { "id": "16", "title": [ "Implementation trends and architectural trade-offs", "实现技术趋势与架构权衡" ], "blocks": [ { "id": "16.chiplet", "type": "prose", "text": [ "The first-generation Dhyana reference already uses multiple dies. The later development story is therefore not simply a move from monolithic to chiplet. It is a move toward more specialized chiplet roles, richer packaging and a broader system interface. The 2025 annual report describes modular chiplet design, DDR/HBM controller IP, coherent data-fabric IP and advanced cache and interface work. A future package can trade yield and reuse against fabric latency and energy, but the public evidence does not quantify those costs per generation.", "第一代 Dhyana 参考配置已采用多裸片，因此后续故事并非简单的单片到芯粒。演进方向是更专门化的芯粒角色、更复杂的封装及更广的系统接口。2025 年年报描述模块化芯粒设计、DDR／HBM 控制器 IP、一致性数据互联 IP，以及缓存和接口研发。未来封装可在良率、复用与互联延迟、能耗之间权衡，但公开证据尚未逐代量化这些成本。" ], "sources": [ "R02", "E04" ] }, { "id": "16.memory", "type": "prose", "text": [ "Memory scaling is more measurable in early products than current DCUs. The 7200 reference gives a clean per-core DDR baseline; the first DCU gives a clean HBM-bandwidth baseline. Current board capacity is visible in deployment records, while comparable dense BF16/FP8 peaks are not. Consequently, a purported generational bytes-per-FLOP curve would be misleading. The correct comparison retains missing ratios rather than combining unrelated SKUs or numerical formats.", "早期产品的内存扩展更容易量化。7200 提供明确的每核 DDR 基线，第一代 DCU 提供明确的 HBM 带宽基线。当前板卡容量可从部署资料核实，但可比的稠密 BF16／FP8 峰值尚不完整。因此不能绘制看似连续、实则混合不同 SKU 或精度的每 FLOP 字节数曲线；应保留缺失比值。" ], "sources": [ "E03", "C02" ] }, { "id": "16.host", "type": "prose", "text": [ "The CPU remains consequential in accelerator systems. It handles scheduling, data preparation, storage and network services, and often the serial portion of scientific solvers. HSL potentially changes the cost of crossing the CPU–accelerator boundary; it does not eliminate memory hierarchy or contention. The highest-value next disclosures would be a coherent topology diagram, per-direction link rates, host-memory access behavior, a supported partition matrix and workload-level scaling measurements.", "CPU 在加速系统中仍然重要：它承担调度、数据准备、存储与网络服务，以及科学求解器中的串行部分。HSL 有望改变跨越 CPU–加速器边界的成本，但不会消除存储层次或资源竞争。最有价值的后续披露包括一致性拓扑图、单向链路速率、主机内存访问行为、受支持的分区矩阵，以及工作负载级扩展实测。" ], "sources": [ "R02", "E05" ] } ] }, { "id": "17", "title": [ "Integrated stack across three eras", "三个阶段的完整基础设施视图" ], "blocks": [ { "id": "17.intro", "type": "prose", "text": [ "The figures describe supported architectural relationships, not undocumented product wiring. Partner networking and storage remain outside Hygon’s documented chip portfolio. The last figure is the disclosed integration direction, with deployment details left to specific systems.", "下图表示有证据支持的架构关系，不推定未披露的实际布线。伙伴网络和存储仍置于海光已核实芯片产品组合之外。最后一图表示已披露的集成方向，具体部署细节依系统确定。" ], "sources": [ "E03", "C02", "E05", "E01" ] }, { "id": "era1", "type": "figure", "figure": "era1" }, { "id": "era2", "type": "figure", "figure": "era2" }, { "id": "era3", "type": "figure", "figure": "era3" } ] }, { "id": "18", "title": [ "Bandwidth hierarchy and derived ratios", "带宽层次与推算比值" ], "blocks": [ { "id": "bandwidth", "type": "table", "table": "bandwidth" }, { "id": "ratios", "type": "table", "table": "ratios" } ] }, { "id": "19", "title": [ "Conference-to-product index and search coverage", "会议到产品索引与检索覆盖" ], "blocks": [ { "id": "conference", "type": "table", "table": "conference" }, { "id": "19.audit", "type": "prose", "text": [ "Searches covered Hygon, Haiguang, Dhyana, C86 and DCU with ISCA, MICRO, HPCA, ASPLOS, Hot Chips, ISSCC and DAC. No primary product-architecture or circuit paper was verified for a complete Hygon generation in those venues. Search hits included author affiliations, patents citing conference work and papers referencing Hygon research; these are not product disclosures. This is a result of this source audit, not a claim that Hygon has never participated.", "检索组合覆盖 Hygon、Haiguang、Dhyana、C86、DCU 与 ISCA、MICRO、HPCA、ASPLOS、Hot Chips、ISSCC、DAC。本次未核实到这些会议中能够披露海光完整产品代际的一手架构或电路论文。命中项包括作者单位、引用会议工作的专利，以及引用海光相关研究的论文，均不能作为产品披露。这是本次来源核查结果，不代表海光从未参会。" ], "sources": [ "R01", "R02", "R03", "P05" ] }, { "id": "19.venues", "type": "prose", "text": [ "SC/ISC, interconnect and systems venues, and industry events such as MWC, Computex, OCP, GTC, re:Invent, Ignite and Google Cloud Next were considered as possible deployment channels. No specific Hygon product talk at these events was used to establish a specification. The strongest verified event material here comes from Hygon’s own launch ecosystem, HAIC and the IHEP system presentation. The missing Hot Chips/ISSCC layer is not replaced with AMD papers about later Zen or CDNA products.", "SC／ISC、互联与系统会议，以及 MWC、Computex、OCP、GTC、re:Invent、Ignite、Google Cloud Next 等产业活动，作为潜在部署披露渠道纳入考虑。本报告未使用这些活动中某个未经核实的海光产品演讲来确定规格。已核实的重点活动材料来自海光自身发布生态、HAIC 及高能所系统报告。缺失的 Hot Chips／ISSCC 层信息，不用后续 AMD Zen 或 CDNA 产品论文替代。" ], "sources": [ "C03", "E05", "C02" ] } ] }, { "id": "20", "title": [ "Names, product boundaries and remaining disclosures", "命名、产品边界与待补披露" ], "blocks": [ { "id": "crosswalk", "type": "table", "table": "crosswalk" }, { "id": "20.gaps", "type": "prose", "text": [ "The highest-impact disclosure gaps are concentrated, not universal: later CPU core and cache organization; a complete DCU generation-to-board map; dense numerical-format throughput; HBM stacks and bandwidth on newer silicon; link direction and domain limits; and the association of packaging, virtualization and security features with commercial SKUs. The established story is already clear: a compatible server CPU base expanded into a general-purpose accelerator ecosystem, then toward a more tightly integrated CPU–xPU platform. The next architecture comparison should test that integration at the workload level.", "关键披露缺口集中在若干方面：后续 CPU 核心与缓存组织、完整 DCU 代际到板卡映射、各数值格式的稠密算力、新芯片 HBM 堆栈和带宽、互联方向与域上限，以及封装、虚拟化、安全能力对应的商业 SKU。已确定的演进主线清晰：兼容服务器 CPU 基础扩展成通用加速器生态，再走向更紧密的 CPU–xPU 平台。下一步架构比较应在工作负载层面检验这种集成。" ], "sources": [ "E03", "P04", "E05", "E01" ] } ] } ], "tables": { "headline": { "id": "headline", "title": [ "Selected anchors across generations", "各代际的关键技术锚点" ], "headers": [ [ "Anchor", "锚点" ], [ "CPU / host", "CPU／主机" ], [ "Accelerator / memory", "加速器／内存" ], [ "Integration", "集成方式" ] ], "rows": [ { "id": "a1", "values": [ [ "2018–2020 baseline", "2018–2020 基线" ], [ "Dhyana: 32 cores; 4 dies", "Dhyana：32 核；4 裸片" ], [ "Early heterogeneous research systems", "早期异构研究系统" ], [ "PCIe; NUMA-aware placement", "PCIe；感知 NUMA 的部署" ] ], "sources": [ "R02" ] }, { "id": "a2", "values": [ [ "2021–2022", "2021–2022" ], [ "7200: 170.624 GB/s derived DDR peak", "7200：DDR 理论峰值推算为 170.624 GB/s" ], [ "No. 1: 32 GB HBM2; 1.024 TB/s", "深算一号：32 GB HBM2；1.024 TB/s" ], [ "PCIe 4.0 x16 on DCU; host may limit rate", "DCU 端 PCIe 4.0 x16；速率仍受主机限制" ] ], "sources": [ "E03" ] }, { "id": "a3", "values": [ [ "2024–2025 deployment", "2024–2025 部署" ], [ "Generation 3; DDR4 host ecosystem", "第三代；DDR4 主机生态" ], [ "IHEP: 6 nodes × 8 K100-AI; 64 GB/card", "高能所：6 节点×8 张 K100-AI；每卡 64 GB" ], [ "Actual eight-card servers; link-domain limit n/d", "实际八卡服务器；互联域上限 n/d" ] ], "sources": [ "P07", "C02" ] }, { "id": "a4", "values": [ [ "2025–2026 platform", "2025–2026 平台" ], [ "C86-4G: 64 cores/socket; DDR5-5600 platform", "C86-4G：每颗 64 核；DDR5-5600 平台" ], [ "No. 3 commercial; dense BF16/FP8 n/d", "深算三号已商用；稠密 BF16／FP8 n/d" ], [ "HSL 1.0; DTK; CPU–DCU security work", "HSL 1.0；DTK；CPU–DCU 安全协同" ] ], "sources": [ "P04", "E05", "E01" ] } ], "panels": [ [ 0, 1, 2, 3 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "cpu": { "id": "cpu", "title": [ "CPU comparison: reference products, not inferred Zen equivalents", "CPU 对照：以海光参考产品为准，不推定对应 Zen 代际" ], "headers": [ [ "Generation / reference SKU", "代际／参考 SKU" ], [ "Codename", "代号" ], [ "GA", "正式商用" ], [ "Status", "状态" ], [ "Core µarch", "核心微架构" ], [ "Cores / threads", "核心／线程" ], [ "Process per die", "各裸片工艺" ], [ "Dies / packaging", "裸片／封装" ], [ "L2 per core", "每核 L2" ], [ "L3 / domain", "L3／共享域" ], [ "Memory: channels; rate; GB/s", "内存：通道；速率；GB/s" ], [ "Sockets / links", "插槽／互联" ], [ "PCIe / CXL", "PCIe／CXL" ], [ "TDP", "TDP" ], [ "Vector / matrix ISA", "向量／矩阵 ISA" ] ], "rows": [ { "id": "g1", "values": [ [ "No. 1 / 7100", "海光一号／7100" ], [ "Dhyana", "Dhyana" ], [ "2018-04 production", "2018-04 量产" ], [ "Historical shipping", "历史已商用" ], [ "Licensed origin; Hygon Family 18h", "授权起点；Hygon Family 18h" ], [ "32 / 64", "32 / 64" ], [ "14 nm", "14 nm" ], [ "4 dies; 2 CCX/die", "4 裸片；每裸片 2 CCX" ], [ "512 KB", "512 KB" ], [ "64 MB; 8 MB / 4 cores", "64 MB；每 4 核 8 MB" ], [ "n/d", "n/d" ], [ "Multi-socket; link rate n/d", "多路；链路速率 n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "AVX / AVX2", "AVX / AVX2" ] ], "sources": [ "E03", "R02", "P05" ] }, { "id": "g2", "values": [ [ "No. 2 / 7200", "海光二号／7200" ], [ "n/d", "n/d" ], [ "2020-01 production", "2020-01 量产" ], [ "Historical shipping", "历史已商用" ], [ "Hygon C86; details n/d", "海光 C86；细节 n/d" ], [ "32 / 64", "32 / 64" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "512 KB", "512 KB" ], [ "32 / 64 MB; domain n/d", "32／64 MB；共享域 n/d" ], [ "DDR4; 8; 2666 MT/s; 170.624 GB/s", "DDR4; 8; 2666 MT/s; 170.624 GB/s" ], [ "2P observed; links n/d", "已验证双路；链路 n/d" ], [ "128 PCIe 3.0 lanes, shared uses; CXL n/d", "128 条 PCIe 3.0 通道，多用途；CXL n/d" ], [ "225 W typical upper value", "典型功耗上限值 225 W" ], [ "n/d", "n/d" ] ], "sources": [ "E03" ] }, { "id": "g3", "values": [ [ "No. 3 / 7300 platform", "海光三号／7300 平台" ], [ "n/d", "n/d" ], [ "2022 small-volume sales", "2022 小批量销售" ], [ "Shipping / available", "已商用／可获取" ], [ "Hygon C86; details n/d", "海光 C86；细节 n/d" ], [ "32 cores; threads n/d in OEM brief", "32 核；整机简表线程数 n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "DDR4; channels n/d; up to 3200 MT/s; GB/s n/d", "DDR4；通道 n/d；最高 3200 MT/s；GB/s n/d" ], [ "2P platform; links n/d", "双路平台；链路 n/d" ], [ "PCIe 4.0/3.0 platform; CXL n/d", "PCIe 4.0／3.0 平台；CXL n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ] ], "sources": [ "E07", "P07", "C03" ] }, { "id": "g4", "values": [ [ "No. 4 / C86-4G", "海光四号／C86-4G" ], [ "n/d", "n/d" ], [ "Available by cutoff; exact GA n/d", "截至资料截止已可获取；精确 GA n/d" ], [ "Shipping / available", "已商用／可获取" ], [ "Hygon C86; details n/d", "海光 C86；细节 n/d" ], [ "64 cores; SMT; max threads n/d", "64 核；SMT；最高线程数 n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "DDR5; channels n/d; up to 5600 MT/s; GB/s n/d", "DDR5；通道 n/d；最高 5600 MT/s；GB/s n/d" ], [ "2P; links n/d", "双路；链路 n/d" ], [ "PCIe 5.0 platform; CXL SKU mapping n/d", "PCIe 5.0 平台；CXL SKU 映射 n/d" ], [ "400 W processor maximum", "处理器最大 400 W" ], [ "n/d", "n/d" ] ], "sources": [ "P04" ] }, { "id": "g5", "values": [ [ "No. 5", "海光五号" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "Roadmap", "路线图" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ] ], "sources": [ "E07" ] } ], "panels": [ [ 0, 1, 2, 3, 4, 5 ], [ 0, 6, 7, 8, 9 ], [ 0, 10, 11, 12, 13, 14 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "accelerator": { "id": "accelerator", "title": [ "DCU comparison", "DCU 对照" ], "headers": [ [ "Product", "产品" ], [ "Architecture", "架构" ], [ "GA / milestone", "商用／里程碑" ], [ "Status", "状态" ], [ "Process", "工艺" ], [ "Dies / packaging", "裸片／封装" ], [ "Compute units", "计算单元" ], [ "Dense BF16", "稠密 BF16" ], [ "Dense FP8", "稠密 FP8" ], [ "Dense FP6 / FP4", "稠密 FP6／FP4" ], [ "FP64 vector / matrix", "FP64 向量／矩阵" ], [ "Memory: type; stacks; GB; TB/s", "内存：类型；堆栈；GB；TB/s" ], [ "LLC / SRAM", "末级缓存／SRAM" ], [ "Scale-up: links; GB/s per direction; domain", "纵向扩展：链路；单向 GB/s；域" ], [ "Host link", "主机连接" ], [ "Power / cooling", "功耗／散热" ], [ "Form factor", "形态" ] ], "rows": [ { "id": "d1", "values": [ [ "Deep Computing No. 1", "深算一号" ], [ "GPGPU; commercial codename n/d", "GPGPU；商业代号 n/d" ], [ "2021 commercial", "2021 商用" ], [ "Historical shipping", "历史已商用" ], [ "7 nm FinFET", "7 nm FinFET" ], [ "Die count n/d; HBM package", "裸片数 n/d；HBM 封装" ], [ "64 CUs / 4096", "64 CUs / 4096" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "HBM2; stacks n/d; 32 GB; 1.024 TB/s", "HBM2; stacks n/d; 32 GB; 1.024 TB/s" ], [ "n/d", "n/d" ], [ "2 xGMI; 184 GB/s quoted, direction n/d; domain n/d", "2 条 xGMI；原值 184 GB/s，方向 n/d；域 n/d" ], [ "PCIe 4.0 x16", "PCIe 4.0 x16" ], [ "350 W TDP; cooling n/d", "350 W TDP；散热 n/d" ], [ "n/d", "n/d" ] ], "sources": [ "E03" ] }, { "id": "d2", "values": [ [ "Deep Computing No. 2", "深算二号" ], [ "GPGPU", "GPGPU" ], [ "By 2023-11 commercial", "截至 2023-11 已商用" ], [ "Shipping / available", "已商用／可获取" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ] ], "sources": [ "E11" ] }, { "id": "d3", "values": [ [ "Deep Computing No. 3", "深算三号" ], [ "GPGPU", "GPGPU" ], [ "2025 commercial", "2025 商用" ], [ "Shipping / available", "已商用／可获取" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ] ], "sources": [ "E05" ] }, { "id": "k100ai", "values": [ [ "K100-AI deployment reference", "K100-AI 部署参考" ], [ "Generation crosswalk n/d", "代际映射 n/d" ], [ "2024–2025 deployed", "2024–2025 已部署" ], [ "Shipping / available", "已商用／可获取" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "64 GB; type, stacks, bandwidth n/d", "64 GB；类型、堆栈及带宽 n/d" ], [ "n/d", "n/d" ], [ "8-card servers observed; link/domain maximum n/d", "观察到八卡服务器；链路／域上限 n/d" ], [ "PCIe", "PCIe" ], [ "400 W in P08 configuration; cooling n/d", "P08 配置为 400 W；散热 n/d" ], [ "PCIe card", "PCIe 板卡" ] ], "sources": [ "C02", "P08" ] } ], "panels": [ [ 0, 1, 2, 3, 4, 5, 6 ], [ 0, 7, 8, 9, 10, 11 ], [ 0, 12, 13, 14, 15, 16 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "interconnect": { "id": "interconnect", "title": [ "Interconnect inventory", "互联技术表" ], "headers": [ [ "Interconnect", "互联" ], [ "Year / generation", "年份／代际" ], [ "Lane rate", "通道速率" ], [ "Lanes / link", "每链路通道" ], [ "GB/s per link per direction", "每链路单向 GB/s" ], [ "Links / device", "每设备链路" ], [ "Topology", "拓扑" ], [ "Domain limit", "域规模" ], [ "Coherence / semantics", "一致性／语义" ] ], "rows": [ { "id": "pcie", "values": [ [ "PCIe host path", "PCIe 主机通路" ], [ "Gen3 → Gen4 → Gen5 platforms", "Gen3 → Gen4 → Gen5 平台" ], [ "8 / 16 / 32 GT/s", "8 / 16 / 32 GT/s" ], [ "x16 reference", "x16 参考" ], [ "15.754 / 31.508 / 63.015", "15.754 / 31.508 / 63.015" ], [ "Board dependent", "依主板" ], [ "Root complex / switch", "根复合体／交换机" ], [ "n/a", "n/a" ], [ "I/O transport; no assumed cache coherence", "I/O 传输；不默认缓存一致性" ] ], "sources": [ "E03", "P07", "P04" ] }, { "id": "xgmi", "values": [ [ "xGMI, No. 1", "深算一号 xGMI" ], [ "2021", "2021" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "2", "2" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "Peer-link semantics n/d", "对等连接语义 n/d" ] ], "sources": [ "E03" ] }, { "id": "hsl", "values": [ [ "HSL 1.0", "HSL 1.0" ], [ "2025-12", "2025-12" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "CPU–xPU ecosystem", "CPU–xPU 生态" ], [ "n/d", "n/d" ], [ "Tightly coupled integration; exact public protocol details n/d", "紧耦合集成；公开协议细节 n/d" ] ], "sources": [ "E05" ] } ], "panels": [ [ 0, 1, 2, 3, 4 ], [ 0, 5, 6, 7, 8 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "network": { "id": "network", "title": [ "Networking scope", "网络覆盖范围" ], "headers": [ [ "Product", "产品" ], [ "GA / milestone", "商用／里程碑" ], [ "Status", "状态" ], [ "Class", "类别" ], [ "Ports × speed", "端口×速率" ], [ "SerDes", "SerDes" ], [ "Host interface", "主机接口" ], [ "Programmable engine", "可编程引擎" ], [ "Embedded CPU", "嵌入式 CPU" ], [ "On-card memory", "板载内存" ], [ "Transport / RDMA", "传输／RDMA" ], [ "Congestion control", "拥塞控制" ], [ "Key offloads", "主要卸载" ], [ "Power", "功耗" ] ], "rows": [ { "id": "partner", "values": [ [ "Partner NICs in Hygon servers", "海光服务器中的伙伴网卡" ], [ "Platform-dependent", "依平台" ], [ "Shipping / available", "已商用／可获取" ], [ "Integration layer; not Hygon-owned SKU", "集成层；非海光自有 SKU" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "PCIe / OCP", "PCIe / OCP" ], [ "Adapter-dependent", "依网卡" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "Adapter/fabric-dependent", "依网卡／网络" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ] ], "sources": [ "P04", "P07" ] } ], "panels": [ [ 0, 1, 2, 3, 4, 5, 6 ], [ 0, 7, 8, 9, 10, 11, 12, 13 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "systems": { "id": "systems", "title": [ "Reference systems", "参考系统" ], "headers": [ [ "Platform", "平台" ], [ "Year / milestone", "年份／里程碑" ], [ "CPU / accelerator count", "CPU／加速器数量" ], [ "Scale-up domain", "纵向扩展域" ], [ "Scale-out per accelerator", "每加速器横向带宽" ], [ "Rack power", "机架功耗" ], [ "Cooling", "散热" ] ], "rows": [ { "id": "g5", "values": [ [ "H3C R4930 G5", "H3C R4930 G5" ], [ "Current documentation", "现行文档" ], [ "2 × generation 2/3 CPUs; accelerator options", "2 颗第二／三代 CPU；可选加速器" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "Platform fans; configuration dependent", "平台风扇；依配置" ] ], "sources": [ "P07" ] }, { "id": "g7", "values": [ [ "H3C R4930 G7", "H3C R4930 G7" ], [ "Current documentation", "现行文档" ], [ "2 × C86-4G; up to 128 CPU cores", "2 颗 C86-4G；最高 128 CPU 核" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "Server configuration dependent", "依服务器配置" ] ], "sources": [ "P04" ] }, { "id": "ihep", "values": [ [ "IHEP AI DCU installation", "高能所 AI DCU 部署" ], [ "2024–2025", "2024–2025" ], [ "6 × 8 K100-AI; CPU model n/d here", "6×8 张 K100-AI；此处 CPU 型号 n/d" ], [ "8 cards/node; protocol domain n/d", "每节点 8 卡；协议域 n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ] ], "sources": [ "C02" ] }, { "id": "seu", "values": [ [ "SEU equipment reference", "东南大学设备参考" ], [ "Available by cutoff", "截至资料截止已可获取" ], [ "2 × Hygon 7491; 1 × K100 AI 64 GB", "2 颗海光 7491；1 张 64 GB K100 AI" ], [ "n/a", "n/a" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "N+1 cooling; dual PSU", "N+1 散热；双电源" ] ], "sources": [ "P08" ] } ], "panels": [ [ 0, 1, 2, 3 ], [ 0, 4, 5, 6 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "software": { "id": "software", "title": [ "Software milestones", "软件里程碑" ], "headers": [ [ "Release / evidence", "版本／证据" ], [ "Date", "日期" ], [ "Hardware enabled", "支持硬件" ], [ "Key features", "主要内容" ] ], "rows": [ { "id": "sw1", "values": [ [ "Paddle validation", "飞桨验证" ], [ "2021", "2021" ], [ "Hygon 7000 + Z100", "海光 7000 + Z100" ], [ "Framework compatibility validation", "框架兼容性验证" ] ], "sources": [ "E02" ] }, { "id": "sw2", "values": [ [ "Paddle Inference guide", "Paddle Inference 指南" ], [ "Historical published guide", "历史公开指南" ], [ "Z100 / ROCm 4.0.1", "Z100 / ROCm 4.0.1" ], [ "Source build; driver/runtime environment", "源码构建；驱动／运行时环境" ] ], "sources": [ "P03" ] }, { "id": "sw3", "values": [ [ "Research kernel optimization", "研究算子优化" ], [ "2024–2025", "2024–2025" ], [ "Tested DCU configurations", "论文测试 DCU 配置" ], [ "HIP; MIOpen baseline; tuned memory reuse", "HIP；MIOpen 基线；内存复用调优" ] ], "sources": [ "R01", "R03" ] }, { "id": "sw4", "values": [ [ "DTK and ecosystem disclosure", "DTK 与生态披露" ], [ "2025–2026", "2025–2026" ], [ "CPU + DCU portfolio; exact version matrix n/d", "CPU + DCU 产品组合；精确版本矩阵 n/d" ], [ "Compilers, kernels, model adaptation; security and virtualization development", "编译器、算子、模型适配；安全与虚拟化研发" ] ], "sources": [ "E04", "E01" ] } ], "panels": [ [ 0, 1, 2, 3 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "bandwidth": { "id": "bandwidth", "title": [ "Bandwidth hierarchy by evidence era", "按证据阶段整理的带宽层次" ], "headers": [ [ "Era / reference", "阶段／参考" ], [ "On-die / die-to-die", "片内／裸片互联" ], [ "Memory", "内存" ], [ "CPU–DCU", "CPU–DCU" ], [ "Scale-up / accelerator", "每加速器纵向扩展" ], [ "Scale-out / accelerator", "每加速器横向扩展" ] ], "rows": [ { "id": "b1", "values": [ [ "7200 + No. 1 DCU", "7200 + 深算一号 DCU" ], [ "n/d", "n/d" ], [ "CPU 170.624 GB/s; DCU 1024 GB/s", "CPU 170.624 GB/s；DCU 1024 GB/s" ], [ "DCU Gen4 x16 31.508 GB/s/direction; Gen3 host caps at 15.754", "DCU Gen4 x16 单向 31.508 GB/s；Gen3 主机上限 15.754" ], [ "184 GB/s quoted; direction n/d", "原值 184 GB/s；方向 n/d" ], [ "n/d", "n/d" ] ], "sources": [ "E03" ] }, { "id": "b2", "values": [ [ "K100-AI deployment", "K100-AI 部署" ], [ "n/d", "n/d" ], [ "64 GB/card; bandwidth n/d", "每卡 64 GB；带宽 n/d" ], [ "PCIe; negotiated rate n/d", "PCIe；协商速率 n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ] ], "sources": [ "C02" ] }, { "id": "b3", "values": [ [ "C86-4G / HSL era", "C86-4G／HSL 阶段" ], [ "n/d", "n/d" ], [ "DDR5-5600 platform; channel map n/d", "DDR5-5600 平台；通道图 n/d" ], [ "Gen5 x16 ceiling 63.015 GB/s/direction; HSL n/d", "Gen5 x16 单向上限 63.015 GB/s；HSL n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ] ], "sources": [ "P04", "E05" ] } ], "panels": [ [ 0, 1, 2, 3 ], [ 0, 4, 5 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "ratios": { "id": "ratios", "title": [ "Reproducible ratios and their limits", "可复算比值及适用范围" ], "headers": [ [ "Metric", "指标" ], [ "Calculation", "计算" ], [ "Result", "结果" ], [ "Scope / limit", "范围／限制" ] ], "rows": [ { "id": "r1", "values": [ [ "7200 DDR bandwidth/core", "7200 每核 DDR 带宽" ], [ "8 × 2666 × 10^6 × 8 / 32", "8 × 2666 × 10^6 × 8 / 32" ], [ "5.332 GB/s/core", "5.332 GB/s/core" ], [ "Derived; 32-core SKU at peak rate", "推算；32 核 SKU 最高速率" ] ], "sources": [ "E03" ] }, { "id": "r2", "values": [ [ "7200 L3/core, 64 MB SKU", "7200 每核 L3，64 MB SKU" ], [ "64 / 32", "64 / 32" ], [ "2 MB/core", "2 MB/core" ], [ "Arithmetic average; not private cache", "算术平均；不是私有缓存" ] ], "sources": [ "E03" ] }, { "id": "r3", "values": [ [ "No. 1 HBM / Gen4 x16", "深算一号 HBM／Gen4 x16" ], [ "1024 / 31.508", "1024 / 31.508" ], [ "32.50×", "32.50×" ], [ "Memory bandwidth vs one-way link ceiling", "内存带宽与单向链路上限之比" ] ], "sources": [ "E03" ] }, { "id": "r4", "values": [ [ "8-card capacity", "八卡容量" ], [ "8 × 64 GB", "8 × 64 GB" ], [ "512 GB", "512 GB" ], [ "K100-AI node aggregate; not unified memory", "K100-AI 节点总量；不是统一内存" ] ], "sources": [ "C02" ] }, { "id": "r5", "values": [ [ "HBM bytes / dense BF16 or FP8 FLOP", "HBM 字节／稠密 BF16 或 FP8 FLOP" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "No matched format/throughput denominator", "缺少对应精度／算力分母" ] ], "sources": [ "E03", "E05", "C02" ] }, { "id": "r6", "values": [ [ "Scale-up/HBM; scale-out/card; FLOP/W", "纵向互联／HBM；横向带宽／卡；FLOP/W" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "Direction, NIC mapping or compute/power pair missing", "缺少方向、网卡映射或算力／功耗配对" ] ], "sources": [ "E03", "C02", "P08" ] } ], "panels": [ [ 0, 1, 2, 3 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "conference": { "id": "conference", "title": [ "Verified disclosures and research anchors", "已核实披露与研究锚点" ], "headers": [ [ "Venue", "会议／活动" ], [ "Year", "年份" ], [ "Paper / talk / disclosure", "论文／演讲／披露" ], [ "Presenter / authors", "报告人／作者" ], [ "Product", "产品" ], [ "Evidence type", "证据类型" ], [ "Source", "来源" ] ], "rows": [ { "id": "c1", "values": [ [ "Hygon spring launch", "海光春季发布会" ], [ "2022", "2022" ], [ "CPU No. 3 and heterogeneous platform launch", "海光三号及异构平台发布" ], [ "Hygon; named speaker n/d", "海光；具名报告人 n/d" ], [ "No. 3 CPU + DCU", "海光三号 CPU + DCU" ], [ "Company product event", "公司产品活动" ], [ "C03", "C03" ] ], "sources": [ "C03" ] }, { "id": "c2", "values": [ [ "HAIC", "HAIC" ], [ "2025", "2025" ], [ "HSL 1.0 specification release", "HSL 1.0 规范发布" ], [ "Hygon and ecosystem partners", "海光及生态伙伴" ], [ "HSL 1.0", "HSL 1.0" ], [ "System / interconnect; issuer recap", "系统／互联；公司回顾" ], [ "E05", "E05" ] ], "sources": [ "E05" ] }, { "id": "c3", "values": [ [ "IHEP technical presentation", "高能所技术报告" ], [ "2025", "2025" ], [ "AI@IHEPCC", "AI@IHEPCC" ], [ "IHEP computing team", "高能所计算团队" ], [ "K100 / K100-AI", "K100 / K100-AI" ], [ "Deployed systems / applications", "部署系统／应用" ], [ "C02", "C02" ] ], "sources": [ "C02" ] }, { "id": "c4", "values": [ [ "Journal of Software", "Journal of Software" ], [ "2021", "2021" ], [ "CPU-side High Performance BLAS Library Optimization in Heterogeneous HPL Algorithm", "CPU-side High Performance BLAS Library Optimization in Heterogeneous HPL Algorithm" ], [ "Cai Y. et al.", "Cai Y. et al." ], [ "Dhyana", "Dhyana" ], [ "Related research; tested CPU topology", "相关研究；测试 CPU 拓扑" ], [ "R02", "R02" ] ], "sources": [ "R02" ] }, { "id": "c5", "values": [ [ "CCF Trans. HPC", "CCF Trans. HPC" ], [ "2024", "2024" ], [ "Optimizing depthwise separable convolution on DCU", "Optimizing depthwise separable convolution on DCU" ], [ "Liu Z. et al.", "Liu Z. et al." ], [ "64-CU test device", "64-CU 测试设备" ], [ "Related research; kernels / architecture", "相关研究；算子／架构" ], [ "R01", "R01" ] ], "sources": [ "R01" ] }, { "id": "c6", "values": [ [ "CCF Trans. HPC", "CCF Trans. HPC" ], [ "2025 / 2026", "2025 / 2026" ], [ "Optimizing Standard Convolution for Diverse Precision on DCU", "Optimizing Standard Convolution for Diverse Precision on DCU" ], [ "Hua H. et al.", "Hua H. et al." ], [ "DCU", "DCU" ], [ "Related research; abstract read only", "相关研究；仅审阅摘要" ], [ "R03", "R03" ] ], "sources": [ "R03" ] } ], "panels": [ [ 0, 1, 2, 3 ], [ 0, 4, 5, 6 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "crosswalk": { "id": "crosswalk", "title": [ "Product and technology crosswalk", "产品与技术名称对照" ], "headers": [ [ "Name", "名称" ], [ "Meaning", "含义" ], [ "Mapped identity", "对应身份" ], [ "Boundary", "边界" ] ], "rows": [ { "id": "x1", "values": [ [ "Dhyana", "Dhyana" ], [ "Initial CPU identity", "初代 CPU 标识" ], [ "Hygon Family 18h", "Hygon Family 18h" ], [ "Do not reuse as a later Zen-generation mapping", "不用于推定后续 Zen 代际" ] ], "sources": [ "P05", "R02" ] }, { "id": "x2", "values": [ [ "7100 / 5100 / 3100", "7100 / 5100 / 3100" ], [ "Generation 1 tiers", "第一代档次" ], [ "No. 1 CPU", "海光一号 CPU" ], [ "Server / smaller server / workstation tiers", "高端服务器／较小服务器／工作站档次" ] ], "sources": [ "E03" ] }, { "id": "x3", "values": [ [ "7200 / 5200 / 3200", "7200 / 5200 / 3200" ], [ "Generation 2 tiers", "第二代档次" ], [ "No. 2 CPU", "海光二号 CPU" ], [ "Tier is not a generation", "档次不等于代际" ] ], "sources": [ "E03" ] }, { "id": "x4", "values": [ [ "C86-4G", "C86-4G" ], [ "Fourth-generation host platform", "第四代主机平台" ], [ "No. 4 CPU; 64-core/socket OEM reference", "海光四号 CPU；整机参考每颗 64 核" ], [ "128 cores means two sockets in P04", "P04 的 128 核是双路口径" ] ], "sources": [ "P04" ] }, { "id": "x5", "values": [ [ "Deep Computing No. 1/2/3", "深算一号／二号／三号" ], [ "DCU silicon generations", "DCU 芯片代际" ], [ "Commercial milestones 2021/2023/2025", "商业里程碑 2021／2023／2025" ], [ "Not CPU family numbering", "不是 CPU 系列编号" ] ], "sources": [ "E03", "E11", "E05" ] }, { "id": "x6", "values": [ [ "Z100 / K100 / K100-AI", "Z100 / K100 / K100-AI" ], [ "Software and board identities", "软件及板卡身份" ], [ "Actual validation / deployment names", "实际验证／部署名称" ], [ "Full silicon-generation crosswalk n/d", "完整芯片代际映射 n/d" ] ], "sources": [ "E02", "P03", "C02" ] }, { "id": "x7", "values": [ [ "XCD / MID / HIG", "XCD / MID / HIG" ], [ "Chiplet and partitioning terminology", "芯粒与资源划分术语" ], [ "Disclosed development capabilities", "已披露研发能力" ], [ "Commercial SKU mapping n/d", "商业 SKU 映射 n/d" ] ], "sources": [ "E01" ] }, { "id": "x8", "values": [ [ "HSL / DTK", "HSL / DTK" ], [ "System Link / software toolkit", "系统互联／软件工具包" ], [ "Platform integration / enablement", "平台集成／软件支持" ], [ "Not independent DPU or AI NIC products", "不是独立 DPU 或 AI 网卡产品" ] ], "sources": [ "E05", "E04" ] } ], "panels": [ [ 0, 1, 2, 3 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" } }, "figures": { "era1": { "id": "era1", "title": [ "Era 1: enterprise host and early DCU, 2018–2022", "阶段一：企业主机与早期 DCU，2018–2022" ], "nodes": [ [ "cpu", [ "C86 CPU\nCCX / NUMA", "C86 CPU\nCCX／NUMA" ], 0, 0 ], [ "dram", [ "Host DDR4\nLocality-sensitive", "主机 DDR4\n重视局部性" ], 1, 0 ], [ "gpu", [ "No. 1 DCU / Z100 ecosystem", "深算一号／Z100 生态" ], 0, 1 ], [ "hbm", [ "DCU-local memory", "DCU 本地内存" ], 1, 1 ], [ "sw", [ "HIP / ROCm\nPaddle enablement", "HIP／ROCm\n飞桨支持" ], 0, 2 ], [ "nic", [ "Partner NIC / storage\nServer integration", "伙伴网卡／存储\n服务器集成" ], 1, 2 ] ], "edges": [ [ "cpu", "dram", [ "Memory", "内存" ] ], [ "cpu", "gpu", [ "PCIe", "PCIe" ] ], [ "gpu", "hbm", [ "Local", "本地" ] ], [ "gpu", "sw", [ "Runtime", "运行时" ] ], [ "sw", "nic", [ "System services", "系统服务" ] ] ], "caption": [ "No. 1 silicon specifications and Z100 software support are separate evidence anchors; the figure does not force a universal SKU mapping.", "深算一号芯片规格与 Z100 软件支持是两类证据，图中不强制建立通用 SKU 对应关系。" ] }, "era2": { "id": "era2", "title": [ "Era 2: operational multi-card systems, 2023–2025", "阶段二：实际多卡系统，2023–2025" ], "nodes": [ [ "cpu", [ "C86 server host", "C86 服务器主机" ], 0, 0 ], [ "dram", [ "Host memory / storage", "主机内存／存储" ], 1, 0 ], [ "gpus", [ "8 × K100-AI per node\nIHEP reference", "每节点 8 张 K100-AI\n高能所参考" ], 0, 1 ], [ "mem", [ "64 GB per card\n512 GB total, derived", "每卡 64 GB\n总计推算 512 GB" ], 1, 1 ], [ "sw", [ "Frameworks / HIP / kernels", "框架／HIP／算子" ], 0, 2 ], [ "net", [ "6 nodes in installation\nFabric details n/d", "部署共 6 节点\n网络细节 n/d" ], 1, 2 ] ], "edges": [ [ "cpu", "dram", [ "Host", "主机" ] ], [ "cpu", "gpus", [ "PCIe", "PCIe" ] ], [ "gpus", "mem", [ "Local memory", "本地内存" ] ], [ "gpus", "sw", [ "Execution", "执行" ] ], [ "sw", "net", [ "Distributed runtime", "分布式运行时" ] ] ], "caption": [ "Aggregate card capacity is not a unified physical-memory guarantee. Eight cards per node and six nodes are deployment counts, not maximum link-domain sizes.", "板卡容量相加不代表统一物理内存。每节点八卡及六节点是部署数量，不是链路域最大规模。" ] }, "era3": { "id": "era3", "title": [ "Era 3: CPU–DCU platform direction, 2025–2026", "阶段三：CPU–DCU 平台方向，2025–2026" ], "nodes": [ [ "cpu", [ "C86-4G host platform\nDDR5 / PCIe 5.0", "C86-4G 主机平台\nDDR5／PCIe 5.0" ], 0, 0 ], [ "xpu", [ "Partner xPUs\nHSL ecosystem", "伙伴 xPU\nHSL 生态" ], 1, 0 ], [ "gpus", [ "Commercial DCU generations\nNo. 3 shipping", "商业 DCU 代际\n深算三号已商用" ], 0, 1 ], [ "ip", [ "XCD / MID / HIG\nR&D-to-SKU map n/d", "XCD／MID／HIG\n研发至 SKU 映射 n/d" ], 1, 1 ], [ "sw", [ "DTK / application tools\nSecurity integration", "DTK／应用工具\n安全集成" ], 0, 2 ], [ "net", [ "Partner fabric / storage\nNo verified owned DPU line", "伙伴网络／存储\n未核实自有 DPU 系列" ], 1, 2 ] ], "edges": [ [ "cpu", "xpu", [ "HSL direction", "HSL 方向" ] ], [ "cpu", "gpus", [ "System integration", "系统集成" ] ], [ "gpus", "ip", [ "Development themes", "研发方向" ] ], [ "gpus", "sw", [ "Enablement", "软件支持" ] ], [ "sw", "net", [ "System software", "系统软件" ] ] ], "caption": [ "The diagram separates shipping host/DCU products from implementation capabilities and partner fabric. It does not claim a particular HSL link on an identified DCU SKU.", "图中区分已商用主机／DCU、实现能力及伙伴网络，不声称某个具名 DCU SKU 已采用特定 HSL 链路。" ] } }, "claims": { "headline.a1.0": { "value": "2018–2020 baseline", "field": "Anchor", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R02" ], "disclosure_date": "2021", "status": "historical", "scope": "a1" }, "headline.a1.1": { "value": "Dhyana: 32 cores; 4 dies", "field": "CPU / host", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R02" ], "disclosure_date": "2021", "status": "historical", "scope": "a1" }, "headline.a1.2": { "value": "Early heterogeneous research systems", "field": "Accelerator / memory", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R02" ], "disclosure_date": "2021", "status": "historical", "scope": "a1" }, "headline.a1.3": { "value": "PCIe; NUMA-aware placement", "field": "Integration", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R02" ], "disclosure_date": "2021", "status": "historical", "scope": "a1" }, "headline.a2.0": { "value": "2021–2022", "field": "Anchor", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "shipping", "scope": "a2" }, "headline.a2.1": { "value": "7200: 170.624 GB/s derived DDR peak", "field": "CPU / host", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "shipping", "scope": "a2" }, "headline.a2.2": { "value": "No. 1: 32 GB HBM2; 1.024 TB/s", "field": "Accelerator / memory", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "shipping", "scope": "a2" }, "headline.a2.3": { "value": "PCIe 4.0 x16 on DCU; host may limit rate", "field": "Integration", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "shipping", "scope": "a2" }, "headline.a3.0": { "value": "2024–2025 deployment", "field": "Anchor", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C02" ], "disclosure_date": "2025-08-25", "status": "shipping", "scope": "a3" }, "headline.a3.1": { "value": "Generation 3; DDR4 host ecosystem", "field": "CPU / host", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C02" ], "disclosure_date": "2025-08-25", "status": "shipping", "scope": "a3" }, "headline.a3.2": { "value": "IHEP: 6 nodes × 8 K100-AI; 64 GB/card", "field": "Accelerator / memory", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C02" ], "disclosure_date": "2025-08-25", "status": "shipping", "scope": "a3" }, "headline.a3.3": { "value": "Actual eight-card servers; link-domain limit n/d", "field": "Integration", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C02" ], "disclosure_date": "2025-08-25", "status": "shipping", "scope": "a3" }, "headline.a4.0": { "value": "2025–2026 platform", "field": "Anchor", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "E05", "E01" ], "disclosure_date": "2026-08-14", "status": "mixed", "scope": "a4" }, "headline.a4.1": { "value": "C86-4G: 64 cores/socket; DDR5-5600 platform", "field": "CPU / host", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "E05", "E01" ], "disclosure_date": "2026-08-14", "status": "mixed", "scope": "a4" }, "headline.a4.2": { "value": "No. 3 commercial; dense BF16/FP8 n/d", "field": "Accelerator / memory", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "E05", "E01" ], "disclosure_date": "2026-08-14", "status": "mixed", "scope": "a4" }, "headline.a4.3": { "value": "HSL 1.0; DTK; CPU–DCU security work", "field": "Integration", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "E05", "E01" ], "disclosure_date": "2026-08-14", "status": "mixed", "scope": "a4" }, "cpu.g1.0": { "value": "No. 1 / 7100", "field": "Generation / reference SKU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "R02", "P05" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g1" }, "cpu.g1.1": { "value": "Dhyana", "field": "Codename", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "R02", "P05" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g1" }, "cpu.g1.2": { "value": "2018-04 production", "field": "GA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "R02", "P05" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g1" }, "cpu.g1.3": { "value": "Historical shipping", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "R02", "P05" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g1" }, "cpu.g1.4": { "value": "Licensed origin; Hygon Family 18h", "field": "Core µarch", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "R02", "P05" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g1" }, "cpu.g1.5": { "value": "32 / 64", "field": "Cores / threads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "R02", "P05" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g1" }, "cpu.g1.6": { "value": "14 nm", "field": "Process per die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "R02", "P05" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g1" }, "cpu.g1.7": { "value": "4 dies; 2 CCX/die", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "R02", "P05" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g1" }, "cpu.g1.8": { "value": "512 KB", "field": "L2 per core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "R02", "P05" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g1" }, "cpu.g1.9": { "value": "64 MB; 8 MB / 4 cores", "field": "L3 / domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "R02", "P05" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g1" }, "cpu.g1.10": { "value": "n/d", "field": "Memory: channels; rate; GB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "R02", "P05" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g1" }, "cpu.g1.11": { "value": "Multi-socket; link rate n/d", "field": "Sockets / links", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "R02", "P05" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g1" }, "cpu.g1.12": { "value": "n/d", "field": "PCIe / CXL", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "R02", "P05" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g1" }, "cpu.g1.13": { "value": "n/d", "field": "TDP", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "R02", "P05" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g1" }, "cpu.g1.14": { "value": "AVX / AVX2", "field": "Vector / matrix ISA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "R02", "P05" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g1" }, "cpu.g2.0": { "value": "No. 2 / 7200", "field": "Generation / reference SKU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g2" }, "cpu.g2.1": { "value": "n/d", "field": "Codename", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g2" }, "cpu.g2.2": { "value": "2020-01 production", "field": "GA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g2" }, "cpu.g2.3": { "value": "Historical shipping", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g2" }, "cpu.g2.4": { "value": "Hygon C86; details n/d", "field": "Core µarch", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g2" }, "cpu.g2.5": { "value": "32 / 64", "field": "Cores / threads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g2" }, "cpu.g2.6": { "value": "n/d", "field": "Process per die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g2" }, "cpu.g2.7": { "value": "n/d", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g2" }, "cpu.g2.8": { "value": "512 KB", "field": "L2 per core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g2" }, "cpu.g2.9": { "value": "32 / 64 MB; domain n/d", "field": "L3 / domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g2" }, "cpu.g2.10": { "value": "DDR4; 8; 2666 MT/s; 170.624 GB/s", "field": "Memory: channels; rate; GB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g2" }, "cpu.g2.11": { "value": "2P observed; links n/d", "field": "Sockets / links", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g2" }, "cpu.g2.12": { "value": "128 PCIe 3.0 lanes, shared uses; CXL n/d", "field": "PCIe / CXL", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g2" }, "cpu.g2.13": { "value": "225 W typical upper value", "field": "TDP", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g2" }, "cpu.g2.14": { "value": "n/d", "field": "Vector / matrix ISA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "g2" }, "cpu.g3.0": { "value": "No. 3 / 7300 platform", "field": "Generation / reference SKU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07", "P07", "C03" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g3" }, "cpu.g3.1": { "value": "n/d", "field": "Codename", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07", "P07", "C03" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g3" }, "cpu.g3.2": { "value": "2022 small-volume sales", "field": "GA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07", "P07", "C03" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g3" }, "cpu.g3.3": { "value": "Shipping / available", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07", "P07", "C03" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g3" }, "cpu.g3.4": { "value": "Hygon C86; details n/d", "field": "Core µarch", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07", "P07", "C03" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g3" }, "cpu.g3.5": { "value": "32 cores; threads n/d in OEM brief", "field": "Cores / threads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07", "P07", "C03" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g3" }, "cpu.g3.6": { "value": "n/d", "field": "Process per die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07", "P07", "C03" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g3" }, "cpu.g3.7": { "value": "n/d", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07", "P07", "C03" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g3" }, "cpu.g3.8": { "value": "n/d", "field": "L2 per core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07", "P07", "C03" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g3" }, "cpu.g3.9": { "value": "n/d", "field": "L3 / domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07", "P07", "C03" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g3" }, "cpu.g3.10": { "value": "DDR4; channels n/d; up to 3200 MT/s; GB/s n/d", "field": "Memory: channels; rate; GB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07", "P07", "C03" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g3" }, "cpu.g3.11": { "value": "2P platform; links n/d", "field": "Sockets / links", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07", "P07", "C03" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g3" }, "cpu.g3.12": { "value": "PCIe 4.0/3.0 platform; CXL n/d", "field": "PCIe / CXL", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07", "P07", "C03" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g3" }, "cpu.g3.13": { "value": "n/d", "field": "TDP", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07", "P07", "C03" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g3" }, "cpu.g3.14": { "value": "n/d", "field": "Vector / matrix ISA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07", "P07", "C03" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g3" }, "cpu.g4.0": { "value": "No. 4 / C86-4G", "field": "Generation / reference SKU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g4" }, "cpu.g4.1": { "value": "n/d", "field": "Codename", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g4" }, "cpu.g4.2": { "value": "Available by cutoff; exact GA n/d", "field": "GA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g4" }, "cpu.g4.3": { "value": "Shipping / available", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g4" }, "cpu.g4.4": { "value": "Hygon C86; details n/d", "field": "Core µarch", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g4" }, "cpu.g4.5": { "value": "64 cores; SMT; max threads n/d", "field": "Cores / threads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g4" }, "cpu.g4.6": { "value": "n/d", "field": "Process per die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g4" }, "cpu.g4.7": { "value": "n/d", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g4" }, "cpu.g4.8": { "value": "n/d", "field": "L2 per core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g4" }, "cpu.g4.9": { "value": "n/d", "field": "L3 / domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g4" }, "cpu.g4.10": { "value": "DDR5; channels n/d; up to 5600 MT/s; GB/s n/d", "field": "Memory: channels; rate; GB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g4" }, "cpu.g4.11": { "value": "2P; links n/d", "field": "Sockets / links", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g4" }, "cpu.g4.12": { "value": "PCIe 5.0 platform; CXL SKU mapping n/d", "field": "PCIe / CXL", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g4" }, "cpu.g4.13": { "value": "400 W processor maximum", "field": "TDP", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g4" }, "cpu.g4.14": { "value": "n/d", "field": "Vector / matrix ISA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "g4" }, "cpu.g5.0": { "value": "No. 5", "field": "Generation / reference SKU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07" ], "disclosure_date": "2023-04-18", "status": "roadmap; no verified GA", "scope": "g5" }, "cpu.g5.1": { "value": "n/d", "field": "Codename", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07" ], "disclosure_date": "2023-04-18", "status": "roadmap; no verified GA", "scope": "g5" }, "cpu.g5.2": { "value": "n/d", "field": "GA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07" ], "disclosure_date": "2023-04-18", "status": "roadmap; no verified GA", "scope": "g5" }, "cpu.g5.3": { "value": "Roadmap", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07" ], "disclosure_date": "2023-04-18", "status": "roadmap; no verified GA", "scope": "g5" }, "cpu.g5.4": { "value": "n/d", "field": "Core µarch", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07" ], "disclosure_date": "2023-04-18", "status": "roadmap; no verified GA", "scope": "g5" }, "cpu.g5.5": { "value": "n/d", "field": "Cores / threads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07" ], "disclosure_date": "2023-04-18", "status": "roadmap; no verified GA", "scope": "g5" }, "cpu.g5.6": { "value": "n/d", "field": "Process per die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07" ], "disclosure_date": "2023-04-18", "status": "roadmap; no verified GA", "scope": "g5" }, "cpu.g5.7": { "value": "n/d", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07" ], "disclosure_date": "2023-04-18", "status": "roadmap; no verified GA", "scope": "g5" }, "cpu.g5.8": { "value": "n/d", "field": "L2 per core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07" ], "disclosure_date": "2023-04-18", "status": "roadmap; no verified GA", "scope": "g5" }, "cpu.g5.9": { "value": "n/d", "field": "L3 / domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07" ], "disclosure_date": "2023-04-18", "status": "roadmap; no verified GA", "scope": "g5" }, "cpu.g5.10": { "value": "n/d", "field": "Memory: channels; rate; GB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07" ], "disclosure_date": "2023-04-18", "status": "roadmap; no verified GA", "scope": "g5" }, "cpu.g5.11": { "value": "n/d", "field": "Sockets / links", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07" ], "disclosure_date": "2023-04-18", "status": "roadmap; no verified GA", "scope": "g5" }, "cpu.g5.12": { "value": "n/d", "field": "PCIe / CXL", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07" ], "disclosure_date": "2023-04-18", "status": "roadmap; no verified GA", "scope": "g5" }, "cpu.g5.13": { "value": "n/d", "field": "TDP", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07" ], "disclosure_date": "2023-04-18", "status": "roadmap; no verified GA", "scope": "g5" }, "cpu.g5.14": { "value": "n/d", "field": "Vector / matrix ISA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E07" ], "disclosure_date": "2023-04-18", "status": "roadmap; no verified GA", "scope": "g5" }, "accelerator.d1.0": { "value": "Deep Computing No. 1", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "d1" }, "accelerator.d1.1": { "value": "GPGPU; commercial codename n/d", "field": "Architecture", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "d1" }, "accelerator.d1.2": { "value": "2021 commercial", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "d1" }, "accelerator.d1.3": { "value": "Historical shipping", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "d1" }, "accelerator.d1.4": { "value": "7 nm FinFET", "field": "Process", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "d1" }, "accelerator.d1.5": { "value": "Die count n/d; HBM package", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "d1" }, "accelerator.d1.6": { "value": "64 CUs / 4096", "field": "Compute units", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "d1" }, "accelerator.d1.7": { "value": "n/d", "field": "Dense BF16", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "d1" }, "accelerator.d1.8": { "value": "n/d", "field": "Dense FP8", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "d1" }, "accelerator.d1.9": { "value": "n/d", "field": "Dense FP6 / FP4", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "d1" }, "accelerator.d1.10": { "value": "n/d", "field": "FP64 vector / matrix", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "d1" }, "accelerator.d1.11": { "value": "HBM2; stacks n/d; 32 GB; 1.024 TB/s", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "d1" }, "accelerator.d1.12": { "value": "n/d", "field": "LLC / SRAM", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "d1" }, "accelerator.d1.13": { "value": "2 xGMI; 184 GB/s quoted, direction n/d; domain n/d", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "d1" }, "accelerator.d1.14": { "value": "PCIe 4.0 x16", "field": "Host link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "d1" }, "accelerator.d1.15": { "value": "350 W TDP; cooling n/d", "field": "Power / cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "d1" }, "accelerator.d1.16": { "value": "n/d", "field": "Form factor", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "d1" }, "accelerator.d2.0": { "value": "Deep Computing No. 2", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E11" ], "disclosure_date": "2023-11-22", "status": "shipping", "scope": "d2" }, "accelerator.d2.1": { "value": "GPGPU", "field": "Architecture", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E11" ], "disclosure_date": "2023-11-22", "status": "shipping", "scope": "d2" }, "accelerator.d2.2": { "value": "By 2023-11 commercial", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E11" ], "disclosure_date": "2023-11-22", "status": "shipping", "scope": "d2" }, "accelerator.d2.3": { "value": "Shipping / available", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E11" ], "disclosure_date": "2023-11-22", "status": "shipping", "scope": "d2" }, "accelerator.d2.4": { "value": "n/d", "field": "Process", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E11" ], "disclosure_date": "2023-11-22", "status": "shipping", "scope": "d2" }, "accelerator.d2.5": { "value": "n/d", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E11" ], "disclosure_date": "2023-11-22", "status": "shipping", "scope": "d2" }, "accelerator.d2.6": { "value": "n/d", "field": "Compute units", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E11" ], "disclosure_date": "2023-11-22", "status": "shipping", "scope": "d2" }, "accelerator.d2.7": { "value": "n/d", "field": "Dense BF16", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E11" ], "disclosure_date": "2023-11-22", "status": "shipping", "scope": "d2" }, "accelerator.d2.8": { "value": "n/d", "field": "Dense FP8", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E11" ], "disclosure_date": "2023-11-22", "status": "shipping", "scope": "d2" }, "accelerator.d2.9": { "value": "n/d", "field": "Dense FP6 / FP4", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E11" ], "disclosure_date": "2023-11-22", "status": "shipping", "scope": "d2" }, "accelerator.d2.10": { "value": "n/d", "field": "FP64 vector / matrix", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E11" ], "disclosure_date": "2023-11-22", "status": "shipping", "scope": "d2" }, "accelerator.d2.11": { "value": "n/d", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E11" ], "disclosure_date": "2023-11-22", "status": "shipping", "scope": "d2" }, "accelerator.d2.12": { "value": "n/d", "field": "LLC / SRAM", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E11" ], "disclosure_date": "2023-11-22", "status": "shipping", "scope": "d2" }, "accelerator.d2.13": { "value": "n/d", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E11" ], "disclosure_date": "2023-11-22", "status": "shipping", "scope": "d2" }, "accelerator.d2.14": { "value": "n/d", "field": "Host link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E11" ], "disclosure_date": "2023-11-22", "status": "shipping", "scope": "d2" }, "accelerator.d2.15": { "value": "n/d", "field": "Power / cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E11" ], "disclosure_date": "2023-11-22", "status": "shipping", "scope": "d2" }, "accelerator.d2.16": { "value": "n/d", "field": "Form factor", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E11" ], "disclosure_date": "2023-11-22", "status": "shipping", "scope": "d2" }, "accelerator.d3.0": { "value": "Deep Computing No. 3", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E05" ], "disclosure_date": "2026-04-08", "status": "shipping", "scope": "d3" }, "accelerator.d3.1": { "value": "GPGPU", "field": "Architecture", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E05" ], "disclosure_date": "2026-04-08", "status": "shipping", "scope": "d3" }, "accelerator.d3.2": { "value": "2025 commercial", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E05" ], "disclosure_date": "2026-04-08", "status": "shipping", "scope": "d3" }, "accelerator.d3.3": { "value": "Shipping / available", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E05" ], "disclosure_date": "2026-04-08", "status": "shipping", "scope": "d3" }, "accelerator.d3.4": { "value": "n/d", "field": "Process", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E05" ], "disclosure_date": "2026-04-08", "status": "shipping", "scope": "d3" }, "accelerator.d3.5": { "value": "n/d", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E05" ], "disclosure_date": "2026-04-08", "status": "shipping", "scope": "d3" }, "accelerator.d3.6": { "value": "n/d", "field": "Compute units", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E05" ], "disclosure_date": "2026-04-08", "status": "shipping", "scope": "d3" }, "accelerator.d3.7": { "value": "n/d", "field": "Dense BF16", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E05" ], "disclosure_date": "2026-04-08", "status": "shipping", "scope": "d3" }, "accelerator.d3.8": { "value": "n/d", "field": "Dense FP8", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E05" ], "disclosure_date": "2026-04-08", "status": "shipping", "scope": "d3" }, "accelerator.d3.9": { "value": "n/d", "field": "Dense FP6 / FP4", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E05" ], "disclosure_date": "2026-04-08", "status": "shipping", "scope": "d3" }, "accelerator.d3.10": { "value": "n/d", "field": "FP64 vector / matrix", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E05" ], "disclosure_date": "2026-04-08", "status": "shipping", "scope": "d3" }, "accelerator.d3.11": { "value": "n/d", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E05" ], "disclosure_date": "2026-04-08", "status": "shipping", "scope": "d3" }, "accelerator.d3.12": { "value": "n/d", "field": "LLC / SRAM", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E05" ], "disclosure_date": "2026-04-08", "status": "shipping", "scope": "d3" }, "accelerator.d3.13": { "value": "n/d", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E05" ], "disclosure_date": "2026-04-08", "status": "shipping", "scope": "d3" }, "accelerator.d3.14": { "value": "n/d", "field": "Host link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E05" ], "disclosure_date": "2026-04-08", "status": "shipping", "scope": "d3" }, "accelerator.d3.15": { "value": "n/d", "field": "Power / cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E05" ], "disclosure_date": "2026-04-08", "status": "shipping", "scope": "d3" }, "accelerator.d3.16": { "value": "n/d", "field": "Form factor", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E05" ], "disclosure_date": "2026-04-08", "status": "shipping", "scope": "d3" }, "accelerator.k100ai.0": { "value": "K100-AI deployment reference", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2025-08-25", "status": "deployed reference", "scope": "k100ai" }, "accelerator.k100ai.1": { "value": "Generation crosswalk n/d", "field": "Architecture", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2025-08-25", "status": "deployed reference", "scope": "k100ai" }, "accelerator.k100ai.2": { "value": "2024–2025 deployed", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2025-08-25", "status": "deployed reference", "scope": "k100ai" }, "accelerator.k100ai.3": { "value": "Shipping / available", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2025-08-25", "status": "deployed reference", "scope": "k100ai" }, "accelerator.k100ai.4": { "value": "n/d", "field": "Process", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2025-08-25", "status": "deployed reference", "scope": "k100ai" }, "accelerator.k100ai.5": { "value": "n/d", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2025-08-25", "status": "deployed reference", "scope": "k100ai" }, "accelerator.k100ai.6": { "value": "n/d", "field": "Compute units", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2025-08-25", "status": "deployed reference", "scope": "k100ai" }, "accelerator.k100ai.7": { "value": "n/d", "field": "Dense BF16", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2025-08-25", "status": "deployed reference", "scope": "k100ai" }, "accelerator.k100ai.8": { "value": "n/d", "field": "Dense FP8", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2025-08-25", "status": "deployed reference", "scope": "k100ai" }, "accelerator.k100ai.9": { "value": "n/d", "field": "Dense FP6 / FP4", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2025-08-25", "status": "deployed reference", "scope": "k100ai" }, "accelerator.k100ai.10": { "value": "n/d", "field": "FP64 vector / matrix", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2025-08-25", "status": "deployed reference", "scope": "k100ai" }, "accelerator.k100ai.11": { "value": "64 GB; type, stacks, bandwidth n/d", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2025-08-25", "status": "deployed reference", "scope": "k100ai" }, "accelerator.k100ai.12": { "value": "n/d", "field": "LLC / SRAM", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2025-08-25", "status": "deployed reference", "scope": "k100ai" }, "accelerator.k100ai.13": { "value": "8-card servers observed; link/domain maximum n/d", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2025-08-25", "status": "deployed reference", "scope": "k100ai" }, "accelerator.k100ai.14": { "value": "PCIe", "field": "Host link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2025-08-25", "status": "deployed reference", "scope": "k100ai" }, "accelerator.k100ai.15": { "value": "400 W in P08 configuration; cooling n/d", "field": "Power / cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2025-08-25", "status": "deployed reference", "scope": "k100ai" }, "accelerator.k100ai.16": { "value": "PCIe card", "field": "Form factor", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2025-08-25", "status": "deployed reference", "scope": "k100ai" }, "interconnect.pcie.0": { "value": "PCIe host path", "field": "Interconnect", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "P07", "P04" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "pcie" }, "interconnect.pcie.1": { "value": "Gen3 → Gen4 → Gen5 platforms", "field": "Year / generation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "P07", "P04" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "pcie" }, "interconnect.pcie.2": { "value": "8 / 16 / 32 GT/s", "field": "Lane rate", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "P07", "P04" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "pcie" }, "interconnect.pcie.3": { "value": "x16 reference", "field": "Lanes / link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "P07", "P04" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "pcie" }, "interconnect.pcie.4": { "value": "15.754 / 31.508 / 63.015", "field": "GB/s per link per direction", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "P07", "P04" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "pcie" }, "interconnect.pcie.5": { "value": "Board dependent", "field": "Links / device", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "P07", "P04" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "pcie" }, "interconnect.pcie.6": { "value": "Root complex / switch", "field": "Topology", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "P07", "P04" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "pcie" }, "interconnect.pcie.7": { "value": "n/a", "field": "Domain limit", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "P07", "P04" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "pcie" }, "interconnect.pcie.8": { "value": "I/O transport; no assumed cache coherence", "field": "Coherence / semantics", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "P07", "P04" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "pcie" }, "interconnect.xgmi.0": { "value": "xGMI, No. 1", "field": "Interconnect", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "xgmi" }, "interconnect.xgmi.1": { "value": "2021", "field": "Year / generation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "xgmi" }, "interconnect.xgmi.2": { "value": "n/d", "field": "Lane rate", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "xgmi" }, "interconnect.xgmi.3": { "value": "n/d", "field": "Lanes / link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "xgmi" }, "interconnect.xgmi.4": { "value": "n/d", "field": "GB/s per link per direction", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "xgmi" }, "interconnect.xgmi.5": { "value": "2", "field": "Links / device", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "xgmi" }, "interconnect.xgmi.6": { "value": "n/d", "field": "Topology", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "xgmi" }, "interconnect.xgmi.7": { "value": "n/d", "field": "Domain limit", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "historical shipping", "scope": "xgmi" }, "interconnect.xgmi.8": { "value": "Peer-link semantics n/d", "field": "Coherence / semantics", "basis": "Per reference product; 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bandwidth n/d", "field": "Memory", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2025-08-25", "status": "deployed", "scope": "b2" }, "bandwidth.b2.3": { "value": "PCIe; negotiated rate n/d", "field": "CPU–DCU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2025-08-25", "status": "deployed", "scope": "b2" }, "bandwidth.b2.4": { "value": "n/d", "field": "Scale-up / accelerator", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2025-08-25", "status": "deployed", "scope": "b2" }, "bandwidth.b2.5": { "value": "n/d", "field": "Scale-out / accelerator", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2025-08-25", "status": "deployed", "scope": "b2" }, "bandwidth.b3.0": { "value": "C86-4G / HSL era", "field": "Era / reference", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "E05" ], "disclosure_date": "2026-09-28", "status": "mixed", "scope": "b3" }, "bandwidth.b3.1": { "value": "n/d", "field": "On-die / die-to-die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "E05" ], "disclosure_date": "2026-09-28", "status": "mixed", "scope": "b3" }, "bandwidth.b3.2": { "value": "DDR5-5600 platform; channel map n/d", "field": "Memory", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "E05" ], "disclosure_date": "2026-09-28", "status": "mixed", "scope": "b3" }, "bandwidth.b3.3": { "value": "Gen5 x16 ceiling 63.015 GB/s/direction; HSL n/d", "field": "CPU–DCU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "E05" ], "disclosure_date": "2026-09-28", "status": "mixed", "scope": "b3" }, "bandwidth.b3.4": { "value": "n/d", "field": "Scale-up / accelerator", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "E05" ], "disclosure_date": "2026-09-28", "status": "mixed", "scope": "b3" }, "bandwidth.b3.5": { "value": "n/d", "field": "Scale-out / accelerator", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "E05" ], "disclosure_date": "2026-09-28", "status": "mixed", "scope": "b3" }, "ratios.r1.0": { "value": "7200 DDR bandwidth/core", "field": "Metric", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "derived", "scope": "r1" }, "ratios.r1.1": { "value": "8 × 2666 × 10^6 × 8 / 32", "field": "Calculation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "derived", "scope": "r1" }, "ratios.r1.2": { "value": "5.332 GB/s/core", "field": "Result", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "derived", "scope": "r1" }, "ratios.r1.3": { "value": "Derived; 32-core SKU at peak rate", "field": "Scope / limit", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "derived", "scope": "r1" }, "ratios.r2.0": { "value": "7200 L3/core, 64 MB SKU", "field": "Metric", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "derived", "scope": "r2" }, "ratios.r2.1": { "value": "64 / 32", "field": "Calculation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "derived", "scope": "r2" }, "ratios.r2.2": { "value": "2 MB/core", "field": "Result", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "derived", "scope": "r2" }, "ratios.r2.3": { "value": "Arithmetic average; not private cache", "field": "Scope / limit", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "derived", "scope": "r2" }, "ratios.r3.0": { "value": "No. 1 HBM / Gen4 x16", "field": "Metric", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "derived", "scope": "r3" }, "ratios.r3.1": { "value": "1024 / 31.508", "field": "Calculation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "derived", "scope": "r3" }, "ratios.r3.2": { "value": "32.50×", "field": "Result", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "derived", "scope": "r3" }, "ratios.r3.3": { "value": "Memory bandwidth vs one-way link ceiling", "field": "Scope / limit", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "derived", "scope": "r3" }, "ratios.r4.0": { "value": "8-card capacity", "field": "Metric", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2025-08-25", "status": "derived", "scope": "r4" }, "ratios.r4.1": { "value": "8 × 64 GB", "field": "Calculation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2025-08-25", "status": "derived", "scope": "r4" }, "ratios.r4.2": { "value": "512 GB", "field": "Result", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2025-08-25", "status": "derived", "scope": "r4" }, "ratios.r4.3": { "value": "K100-AI node aggregate; not unified memory", "field": "Scope / limit", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2025-08-25", "status": "derived", "scope": "r4" }, "ratios.r5.0": { "value": "HBM bytes / dense BF16 or FP8 FLOP", "field": "Metric", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "E05", "C02" ], "disclosure_date": "2026-09-28", "status": "not disclosed", "scope": "r5" }, "ratios.r5.1": { "value": "n/d", "field": "Calculation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "E05", "C02" ], "disclosure_date": "2026-09-28", "status": "not disclosed", "scope": "r5" }, "ratios.r5.2": { "value": "n/d", "field": "Result", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "E05", "C02" ], "disclosure_date": "2026-09-28", "status": "not disclosed", "scope": "r5" }, "ratios.r5.3": { "value": "No matched format/throughput denominator", "field": "Scope / limit", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "E05", "C02" ], "disclosure_date": "2026-09-28", "status": "not disclosed", "scope": "r5" }, "ratios.r6.0": { "value": "Scale-up/HBM; scale-out/card; FLOP/W", "field": "Metric", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "C02", "P08" ], "disclosure_date": "2026-09-28", "status": "not disclosed", "scope": "r6" }, "ratios.r6.1": { "value": "n/d", "field": "Calculation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "C02", "P08" ], "disclosure_date": "2026-09-28", "status": "not disclosed", "scope": "r6" }, "ratios.r6.2": { "value": "n/d", "field": "Result", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "C02", "P08" ], "disclosure_date": "2026-09-28", "status": "not disclosed", "scope": "r6" }, "ratios.r6.3": { "value": "Direction, NIC mapping or compute/power pair missing", "field": "Scope / limit", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "C02", "P08" ], "disclosure_date": "2026-09-28", "status": "not disclosed", "scope": "r6" }, "conference.c1.0": { "value": "Hygon spring launch", "field": "Venue", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2022-06-07", "status": "indexed primary announcement", "scope": "c1" }, "conference.c1.1": { "value": "2022", "field": "Year", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2022-06-07", "status": "indexed primary announcement", "scope": "c1" }, "conference.c1.2": { "value": "CPU No. 3 and heterogeneous platform launch", "field": "Paper / talk / disclosure", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2022-06-07", "status": "indexed primary announcement", "scope": "c1" }, "conference.c1.3": { "value": "Hygon; named speaker n/d", "field": "Presenter / authors", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2022-06-07", "status": "indexed primary announcement", "scope": "c1" }, "conference.c1.4": { "value": "No. 3 CPU + DCU", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2022-06-07", "status": "indexed primary announcement", "scope": "c1" }, "conference.c1.5": { "value": "Company product event", "field": "Evidence type", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2022-06-07", "status": "indexed primary announcement", "scope": "c1" }, "conference.c1.6": { "value": "C03", "field": "Source", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2022-06-07", "status": "indexed primary announcement", "scope": "c1" }, "conference.c2.0": { "value": "HAIC", "field": "Venue", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E05" ], "disclosure_date": "2025-12", "status": "announced", "scope": "c2" }, "conference.c2.1": { "value": "2025", "field": "Year", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E05" ], "disclosure_date": "2025-12", "status": "announced", "scope": "c2" }, "conference.c2.2": { "value": "HSL 1.0 specification release", "field": "Paper / talk / disclosure", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E05" ], "disclosure_date": "2025-12", "status": "announced", "scope": "c2" }, "conference.c2.3": { "value": "Hygon and ecosystem partners", "field": "Presenter / authors", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E05" ], "disclosure_date": "2025-12", "status": "announced", "scope": "c2" }, "conference.c2.4": { "value": "HSL 1.0", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E05" ], "disclosure_date": "2025-12", "status": "announced", "scope": "c2" }, "conference.c2.5": { "value": "System / interconnect; issuer recap", "field": "Evidence type", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E05" ], "disclosure_date": "2025-12", "status": "announced", "scope": "c2" }, "conference.c2.6": { "value": "E05", "field": "Source", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E05" ], "disclosure_date": "2025-12", "status": "announced", "scope": "c2" }, "conference.c3.0": { "value": "IHEP technical presentation", "field": "Venue", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2025-08-25", "status": "deployed", "scope": "c3" }, "conference.c3.1": { "value": "2025", "field": "Year", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2025-08-25", "status": "deployed", "scope": "c3" }, "conference.c3.2": { "value": "AI@IHEPCC", "field": "Paper / talk / disclosure", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2025-08-25", "status": "deployed", "scope": "c3" }, "conference.c3.3": { "value": "IHEP computing team", "field": "Presenter / authors", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2025-08-25", "status": "deployed", "scope": "c3" }, "conference.c3.4": { "value": "K100 / K100-AI", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2025-08-25", "status": "deployed", "scope": "c3" }, "conference.c3.5": { "value": "Deployed systems / applications", "field": "Evidence type", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2025-08-25", "status": "deployed", "scope": "c3" }, "conference.c3.6": { "value": "C02", "field": "Source", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2025-08-25", "status": "deployed", "scope": "c3" }, "conference.c4.0": { "value": "Journal of Software", "field": "Venue", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R02" ], "disclosure_date": "2021", "status": "research", "scope": "c4" }, "conference.c4.1": { "value": "2021", "field": "Year", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R02" ], "disclosure_date": "2021", "status": "research", "scope": "c4" }, "conference.c4.2": { "value": "CPU-side High Performance BLAS Library Optimization in Heterogeneous HPL Algorithm", "field": "Paper / talk / disclosure", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R02" ], "disclosure_date": "2021", "status": "research", "scope": "c4" }, "conference.c4.3": { "value": "Cai Y. et al.", "field": "Presenter / authors", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R02" ], "disclosure_date": "2021", "status": "research", "scope": "c4" }, "conference.c4.4": { "value": "Dhyana", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R02" ], "disclosure_date": "2021", "status": "research", "scope": "c4" }, "conference.c4.5": { "value": "Related research; tested CPU topology", "field": "Evidence type", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R02" ], "disclosure_date": "2021", "status": "research", "scope": "c4" }, "conference.c4.6": { "value": "R02", "field": "Source", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R02" ], "disclosure_date": "2021", "status": "research", "scope": "c4" }, "conference.c5.0": { "value": "CCF Trans. HPC", "field": "Venue", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R01" ], "disclosure_date": "2024-12-13", "status": "research", "scope": "c5" }, "conference.c5.1": { "value": "2024", "field": "Year", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R01" ], "disclosure_date": "2024-12-13", "status": "research", "scope": "c5" }, "conference.c5.2": { "value": "Optimizing depthwise separable convolution on DCU", "field": "Paper / talk / disclosure", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R01" ], "disclosure_date": "2024-12-13", "status": "research", "scope": "c5" }, "conference.c5.3": { "value": "Liu Z. et al.", "field": "Presenter / authors", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R01" ], "disclosure_date": "2024-12-13", "status": "research", "scope": "c5" }, "conference.c5.4": { "value": "64-CU test device", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R01" ], "disclosure_date": "2024-12-13", "status": "research", "scope": "c5" }, "conference.c5.5": { "value": "Related research; kernels / architecture", "field": "Evidence type", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R01" ], "disclosure_date": "2024-12-13", "status": "research", "scope": "c5" }, "conference.c5.6": { "value": "R01", "field": "Source", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R01" ], "disclosure_date": "2024-12-13", "status": "research", "scope": "c5" }, "conference.c6.0": { "value": "CCF Trans. HPC", "field": "Venue", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R03" ], "disclosure_date": "2025-11-18", "status": "research", "scope": "c6" }, "conference.c6.1": { "value": "2025 / 2026", "field": "Year", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R03" ], "disclosure_date": "2025-11-18", "status": "research", "scope": "c6" }, "conference.c6.2": { "value": "Optimizing Standard Convolution for Diverse Precision on DCU", "field": "Paper / talk / disclosure", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R03" ], "disclosure_date": "2025-11-18", "status": "research", "scope": "c6" }, "conference.c6.3": { "value": "Hua H. et al.", "field": "Presenter / authors", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R03" ], "disclosure_date": "2025-11-18", "status": "research", "scope": "c6" }, "conference.c6.4": { "value": "DCU", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R03" ], "disclosure_date": "2025-11-18", "status": "research", "scope": "c6" }, "conference.c6.5": { "value": "Related research; abstract read only", "field": "Evidence type", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R03" ], "disclosure_date": "2025-11-18", "status": "research", "scope": "c6" }, "conference.c6.6": { "value": "R03", "field": "Source", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "R03" ], "disclosure_date": "2025-11-18", "status": "research", "scope": "c6" }, "crosswalk.x1.0": { "value": "Dhyana", "field": "Name", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "R02" ], "disclosure_date": "2018-09-17", "status": "historical", "scope": "x1" }, "crosswalk.x1.1": { "value": "Initial CPU identity", "field": "Meaning", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "R02" ], "disclosure_date": "2018-09-17", "status": "historical", "scope": "x1" }, "crosswalk.x1.2": { "value": "Hygon Family 18h", "field": "Mapped identity", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "R02" ], "disclosure_date": "2018-09-17", "status": "historical", "scope": "x1" }, "crosswalk.x1.3": { "value": "Do not reuse as a later Zen-generation mapping", "field": "Boundary", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "R02" ], "disclosure_date": "2018-09-17", "status": "historical", "scope": "x1" }, "crosswalk.x2.0": { "value": "7100 / 5100 / 3100", "field": "Name", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "shipping", "scope": "x2" }, "crosswalk.x2.1": { "value": "Generation 1 tiers", "field": "Meaning", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "shipping", "scope": "x2" }, "crosswalk.x2.2": { "value": "No. 1 CPU", "field": "Mapped identity", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "shipping", "scope": "x2" }, "crosswalk.x2.3": { "value": "Server / smaller server / workstation tiers", "field": "Boundary", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "shipping", "scope": "x2" }, "crosswalk.x3.0": { "value": "7200 / 5200 / 3200", "field": "Name", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "shipping", "scope": "x3" }, "crosswalk.x3.1": { "value": "Generation 2 tiers", "field": "Meaning", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "shipping", "scope": "x3" }, "crosswalk.x3.2": { "value": "No. 2 CPU", "field": "Mapped identity", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "shipping", "scope": "x3" }, "crosswalk.x3.3": { "value": "Tier is not a generation", "field": "Boundary", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2022-08-09", "status": "shipping", "scope": "x3" }, "crosswalk.x4.0": { "value": "C86-4G", "field": "Name", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "x4" }, "crosswalk.x4.1": { "value": "Fourth-generation host platform", "field": "Meaning", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "x4" }, "crosswalk.x4.2": { "value": "No. 4 CPU; 64-core/socket OEM reference", "field": "Mapped identity", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "x4" }, "crosswalk.x4.3": { "value": "128 cores means two sockets in P04", "field": "Boundary", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2026-09-28", "status": "shipping", "scope": "x4" }, "crosswalk.x5.0": { "value": "Deep Computing No. 1/2/3", "field": "Name", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03", "E11", "E05" ], "disclosure_date": "2026-04-08", "status": "shipping", "scope": "x5" }, "crosswalk.x5.1": { "value": "DCU silicon generations", "field": "Meaning", "basis": "Per reference product; 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