{
  "vendor": "Huawei",
  "cutoff": "2026-09-28",
  "sections": [
    {
      "id": "01",
      "title": [
        "Scope and executive synthesis",
        "研究范围与核心结论"
      ],
      "blocks": [
        {
          "id": "01.scope",
          "type": "prose",
          "text": [
            "Coverage: Kunpeng host CPUs and Ascend NPUs receive deep coverage; UnifiedBus, DPUs, AI NICs, systems and software receive full generation-level coverage.\nPeriod: 2015–28 September 2026; latest verified event: HUAWEI CONNECT 2026.\nFocus: architecture, implementation and the balance between compute, memory and communication.\nRelated lines: Atlas edge inference, HiSilicon networking, optical engines and KV-cache storage where they explain the server stack.\nExclusions: an exhaustive Kirin smartphone, consumer GPU, telecom baseband or storage-drive catalogue; unverified manufacturing and capacity estimates.",
            "覆盖：深入研究鲲鹏主机 CPU、昇腾 NPU；完整梳理灵衢、DPU、AI 网卡、系统和软件的代际演进。\n时间：2015 年至 2026 年 9 月 28 日；最新核验活动为 2026 年华为全联接大会。\n重点：架构、实现，以及计算、内存和通信之间的平衡。\n关联产品：解释服务器技术栈所需的 Atlas 边缘推理、海思网络芯片、光引擎和 KV 缓存存储。\n不包含：完整的麒麟手机、消费 GPU、通信基带或存储硬盘目录，以及未经证实的制造与产能估计。"
          ],
          "sources": [
            "C01",
            "P01",
            "P15",
            "E11"
          ]
        },
        {
          "id": "01.thesis",
          "type": "prose",
          "text": [
            "Huawei’s infrastructure evolved through three architectural commitments. First, it built custom Arm server cores and reusable compute/I/O dies, culminating in the 2019 Kunpeng 920. Second, Ascend separated matrix, vector and scalar work and made explicit data movement central to performance. Third, the system boundary expanded from a server to a switched pool of CPUs, NPUs and memory. CloudMatrix384 made that third commitment concrete; Ascend 950 and UnifiedBus 2.0 extend it with dedicated communication engines and more flexible memory semantics.",
            "华为基础设施的演进围绕三个架构选择展开。首先是自研 Arm 服务器核心与可复用的计算、I/O 裸片，2019 年鲲鹏 920 是这一阶段的代表。其次，昇腾将矩阵、向量、标量工作分离，把显式数据搬运放在性能优化的中心。第三，系统边界从一台服务器扩展到通过交换网络连接的 CPU、NPU 与内存资源池。CloudMatrix384 将第三个选择落地；昇腾 950 和灵衢 2.0 进一步加入专用通信引擎与更灵活的内存语义。"
          ],
          "sources": [
            "P01",
            "C01",
            "R02",
            "P15"
          ]
        },
        {
          "id": "01.current",
          "type": "prose",
          "text": [
            "The strongest current technical disclosure is the Ascend 950 architecture white paper. It describes two compute dies, two I/O dies, up to 36 matrix cores and 72 vector cores, a coherent on-package memory organization and up to 128 MB of accelerator L2. The PR and DT branches explicitly trade memory cost and bandwidth against workload needs. PR targets prefill and recommendation; DT targets training and complex inference. Atlas 350 is a concrete 950PR card configuration, not the maximum specification of the entire chip family.",
            "当前最完整的技术披露是昇腾 950 架构白皮书：两颗计算裸片、两颗 I/O 裸片，最多 36 个矩阵核心与 72 个向量核心，封装内一致性内存组织，以及最高 128 MB 的加速器 L2。PR、DT 两条分支针对工作负载，在内存成本与带宽之间作出不同选择。PR 面向预填充和推荐，DT 面向训练与复杂推理。Atlas 350 是一个具体的 950PR 加速卡配置，不能代表整个芯片家族的最高规格。"
          ],
          "sources": [
            "P15",
            "P14"
          ]
        },
        {
          "id": "01.roadmap",
          "type": "prose",
          "text": [
            "The September 2026 roadmap brings Ascend 960DT readiness forward to Q1 2027 and 960PR to Q3 2027. Atlas 960E is an announced 4,096-NPU, liquid-cooled NPO system; its launch is not evidence that 960 silicon is already generally available. The engineering direction is clear: optical reach, collective offload and a hierarchy of HBM, CPU memory and KV storage increasingly determine usable model throughput. At the same time, the public record remains thinner on recent Kunpeng core internals, foundry processes and measured system power than on Ascend programming and system topology.",
            "2026 年 9 月路线图将昇腾 960DT 就绪时间提前到 2027 年第一季度，960PR 提前到第三季度。Atlas 960E 是已经发布的 4096 NPU、液冷、NPO 系统方案；发布本身不等于 960 芯片已全面商用。工程方向很明确：光互联距离、集合通信卸载，以及 HBM、CPU 内存和 KV 存储的分层，越来越决定模型的有效吞吐。与此同时，近期鲲鹏核心内部结构、制造工艺及系统实测功耗的公开程度，仍低于昇腾编程模型与系统拓扑。"
          ],
          "sources": [
            "E01",
            "E03",
            "E11",
            "P08",
            "P15"
          ]
        },
        {
          "id": "headline",
          "type": "table",
          "table": "headline"
        }
      ]
    },
    {
      "id": "02",
      "title": [
        "Reading the numbers and product names",
        "数值口径与产品命名"
      ],
      "blocks": [
        {
          "id": "02.rules",
          "type": "prose",
          "text": [
            "Bandwidth uses decimal GB/s and TB/s. Ethernet Gb/s is divided by eight for a raw one-direction byte rate; packet, encoding and protocol overheads remain. A full-duplex total is halved only when the source explicitly identifies it as bidirectional. Peak compute counts a multiply-add as two operations. Matrix-only throughput is kept separate from the sum of Cube and Vector throughput. No sparse multiplier is applied. Precision labels remain exact: FP16 is not BF16, INT8 is not FP8, and MXFP4 is not a generic interchangeable four-bit format.",
            "带宽采用十进制 GB/s、TB/s。以太网 Gb/s 除以八得到单向原始字节速率，仍需扣除编码、报文和协议开销。只有资料明确标为双向汇总时，才将其折半。峰值算力按一次乘加两次运算计；矩阵核心算力与 Cube、Vector 合计算力分开列出，不引入稀疏倍率。精度名称保持原样：FP16 不等于 BF16，INT8 不等于 FP8，MXFP4 也不能与任意四比特格式互换。"
          ],
          "sources": [
            "C01",
            "P14",
            "P15"
          ]
        },
        {
          "id": "02.identity",
          "type": "prose",
          "text": [
            "Ascend names a processor family, DaVinci an architecture, Atlas hardware products, and CloudMatrix a system/cloud architecture. Kunpeng is the CPU family; TaiShan is also used for server products, while TaiShan V110 denotes the 920 core. Unified Buffer and UnifiedBus both abbreviate to UB: the former is local AI-core storage and the latter is the system interconnect. A product marked n/d has a material specification absent from the reviewed evidence; this is not a zero or proof that the feature does not exist.",
            "昇腾是处理器家族，达芬奇是架构，Atlas 是硬件产品，CloudMatrix 是系统／云架构。鲲鹏是 CPU 家族；TaiShan 也用于服务器命名，而 TaiShan V110 指 920 的核心。Unified Buffer 与 UnifiedBus 均缩写为 UB：前者是 AI 核内部存储，后者是系统互联。表格中的 n/d 表示已审阅资料未确定该项规格，不表示数值为零，也不证明不存在该功能。"
          ],
          "sources": [
            "P01",
            "P15",
            "R02"
          ]
        },
        {
          "id": "02.evidence",
          "type": "prose",
          "text": [
            "The bibliography is connected to chapters through a compact source map. Hot Chips 2019 supplies the original DaVinci organization; the HPCA 2021 industry paper and Huawei’s published technical collection add programming and implementation context. IEEE Micro’s Kunpeng paper supplies CPU internals. IEEE Micro is a journal, not the MICRO conference. Related ASPLOS, MICRO and ISCA research is included without treating experimental proposals as shipping circuitry. Announced capabilities, architectural maxima and measured deployments retain their separate scopes.",
            "参考资料通过文末来源映射对应各章。Hot Chips 2019 提供初代达芬奇组织结构，HPCA 2021 工业论文及华为公开技术文集补充编程和实现背景，IEEE Micro 的鲲鹏论文提供 CPU 内部细节。IEEE Micro 是期刊，不是 MICRO 会议。ASPLOS、MICRO、ISCA 的相关研究单独归类，不把实验性方案当成已商用电路。已公布能力、架构上限与实际部署配置始终保持各自口径。"
          ],
          "sources": [
            "C01",
            "C04",
            "P01",
            "R01",
            "R03",
            "R05",
            "R06"
          ]
        }
      ]
    },
    {
      "id": "03",
      "title": [
        "Host CPU generations",
        "主机 CPU 代际总表"
      ],
      "blocks": [
        {
          "id": "cpu",
          "type": "table",
          "table": "cpu"
        }
      ]
    },
    {
      "id": "04",
      "title": [
        "2015–2019: from server Arm to Kunpeng 920",
        "2015—2019：从服务器 Arm 到鲲鹏 920"
      ],
      "blocks": [
        {
          "id": "04.baseline",
          "type": "prose",
          "text": [
            "The 2015 Linux HNS driver submission establishes Hi1610 and Hi1612 as an early server-platform baseline. Kunpeng 916 then used 32 Arm cores and a DDR4 platform. That generation’s significance was platform integration: boot firmware, network drivers, memory validation and operating-system enablement made the later custom-core server product practical. It is useful context, but the reviewed platform documents do not establish the same core implementation as the custom V110 introduced with Kunpeng 920.",
            "2015 年 Linux HNS 驱动提交记录确立了 Hi1610、Hi1612 这一早期服务器平台基线。随后鲲鹏 916 采用 32 个 Arm 核和 DDR4 平台。这一代的意义在于平台集成：启动固件、网络驱动、内存验证与操作系统适配，为后续自研核心服务器奠定基础。它提供了必要背景，但已审阅的平台资料并未证明它与鲲鹏 920 的自研 V110 采用相同核心实现。"
          ],
          "sources": [
            "R07",
            "C03",
            "P10",
            "P16"
          ]
        },
        {
          "id": "04.core",
          "type": "prose",
          "text": [
            "Kunpeng 920’s TaiShan V110 is an out-of-order Arm core with a four-instruction front end/dispatch organization and a multilevel branch-prediction structure. The published design provides separate 64 KiB instruction and data L1 caches and 512 KiB of private L2. Its floating-point/vector units implement 128-bit NEON operations; it should not be assigned Neoverse or SVE characteristics merely because it executes the Arm ISA. Public detail does not establish a complete reorder-buffer, scheduler, load/store queue or branch-predictor capacity inventory.",
            "鲲鹏 920 的 TaiShan V110 是乱序 Arm 核，采用四指令宽的前端／分发组织和多级分支预测结构。公开设计提供独立的 64 KiB 指令、数据 L1，以及每核 512 KiB 私有 L2。浮点／向量单元支持 128 位 NEON 运算；不能因为执行 Arm 指令集，就把 Neoverse 或 SVE 特征套用到它上面。公开资料并未完整给出重排序缓冲、调度器、访存队列及预测器的容量。"
          ],
          "sources": [
            "P01"
          ]
        },
        {
          "id": "04.cache",
          "type": "prose",
          "text": [
            "The LLC averages about 1 MB per core in the 64-core configuration. Tags and distributed data slices connect through the on-die fabric; the paper organizes coherence around home agents rather than a single large centralized cache. The dual-ring fabric emphasizes predictable service and throughput. These details matter because a server’s sustainable performance depends on where a cache miss is resolved and how memory traffic crosses compute-die boundaries, not simply on the sum of cache capacity.",
            "64 核配置的末级缓存平均约为每核 1 MB。标签与分布式数据切片连接片上互联，论文围绕归属代理组织一致性，而不是采用一个集中式大缓存。双环互联强调可预测服务与吞吐。这些细节决定缓存未命中在哪里处理、内存流量如何跨计算裸片，因此持续性能不能只看缓存容量总和。"
          ],
          "sources": [
            "P01"
          ]
        },
        {
          "id": "04.chiplet",
          "type": "prose",
          "text": [
            "The high-end reference combines two 32-core 7 nm compute dies with a 16 nm compute-I/O die. The paper describes CoWoS assembly and a roughly 400 GB/s coherent die-to-die connection; its bandwidth direction is not specified and is therefore not halved in this report. A single-compute-die Lite configuration demonstrates the reuse strategy. Compute and I/O technology can be selected separately, and the same I/O building blocks feed other HiSilicon products. The cost is that package links, memory placement and NUMA policy become first-class design choices.",
            "高端参考实现将两颗 32 核、7 nm 计算裸片与一颗 16 nm 计算 I/O 裸片组合。论文描述了 CoWoS 封装与约 400 GB/s 的一致性裸片互联，但没有明确带宽方向，因此本报告不将其折半。单计算裸片的 Lite 配置体现了复用策略。计算、I/O 可分别选择工艺，同类 I/O 构件也用于其他海思产品。代价是封装链路、内存放置与 NUMA 策略成为一级设计问题。"
          ],
          "sources": [
            "P01"
          ]
        },
        {
          "id": "04.balance",
          "type": "prose",
          "text": [
            "Eight 64-bit DDR4-2933 channels yield a theoretical 187.7 GB/s, or 2.93 GB/s per core at 64 cores. The CPU also offers PCIe 4.0 and integrated high-speed Ethernet options. UMA and NUMA presentation modes are both discussed in the technical record; one address space should not be read as identical physical latency to every memory location. The practical AI-host role is data preparation, orchestration, networking and memory staging, while dense matrix work belongs on Ascend.",
            "八个 64 位 DDR4-2933 通道提供理论 187.7 GB/s，64 核时平均每核 2.93 GB/s。CPU 同时提供 PCIe 4.0 与集成高速以太网选项。技术资料讨论了 UMA、NUMA 两种呈现模式；统一地址空间并不意味着访问所有物理内存的时延相同。在 AI 系统中，其实际职责主要是数据准备、编排、网络和内存暂存，密集矩阵工作则交给昇腾。"
          ],
          "sources": [
            "P01",
            "C03",
            "R04"
          ]
        }
      ]
    },
    {
      "id": "05",
      "title": [
        "Updated 920 and Kunpeng 950: platform evolution",
        "新款 920 与鲲鹏 950：平台演进"
      ],
      "blocks": [
        {
          "id": "05.920new",
          "type": "prose",
          "text": [
            "The current motherboard portfolio explicitly distinguishes “new-model Kunpeng 920” from the original DDR4 product. New-model boards support simultaneous multithreading, DDR5 and PCIe 5.0, including two- and four-socket configurations. The 920 brand therefore spans materially different platforms. It would be incorrect to combine the original V110 core/cache disclosure with the newer board’s memory and I/O and call that a fully documented single SKU.",
            "当前主板产品线明确区分“鲲鹏 920 新型号”和原 DDR4 产品。新型号主板支持双线程、DDR5、PCIe 5.0，并提供双路与四路配置。因此，920 品牌覆盖了实质不同的平台。不能把原 V110 的核心／缓存披露与新版主板的内存、I/O 合并，再把它当成一个资料完整的单一 SKU。"
          ],
          "sources": [
            "P09"
          ]
        },
        {
          "id": "05.950board",
          "type": "prose",
          "text": [
            "The 2026 H1 Kunpeng 950 board brief is more concrete than the earlier roadmap: it specifies two processors with 64- or 96-core options, a 2.3 GHz base clock with Turbo, up to 24 DIMMs, DDR5 RDIMM operation up to 7200 MT/s and MRDIMM operation up to 8800 MT/s. Its 3 TB capacity is a two-socket system configuration. Twenty-four DIMM sockets do not establish twelve memory channels per processor; the document does not disclose the necessary channel-to-slot mapping.",
            "2026 年上半年鲲鹏 950 主板资料比早期路线图更具体：双处理器、64 或 96 核选项，2.3 GHz 基准频率并支持 Turbo，最多 24 条 DIMM，DDR5 RDIMM 最高 7200 MT/s、MRDIMM 最高 8800 MT/s。3 TB 容量属于双路系统配置。24 个 DIMM 插槽不能推导出每处理器 12 个内存通道，因为资料未给出通道与插槽映射。"
          ],
          "sources": [
            "P08"
          ]
        },
        {
          "id": "05.security",
          "type": "prose",
          "text": [
            "The platform emphasizes Arm CCA, secure device access, trusted measurement and RAS, including online handling of faulty cores. These are important when a CPU hosts multi-tenant AI services or provides memory to other processors. They do not establish a confidential-computing guarantee for every external NPU, NIC and software path. The earlier 192-core/384-thread 950 configuration remains separately identified as a roadmap item unless a matching shipping SKU and system are documented.",
            "平台强调 Arm CCA、安全设备访问、可信度量与 RAS，包括故障核心的在线处理。当 CPU 承载多租户 AI 服务、或向其他处理器提供内存时，这些能力尤为重要，但不能据此推定每条外部 NPU、网卡和软件路径都具备机密计算保证。早期公布的 192 核／384 线程 950 配置，在没有匹配的商用 SKU 与系统资料前，仍单列为路线图项。"
          ],
          "sources": [
            "P08",
            "E02"
          ]
        },
        {
          "id": "05.role",
          "type": "prose",
          "text": [
            "Kunpeng’s emerging role extends beyond feeding an accelerator over PCIe. CloudMatrix and the later Peerium architecture expose CPU-attached memory as a resource for the wider compute domain. This can improve capacity efficiency for embedding tables, KV state and agent sandboxes, but locality still matters: remote bandwidth, synchronization, ownership and failure recovery have to be handled by the runtime. A large pool is a capacity resource before it is a substitute for local HBM bandwidth.",
            "鲲鹏的新角色超出了通过 PCIe 为加速器提供数据。CloudMatrix 及后续 Peerium 架构把 CPU 所连内存作为更大计算域的资源，可改善嵌入表、KV 状态和智能体沙箱的容量利用率。但局部性仍然重要：远端带宽、同步、所有权和故障恢复都需要运行时处理。大内存池首先是容量资源，不能直接替代本地 HBM 带宽。"
          ],
          "sources": [
            "R02",
            "E12",
            "E11"
          ]
        }
      ]
    },
    {
      "id": "06",
      "title": [
        "Ascend generation comparison",
        "昇腾代际比较"
      ],
      "blocks": [
        {
          "id": "accelerator",
          "type": "table",
          "table": "accelerator"
        },
        {
          "id": "06.note",
          "type": "prose",
          "text": [
            "The 950 table uses Cube-only throughput, at the largest disclosed bin for each chip and the actual 28-Cube bin for Atlas 350. The Atlas 350 product page instead advertises 425 TFLOPS BF16, 804 TFLOPS MXFP8/HiF8 and 1,561 TFLOPS MXFP4 by combining Cube and Vector capability. The white paper gives 378, 756 and 1,513 TFLOPS respectively for its Cube engines. These are different accounting bases, not a contradiction. A quoted mixed-engine peak is not necessarily simultaneously attainable by one GEMM kernel.",
            "950 表格采用仅 Cube 算力：芯片取公开最高配置，Atlas 350 取实际的 28 Cube 配置。Atlas 350 产品页宣传 BF16 425 TFLOPS、MXFP8／HiF8 804 TFLOPS、MXFP4 1561 TFLOPS，口径为 Cube 与 Vector 合计；白皮书对应 Cube 数值分别为 378、756、1513 TFLOPS。两者是统计口径不同，并不矛盾；混合引擎峰值也不一定能由一个 GEMM 内核同时实现。"
          ],
          "sources": [
            "P14",
            "P15"
          ]
        }
      ]
    },
    {
      "id": "07",
      "title": [
        "2018–2021: DaVinci and the first Ascend systems",
        "2018—2021：达芬奇与首代昇腾系统"
      ],
      "blocks": [
        {
          "id": "07.dataflow",
          "type": "prose",
          "text": [
            "DaVinci’s original design separates scalar control, vector operations and a Cube matrix engine. A 16×16×16 FP16 multiplication produces 4,096 multiply-accumulates, conventionally counted as 8,192 floating-point operations per cycle. That headline rate requires operands to be tiled and reused through local buffers. MTE data-movement engines, L1 storage, L0 operand/result buffers and the Unified Buffer form an explicitly managed hierarchy. Overlapping transfer, matrix work and vector epilogues is the central programming task.",
            "初代达芬奇将标量控制、向量运算和 Cube 矩阵引擎分离。16×16×16 的 FP16 计算包含 4096 次乘加，通常计为每周期 8192 次浮点运算。要达到这一峰值，必须通过局部缓冲分块并复用操作数。MTE 数据搬运引擎、L1、L0 操作数／结果缓冲与 Unified Buffer 组成显式管理的层级。编程的核心是让搬运、矩阵计算和向量后处理重叠执行。"
          ],
          "sources": [
            "C01",
            "P01"
          ]
        },
        {
          "id": "07.310",
          "type": "prose",
          "text": [
            "Ascend 310 put that architecture into an approximately 8 W inference chip with two AI cores, up to 16 TOPS INT8 or 8 TFLOPS FP16. Atlas modules and cards coupled inference with video preprocessing and host integration. The point of covering 310 alongside a datacenter product is architectural continuity: the local-buffer and operator-programming model scales across power envelopes. Mobile SoCs using DaVinci blocks and later 310P edge products extend this lineage, but their CPU and memory subsystems are different products.",
            "昇腾 310 将该架构用于约 8 W 的推理芯片，包含两个 AI 核，最高提供 INT8 16 TOPS 或 FP16 8 TFLOPS。Atlas 模组与板卡把推理、视频预处理和主机集成结合起来。与数据中心产品一同讨论 310，是为了说明局部缓冲和算子编程模型如何跨功耗范围延续。采用达芬奇模块的手机 SoC、后续 310P 边缘产品延展了这一谱系，但其 CPU 与内存子系统属于不同产品。"
          ],
          "sources": [
            "C01",
            "P01",
            "E07",
            "P12"
          ]
        },
        {
          "id": "07.910",
          "type": "prose",
          "text": [
            "Ascend 910 scaled to 32 AI cores and a package combining a 456 mm² compute die, an I/O die and four HBM2 stacks. The Hot Chips talk shows a 6×4 on-chip mesh, roughly 1.2 TB/s external memory bandwidth and HCCS plus Ethernet interfaces. Its compute-die area must not be confused with the sum of all die areas in the package. Likewise, the same talk’s concept combining logic, 3D SRAM and twelve HBM stacks is a forward-looking packaging illustration, not the shipping 910 configuration.",
            "昇腾 910 扩展到 32 个 AI 核，封装包含一颗 456 mm² 计算裸片、一颗 I/O 裸片和四个 HBM2 堆栈。Hot Chips 演讲展示了 6×4 片上网格、约 1.2 TB/s 外存带宽，以及 HCCS 和以太网接口。计算裸片面积不能与封装内所有裸片面积之和混淆。同场演讲中“逻辑＋3D SRAM＋十二个 HBM”的构想属于前瞻封装示意，并不是商用 910 配置。"
          ],
          "sources": [
            "C01"
          ]
        },
        {
          "id": "07.implementation",
          "type": "prose",
          "text": [
            "Hot Chips used a 350 W design target, while the August 2019 launch reported a maximum of 310 W for 256 TFLOPS FP16 and 512 TOPS INT8. The difference is a disclosure update, not permission to apply 310 W to every later 910 board. The HPCA 2021 industry account explains how the hardware and software stack serve multiple AI scenarios. Taken together, these disclosures establish a complete early architecture story: specialized execution, explicitly controlled storage, heterogeneous packaging and a compiler/runtime that must schedule the resulting parallel engines.",
            "Hot Chips 使用 350 W 设计目标，而 2019 年 8 月发布时给出的最大功耗为 310 W，对应 FP16 256 TFLOPS、INT8 512 TOPS。差异属于披露更新，不能把 310 W 套到所有后续 910 板卡。HPCA 2021 工业论文解释了软硬件栈如何覆盖多种 AI 场景。综合这些资料，可以还原早期架构全貌：专用执行单元、显式控制的存储、异构封装，以及负责调度并行引擎的编译器和运行时。"
          ],
          "sources": [
            "C01",
            "P01",
            "C04",
            "E20"
          ]
        }
      ]
    },
    {
      "id": "08",
      "title": [
        "A2 to A3: accelerator nodes become a compute pool",
        "从 A2 到 A3：加速器节点走向计算资源池"
      ],
      "blocks": [
        {
          "id": "08.a2",
          "type": "prose",
          "text": [
            "Atlas A2 products and the 910B family represent the intermediate server generation. Processor suffixes, enabled cores, memory configurations and server names vary; a single enthusiast specification table is not a safe substitute for an exact product document. The ISCA 2026 ENEC paper identifies its 910B2 test device as 24 Cube and 48 Vector units with 64 GB HBM, a useful fixed reference within that broader family. The ASPLOS 2025 study is valuable because it measures Ascend operator behavior and develops a component-level roofline model. It shows why peak matrix throughput alone misses serial execution phases, pipeline imbalance and interference between computation and data movement. That is product characterization and optimization research, not a disclosure of an unrelated next-generation chip.",
            "Atlas A2 产品与 910B 家族构成中间一代服务器平台。处理器后缀、启用核心、内存配置和服务器名称各不相同，不能用一张非官方规格表替代具体产品文档。ISCA 2026 ENEC 论文明确其 910B2 测试设备配置为 24 个 Cube、48 个 Vector 单元及 64 GB HBM，为这一较大的产品家族提供了固定参考。ASPLOS 2025 研究的价值在于测量昇腾算子行为，并构建组件级 Roofline 模型，说明仅看矩阵峰值会忽略串行阶段、流水线失衡，以及计算与数据搬运的干扰。这属于产品特征分析和优化研究，而不是另一款下一代芯片的发布。"
          ],
          "sources": [
            "P12",
            "R01",
            "R05"
          ]
        },
        {
          "id": "08.a3",
          "type": "prose",
          "text": [
            "Huawei dates Atlas 900 A3 delivery to March 2025 and identifies its accelerators as Ascend 910C. The CloudMatrix384 paper describes the corresponding dual-compute-die NPU package with eight memory stacks. Each die has 24 matrix cores and 48 vector cores, seven scale-up transceivers and a separate scale-out interface. The package-level count is therefore 48 matrix and 96 vector cores. This is an important hierarchy change: matrix engines, compute dies, NPU packages and server nodes are four different counting units.",
            "华为将 Atlas 900 A3 交付起点定为 2025 年 3 月，并明确其加速器为昇腾 910C。CloudMatrix384 论文描述了对应的双计算裸片、八内存堆栈 NPU 封装。每裸片有 24 个矩阵核心、48 个向量核心、七个纵向扩展收发器，以及独立的横向扩展接口；因此每封装为 48 个矩阵、96 个向量核心。这里的矩阵引擎、计算裸片、NPU 封装与服务器节点是四种不同计数单位。"
          ],
          "sources": [
            "R02",
            "E02"
          ]
        },
        {
          "id": "08.planes",
          "type": "prose",
          "text": [
            "CloudMatrix384 contains 48 compute nodes, each with eight NPUs, four Kunpeng CPUs and seven on-board UB switches: 384 NPUs and 192 CPUs in total. Twelve compute racks and four communication racks house a two-tier fabric. Seven independent switching subplanes connect the nodes without L2 oversubscription in the published topology. The CPU and NPU resources share the UB scale-up plane; NPU scale-out uses a separate RoCE plane; a QingTian DPU provides the VPC and storage-facing plane. The published system does not collapse all three into one physical network.",
            "CloudMatrix384 包含 48 个计算节点，每节点配置八颗 NPU、四颗鲲鹏 CPU 和七颗板载 UB 交换芯片，合计 384 NPU、192 CPU。十二个计算柜与四个通信柜承载两级互联；公开拓扑用七个独立交换子平面连接节点，第二级没有带宽超售。CPU、NPU 共享 UB 纵向扩展平面，NPU 横向扩展使用独立 RoCE 平面，擎天 DPU 提供 VPC 和面向存储的平面。已披露系统并未把三个平面全部合并成一个物理网络。"
          ],
          "sources": [
            "R02"
          ]
        },
        {
          "id": "08.serving",
          "type": "prose",
          "text": [
            "CloudMatrix-Infer separates prefill, decode and cache resources and uses large expert-parallel domains for mixture-of-experts serving. The paper reports DeepSeek-R1 results including 6,688 prefill tokens/s/NPU for a 4K prompt and 1,943 decode tokens/s/NPU with a 4K cache and time per output token below 50 ms. A tighter 15 ms constraint gives 538 decode tokens/s/NPU. These are vendor-reported end-to-end measurements with specific quantization and scheduling choices. They demonstrate the importance of the throughput/latency operating point; they are not interchangeable with a chip’s FLOPS or an uncontrolled GPU comparison.",
            "CloudMatrix-Infer 分离预填充、解码与缓存资源，并用大规模专家并行域承载混合专家模型。论文报告了 DeepSeek-R1 结果：4K 提示下每 NPU 预填充 6688 token/s；4K 缓存、每输出 token 时延低于 50 ms 时，解码为每 NPU 1943 token/s；更严格的 15 ms 条件下为 538 token/s。这些是采用特定量化和调度策略的厂商端到端测试，体现吞吐／时延工作点的重要性，不能与芯片 FLOPS 或条件不一致的 GPU 测试直接互换。"
          ],
          "sources": [
            "R02"
          ]
        }
      ]
    },
    {
      "id": "09",
      "title": [
        "Ascend 950: computation, memory and communication co-design",
        "昇腾 950：计算、内存与通信协同设计"
      ],
      "blocks": [
        {
          "id": "09.partition",
          "type": "prose",
          "text": [
            "The 950 package separates two AI dies from two I/O dies. PR uses eight memory modules; DT uses four higher-bandwidth modules. The maximum physical organization has 36 AI subsystems, each containing one Cube and two Vector cores, while commercial bins disable different amounts of compute and memory. Eight Linx816 Armv8-A CPU cores with two threads each supply local control and CPU operators. Their own caches are distinct from accelerator L2; hardware coherence connects the CPU and AI-core memory views inside the package.",
            "950 封装将两颗 AI 裸片与两颗 I/O 裸片分离。PR 使用八个内存模组，DT 使用四个更高带宽模组。最大物理组织包含 36 个 AI 子系统，每个包含一个 Cube、两个 Vector 核；不同商业配置启用的计算与内存资源不同。八个支持双线程的 Linx816 Armv8-A CPU 核负责本地控制与 CPU 算子，其私有缓存与加速器 L2 分开，封装内硬件一致性连接 CPU 与 AI 核的内存视图。"
          ],
          "sources": [
            "P15"
          ]
        },
        {
          "id": "09.vector",
          "type": "prose",
          "text": [
            "DaVinci 3 strengthens work around the matrix multiply. Register-based vector execution, dual issue and SIMD/SIMT function blocks address elementwise arithmetic, gather/scatter and branch-heavy code. SIMD remains the principal throughput mode; SIMT improves irregular kernels rather than turning the entire NPU into a conventional GPU. A direct Cube-to-Vector path and conversions during result movement reduce round trips through shared memory. N-dimensional DMA performs layout-aware transfers, easing the cost of tensor tiling and rearrangement.",
            "达芬奇第三代强化了矩阵乘法周围的工作。基于寄存器的向量执行、双发射以及 SIMD／SIMT 函数块，分别服务逐元素运算、gather/scatter 和分支较多的代码。SIMD 仍是主要吞吐模式；SIMT 改善不规则内核，并不意味着整个 NPU 变成传统 GPU。Cube 到 Vector 的直连通路及结果搬运中的格式转换，减少了共享存储往返；N 维 DMA 提供感知布局的搬运，降低张量分块与重排成本。"
          ],
          "sources": [
            "P15",
            "P14"
          ]
        },
        {
          "id": "09.buffers",
          "type": "prose",
          "text": [
            "The disclosed per-AI-core storage includes 512 KB L1, 64 KB each for L0A and L0B, 256 KB L0C and 512 KB Unified Buffer. Global accelerator L2 reaches 128 MB. Its 512-byte lines are divided into 128-byte sectors, allowing small irregular accesses without always moving a full line. Software can use allocation hints and residency controls. Coherence across the two dies does not eliminate locality: the white paper explicitly preserves local affinity, so scheduling and tiling should still avoid unnecessary cross-die movement.",
            "公开的每 AI 核存储包括 512 KB L1、各 64 KB 的 L0A 和 L0B、256 KB L0C，以及 512 KB Unified Buffer。全局加速器 L2 最高 128 MB；512 字节缓存行划分为 128 字节扇区，使小粒度离散访问不必总搬运完整缓存行。软件可使用分配提示和驻留控制。双裸片一致性没有消除局部性：白皮书明确保留本地亲和性，因此调度和分块仍应减少不必要的跨裸片搬运。"
          ],
          "sources": [
            "P15"
          ]
        },
        {
          "id": "09.io",
          "type": "prose",
          "text": [
            "Seventy-two 112 Gb/s SerDes lanes form eighteen ×4 ports. This is 56 GB/s raw per port per direction, or 1,008 GB/s across all ports; Huawei quotes 2,016 GB/s bidirectional. Four ports can instead implement PCIe 5.0 ×16, and two ports can implement two 400 Gb/s UBoE interfaces. Those modes consume shared physical resources. A design cannot add maximum UB, PCIe and Ethernet figures as if each came from a separate set of pins. Optics may further constrain off-enclosure speed.",
            "72 条 112 Gb/s SerDes 通道组成 18 个 ×4 端口。每端口原始单向带宽为 56 GB/s，全部端口单向合计 1008 GB/s，华为给出的双向值为 2016 GB/s。其中四个端口可改作 PCIe 5.0 ×16，两个端口可改作两路 400 Gb/s UBoE。这些模式复用物理资源，因此不能把最大 UB、PCIe、以太网带宽当成三组独立引脚直接相加。跨机框速率还可能受到光模块限制。"
          ],
          "sources": [
            "P15"
          ]
        },
        {
          "id": "09.offload",
          "type": "prose",
          "text": [
            "STARS 2.0 schedules heterogeneous engines and synchronizes their work. The CCU executes collective-communication tasks without dedicating the same AI cores to every transfer and reduction. URMA provides asynchronous remote-memory/message operations; UB Memory provides synchronous load/store/atomic semantics. These are complementary mechanisms. The published 128 TB access capability of a chip interface, the 8,192-card architectural domain and a particular SuperPoD’s advertised address space are separate limits with separate scopes.",
            "STARS 2.0 负责异构引擎调度与同步；CCU 执行集合通信任务，减少每次传输和归约都占用 AI 核的需要。URMA 提供异步远端内存／消息操作，UB Memory 提供同步 load/store/atomic 语义，两者互补。芯片接口公开的 128 TB 访问能力、8192 卡架构域，以及某款超节点宣传的地址空间，分别属于不同范围的限制，不能合并成一个数字。"
          ],
          "sources": [
            "P15"
          ]
        },
        {
          "id": "09.card",
          "type": "prose",
          "text": [
            "Atlas 350 demonstrates why chip maxima must be translated into board topology. Its 112 GB HBM runs at 1.4 TB/s, and its board power is at most 600 W. A four-card full mesh uses three ×4 UB ports per card and advertises 318 GB/s bidirectional; a two-card arrangement uses four ports for 424 GB/s. Their one-direction equivalents are 159 and 212 GB/s. Both are much smaller than the full chip I/O maximum, because the card exposes a different port allocation and physical link configuration.",
            "Atlas 350 说明芯片最大值必须转换成板级拓扑再分析。其 112 GB HBM 带宽为 1.4 TB/s，板卡最大功耗 600 W。四卡全互连时，每卡使用三个 ×4 UB 端口，双向 318 GB/s；双卡时使用四个端口，双向 424 GB/s，折合单向分别为 159、212 GB/s。这两者都明显低于完整芯片 I/O 上限，因为板卡采用不同的端口分配与物理链路配置。"
          ],
          "sources": [
            "P14",
            "P15"
          ]
        }
      ]
    },
    {
      "id": "10",
      "title": [
        "960 and later: roadmap revisions and optical systems",
        "960 及后续：路线图更新与光互联系统"
      ],
      "blocks": [
        {
          "id": "10.timeline",
          "type": "prose",
          "text": [
            "The 2025 announcement named 950PR for Q1 2026, 950DT for Q4 2026, and a later 960 generation. It described an Atlas 950 design point of 8,192 accelerators across 160 cabinets. The July 2026 WAIC disclosure instead describes a particular 1,024-card Atlas 950 with 1 EFLOPS FP8, 2 EFLOPS FP4 and a 256 TB unified address space. The later white paper still supports an 8,192-card architectural domain. These numbers describe a roadmap design point, a concrete system configuration and an architecture limit; they need not be forced into one product row.",
            "2025 年发布将 950PR 定于 2026 年第一季度、950DT 定于第四季度，并公布后续 960 代际；当时 Atlas 950 的设计点是 160 柜、8192 加速器。2026 年 7 月 WAIC 则披露一种具体的 1024 卡 Atlas 950 配置，提供 FP8 1 EFLOPS、FP4 2 EFLOPS 和 256 TB 统一地址空间。后续白皮书仍支持 8192 卡架构域。这些数值分别属于路线图设计点、具体系统配置与架构上限，不应强行合并为同一个产品规格。"
          ],
          "sources": [
            "E02",
            "E18",
            "P15"
          ]
        },
        {
          "id": "10.960",
          "type": "prose",
          "text": [
            "At HUAWEI CONNECT 2026, 960DT readiness moved forward by three quarters to Q1 2027, and 960PR by one quarter to Q3 2027. The company also named 970 and 980 for 2028 and 2029. Atlas 960E couples 4,096 NPUs with Hi-ONE near-packaged optical engines and liquid cooling. Its advertised system peaks are 8 EFLOPS FP8 and 16 EFLOPS FP4 with up to 1 PB of HBM. A system announcement and testing milestone should be tracked separately from silicon readiness and broad customer availability.",
            "2026 年华为全联接大会将 960DT 就绪时间提前三个季度至 2027 年第一季度，960PR 提前一个季度至第三季度，并公布 2028 年的 970 与 2029 年的 980。Atlas 960E 将 4096 颗 NPU、Hi-ONE 近封装光引擎和液冷结合，宣传系统峰值为 FP8 8 EFLOPS、FP4 16 EFLOPS，HBM 最高 1 PB。系统发布、测试里程碑、芯片就绪和广泛客户可用，应分别跟踪。"
          ],
          "sources": [
            "E11",
            "E03",
            "E12"
          ]
        }
      ]
    },
    {
      "id": "11",
      "title": [
        "Scale-up links and memory semantics",
        "纵向扩展链路与内存语义"
      ],
      "blocks": [
        {
          "id": "interconnect",
          "type": "table",
          "table": "interconnect"
        },
        {
          "id": "11.semantics",
          "type": "prose",
          "text": [
            "A shared address range is only one part of a memory system. The protocol must also define ordering, atomics, cacheability, synchronization, permissions and failure behavior. Ascend 950 explicitly documents coherent caches across its compute dies and CPU/AI subsystem; that does not establish uniform CPU-style cache coherence across every SuperPoD endpoint. URMA, UB Memory and UBoE should be evaluated by their own semantics and the software paths that use them.",
            "共享地址范围只是内存系统的一部分，协议还必须定义顺序、原子操作、可缓存性、同步、权限和故障行为。昇腾 950 明确描述了计算裸片之间及 CPU／AI 子系统之间的缓存一致性，但这不足以证明整个超节点每个端点都采用统一的 CPU 式缓存一致性。URMA、UB Memory、UBoE 应分别按自身语义与软件使用路径评估。"
          ],
          "sources": [
            "P15",
            "R02"
          ]
        }
      ]
    },
    {
      "id": "12",
      "title": [
        "DPUs, NICs and the AI communication path",
        "DPU、网卡与 AI 通信路径"
      ],
      "blocks": [
        {
          "id": "network",
          "type": "table",
          "table": "network"
        },
        {
          "id": "12.distinction",
          "type": "prose",
          "text": [
            "Huawei has three distinct networking roles. A conventional or smart NIC connects a host and may offload packet processing. A DPU moves infrastructure services and trust boundaries away from the tenant CPU. An AI NIC prioritizes accelerator communication, direct memory access and collective submission. A network switch and a UB scale-up switch are separate products again. Sharing HiSilicon IP or software interfaces does not make these categories interchangeable.",
            "华为网络产品有三类不同职责。标准或智能网卡连接主机，可卸载报文处理；DPU 将基础设施服务和信任边界从租户 CPU 中移出；AI 网卡优先处理加速器通信、直接内存访问和集合通信下发。网络交换机与 UB 纵向扩展交换芯片又属于另外的产品。共享海思 IP 或软件接口，并不意味着这些类别可以互换。"
          ],
          "sources": [
            "P04",
            "P06",
            "P07",
            "E13",
            "P15"
          ]
        },
        {
          "id": "12.sp900",
          "type": "prose",
          "text": [
            "The SP923Q is a concrete SP900-family DPU: a 24-core Hi1822, four DDR4-2400 channels with 32 GB ECC memory, PCIe 4.0 ×16 and four 25GE ports. Two small M.2 drives support the local operating environment; DPAK exposes network, storage and compute acceleration. The brief specifies an 8 A at 12 V supply requirement, which is not a declared 96 W TDP. Its host link also has more raw capacity than four 25GE ports, illustrating that PCIe provision and external network throughput are different constraints.",
            "SP923Q 是一个规格明确的 SP900 家族 DPU：24 核 Hi1822、四通道 DDR4-2400 与 32 GB ECC 内存、PCIe 4.0 ×16、四个 25GE 端口。两块小容量 M.2 盘支持本地运行环境，DPAK 提供网络、存储与计算加速接口。资料要求 12 V、8 A 供电，这不等于声明了 96 W TDP。其主机链路原始容量也高于四路 25GE，说明 PCIe 配置与外部网络吞吐是不同约束。"
          ],
          "sources": [
            "P04"
          ]
        },
        {
          "id": "12.ainic",
          "type": "prose",
          "text": [
            "The 2026 SP560 announcement adds an 800G AI NIC with UnifiedBus and PCIe host attachment. Direct access to accelerator memory and programmable protocol handling are the disclosed differentiators; the public event record does not provide a full port map, SerDes inventory, embedded-core count or board power. Its 800G label therefore remains a family-level advertised rate, not an invented two-port or four-port configuration. It is also distinct from storage products that happen to reuse the SP560 identifier.",
            "2026 年 SP560 发布增加了支持灵衢、PCIe 主机连接的 800G AI 网卡。已披露的主要差异是直访加速器内存与可编程协议处理，公开活动记录没有提供完整端口映射、SerDes 数量、嵌入式核数或板卡功耗。因此，800G 保持为家族公布速率，不臆造两端口或四端口配置；也不能与恰好复用 SP560 标识的存储产品混淆。"
          ],
          "sources": [
            "E13"
          ]
        }
      ]
    },
    {
      "id": "13",
      "title": [
        "Ethernet switching, optics and KV storage",
        "以太网交换、光互联与 KV 存储"
      ],
      "blocks": [
        {
          "id": "13.switch",
          "type": "prose",
          "text": [
            "CloudEngine 16800 introduced a high-density 400GE datacenter platform in 2019; the 2023 CloudEngine 16800-X disclosure advanced the portfolio toward 800GE. Current XH16800 documentation describes a chassis fabric, cell switching, ECMP, AI ECN and PFC deadlock prevention. These functions manage congestion and forwarding across an Ethernet fabric. They should not be confused with the number of ports on one switch ASIC or with the bandwidth of a UB accelerator domain. The XH16800 document’s “evolution to 800GE” wording is retained rather than treating every listed line card as already 800GE.",
            "CloudEngine 16800 在 2019 年引入高密度 400GE 数据中心平台，2023 年 CloudEngine 16800-X 披露将产品线推进到 800GE。当前 XH16800 文档描述了机框交换结构、信元交换、ECMP、AI ECN 和 PFC 死锁预防。这些功能管理以太网中的拥塞和转发，不能与单颗交换 ASIC 的端口数或 UB 加速器域的带宽混为一谈。XH16800 资料中“演进到 800GE”的措辞予以保留，不把每款已列线卡都写成已经支持 800GE。"
          ],
          "sources": [
            "E14",
            "E15",
            "P11"
          ]
        },
        {
          "id": "13.ubg",
          "type": "prose",
          "text": [
            "The September 2026 UnifiedBus system announcement introduces a 176-port, 1.6T-per-port optical interconnect device and a UBG switch with radix up to 1,024. The first multiplication yields 281.6 Tbit/s of advertised port rate, consistent with the rounded “280T” claim; it does not define bidirectional payload switching capacity. Nor should the second number be read as 1,024 such ports on one monolithic ASIC. Cabinet, chassis, chip and network topology remain separate accounting levels.",
            "2026 年 9 月灵衢系统发布引入了 176 端口、每端口 1.6T 的光互联设备，以及 Radix 最高 1024 的 UBG 交换机。前者相乘为 281.6 Tbit/s 端口标称速率，与取整后的“280T”一致，但没有定义双向有效交换容量；后者也不能理解为一颗单片 ASIC 上有 1024 个同等速率端口。机柜、机框、芯片与网络拓扑必须分别计数。"
          ],
          "sources": [
            "E04"
          ]
        },
        {
          "id": "10.optics",
          "type": "prose",
          "text": [
            "Hi-ONE is specified at 7.2 Tbit/s per optical engine with an integrated light source. The 960E comparison replaces 48,000 conventional 800G optical modules with 5,500 engines and claims more than 550 kW of savings. This is Huawei’s topology-level comparison, not a measured per-NPU TDP improvement. NPO places optics near the package; it should not automatically be renamed co-packaged optics. The design motivation is to shorten high-speed electrical reach and reduce cabling and power while preserving a large switched domain.",
            "Hi-ONE 单光引擎标称 7.2 Tbit/s，集成光源。960E 的比较方案用 5500 个光引擎替代 48000 个传统 800G 光模块，声称节省超过 550 kW。这是华为给出的拓扑级比较，不是每颗 NPU TDP 的实测下降。NPO 将光学部件放在封装附近，不能直接改称共封装光学。其设计动机是缩短高速电信号传输距离、减少线缆与功耗，同时维持大规模交换域。"
          ],
          "sources": [
            "E03",
            "E11"
          ]
        },
        {
          "id": "13.storage",
          "type": "prose",
          "text": [
            "OceanStor M900 adds a PB-scale KV-cache tier, described by Huawei as L3.5 and reachable in one UnifiedBus hop. “L3.5” is a system-tier label, not a CPU cache level. A useful mental model is local HBM for active execution, CPU memory for larger working sets, and a shared persistent or semi-persistent KV tier for reusable context. Storage can avoid recomputation and improve capacity economics, but latency-sensitive decoding still depends on how much useful state reaches HBM on time.",
            "OceanStor M900 增加 PB 级 KV 缓存层，华为称为 L3.5，可经灵衢一跳访问。“L3.5”是系统分层名称，不是 CPU 缓存级别。可以将层次理解为：本地 HBM 服务当前计算，CPU 内存容纳更大工作集，共享持久或半持久 KV 层保存可复用上下文。存储可减少重算、改善容量成本，但时延敏感的解码仍取决于有多少有效状态能及时送入 HBM。"
          ],
          "sources": [
            "E10",
            "E11"
          ]
        }
      ]
    },
    {
      "id": "14",
      "title": [
        "System generations and deployment boundaries",
        "系统代际与部署边界"
      ],
      "blocks": [
        {
          "id": "systems",
          "type": "table",
          "table": "systems"
        },
        {
          "id": "14.deployment",
          "type": "prose",
          "text": [
            "A maximum supported cluster is not an installed cluster. The 2026 disclosures describe very large scale-out topologies, including hundreds of thousands of NPUs and a multi-rail path to one million. Their engineering significance is the hierarchy and reach of the interconnect; the report does not treat those limits as verified customer installations. Likewise, an addressable memory pool is not necessarily the sum of all physical DRAM in every node.",
            "支持的最大集群不等于已安装集群。2026 年披露描述了数十万 NPU 的横向扩展拓扑，以及通过多轨网络达到百万规模的路径。其工程意义在于互联层次与距离，本报告不把这些上限当成已经核实的客户装机。同样，可寻址内存池也不一定等于所有节点物理 DRAM 的总和。"
          ],
          "sources": [
            "E03",
            "E11",
            "E12"
          ]
        }
      ]
    },
    {
      "id": "15",
      "title": [
        "Software evolution and research feedback",
        "软件演进与研究反馈"
      ],
      "blocks": [
        {
          "id": "software",
          "type": "table",
          "table": "software"
        },
        {
          "id": "15.model",
          "type": "prose",
          "text": [
            "Ascend C exposes the machine’s memory hierarchy directly enough that kernel authors must understand tiling, buffer lifetime, queues and synchronization. The payoff is precise overlap between data movement and compute; the cost is that porting an operator may involve more than translating its arithmetic. A framework adapter alone does not guarantee equivalent scheduling, collective behavior or quantization quality. CANN, optimized kernels, HCCL-style collectives and inference-serving software have to mature together.",
            "Ascend C 暴露了较多机器存储层级，因此内核作者必须理解分块、缓冲生命周期、队列和同步。收益是可以精确重叠搬运与计算；代价是移植算子往往不仅仅是翻译算术表达式。单有框架适配层，不能保证调度、集合通信或量化质量等效。CANN、优化内核、HCCL 类集合通信和推理服务软件需要共同成熟。"
          ],
          "sources": [
            "P03",
            "P01",
            "R02",
            "P15"
          ]
        },
        {
          "id": "15.research",
          "type": "prose",
          "text": [
            "The academic record adds mechanisms rather than a second marketing timeline. ASPLOS 2025’s component roofline explains operator bottlenecks. ISCA 2026’s ENEC optimizes lossless weight compression for Ascend, including vector-friendly decoding and dependency reduction. MICRO 2025’s RICH Prefetcher explores storing richer prefetch information in memory to trade capacity and bandwidth for latency hiding. ENEC is software/research on Ascend; RICH is related CPU research. Neither establishes that a specific new decompressor or prefetcher shipped in Kunpeng or Ascend.",
            "学术记录提供机制解释，而不是另一条营销时间线。ASPLOS 2025 的组件级 Roofline 解释算子瓶颈；ISCA 2026 的 ENEC 面向昇腾优化权重无损压缩，包括适合向量执行的解码和依赖消除；MICRO 2025 的 RICH Prefetcher 研究将更丰富的预取信息存放到内存，用容量和带宽换取时延隐藏。ENEC 属于昇腾上的软件／研究，RICH 属于相关 CPU 研究，都不能证明鲲鹏或昇腾已经集成了某个新解压器或预取器。"
          ],
          "sources": [
            "R01",
            "R03",
            "R05",
            "R06"
          ]
        }
      ]
    },
    {
      "id": "16",
      "title": [
        "Bandwidth hierarchy and derived ratios",
        "带宽层级与派生指标"
      ],
      "blocks": [
        {
          "id": "bandwidth",
          "type": "table",
          "table": "bandwidth"
        },
        {
          "id": "ratios",
          "type": "table",
          "table": "ratios"
        }
      ]
    },
    {
      "id": "17",
      "title": [
        "Integrated stack across four eras",
        "四个时期的完整技术栈"
      ],
      "blocks": [
        {
          "id": "17.intro",
          "type": "prose",
          "text": [
            "The diagrams show deployment roles and traffic paths. Lines indicate connectivity, not equal bandwidth, universal coherence or simultaneous use of every optional interface. Source coverage follows the preceding family chapters.",
            "以下图示呈现部署职责和流量路径。连线表示连接关系，不代表等带宽、全域一致性，也不表示每个可选接口可以同时启用。来源与前述产品章节一致。"
          ],
          "sources": [
            "C01",
            "P01",
            "R02",
            "P15",
            "E03",
            "E11",
            "E13"
          ]
        },
        {
          "id": "era1",
          "type": "figure",
          "figure": "era1"
        },
        {
          "id": "era2",
          "type": "figure",
          "figure": "era2"
        },
        {
          "id": "era3",
          "type": "figure",
          "figure": "era3"
        },
        {
          "id": "era4",
          "type": "figure",
          "figure": "era4"
        }
      ]
    },
    {
      "id": "18",
      "title": [
        "Engineering trends and disclosure gaps",
        "工程趋势与披露缺口"
      ],
      "blocks": [
        {
          "id": "18.reuse",
          "type": "prose",
          "text": [
            "Chiplet reuse predates the current AI boom in Huawei’s portfolio. Kunpeng 920 used separate compute and I/O dies; the first 910 paired a large compute die with I/O and HBM; 950 makes the compute/I/O partition more explicit while varying its memory subsystem by workload. The benefit is modularity and the ability to optimize different die functions separately. The cost is package wiring, coherent data movement and another layer of placement sensitivity. No public source reviewed here establishes a universal 3D-stacked SRAM design across these shipping products.",
            "华为产品中的芯粒复用早于当前 AI 热潮。鲲鹏 920 分离计算与 I/O 裸片，初代 910 将大计算裸片与 I/O、HBM 组合，950 进一步明确计算／I/O 分工，并按负载配置不同内存子系统。收益是模块化与不同功能的独立优化，代价是封装布线、一致性搬运和更强的放置敏感性。已审阅公开资料没有证明这些商用产品普遍采用 3D 堆叠 SRAM。"
          ],
          "sources": [
            "P01",
            "C01",
            "P15"
          ]
        },
        {
          "id": "18.precision",
          "type": "prose",
          "text": [
            "Low precision raises compute faster than it raises the supply of useful bytes. The 950 matrix path doubles throughput from BF16 to FP8 and approximately doubles it again to MXFP4. Quantization, vector processing and data layout become increasingly important as the arithmetic gets cheaper. More HBM bandwidth helps memory-bound phases, but operator fusion and keeping intermediate data in L0/L1/Unified Buffer can remove transfers altogether. The next bottleneck may therefore be vector work, synchronization or communication rather than the Cube array.",
            "低精度提升计算的速度往往快于有效数据供给。950 矩阵路径从 BF16 到 FP8 吞吐翻倍，再到 MXFP4 约翻倍。算术变便宜后，量化、向量处理和布局的重要性上升。更多 HBM 带宽有助于内存受限阶段，而算子融合、将中间数据留在 L0／L1／Unified Buffer，则可能直接消除搬运。因此，下一个瓶颈可能是向量工作、同步或通信，而不是 Cube 阵列。"
          ],
          "sources": [
            "P15",
            "R01"
          ]
        },
        {
          "id": "16.balance",
          "type": "prose",
          "text": [
            "The PR/DT split is quantitatively meaningful. DT’s maximum matrix BF16 throughput is only about 12.5% above PR’s, but its memory bandwidth is 2.5 times as large. It therefore offers roughly 2.22 times the memory bandwidth per BF16 FLOP. That is consistent with a training/decoding branch that must sustain more movement per unit of arithmetic. It is an architectural interpretation of the disclosed ratios, not a guarantee that every decode workload runs 2.22 times faster.",
            "PR／DT 分化具有明确的量化意义。DT 最大矩阵 BF16 吞吐只比 PR 高约 12.5%，内存带宽却为其 2.5 倍，因此每 BF16 FLOP 对应的内存带宽约为 2.22 倍。这与训练／解码分支每单位算术需要更多数据搬运相吻合。这里是基于公开比例的架构解释，并不保证每种解码负载都加速 2.22 倍。"
          ],
          "sources": [
            "P15"
          ]
        },
        {
          "id": "18.scale",
          "type": "prose",
          "text": [
            "Larger scale-up domains give mixture-of-experts models more aggregate memory and more choices for expert placement. They also increase the importance of fabric bisection bandwidth, tail latency, optics reliability and failure containment. A domain of thousands of NPUs cannot be judged by multiplying chip peak alone. The strongest evidence would combine measured model throughput and latency, full system power, recovery behavior and the exact topology under the same workload. These measurements are not uniformly disclosed across Huawei’s generations.",
            "更大的纵向扩展域为混合专家模型提供更多总内存和专家放置选择，同时提高了对网络对分带宽、尾时延、光器件可靠性和故障隔离的要求。数千 NPU 的域不能仅靠芯片峰值相乘来评价。最有说服力的证据应同时提供同一负载下的模型吞吐与时延、整机功耗、恢复行为及确切拓扑；华为各代公开资料尚未均匀覆盖这些指标。"
          ],
          "sources": [
            "R02",
            "E03",
            "P15"
          ]
        },
        {
          "id": "13.tradeoff",
          "type": "prose",
          "text": [
            "The architecture gains more from avoiding unnecessary movement than from renaming all resources “memory.” Pooling expands capacity and creates another scheduler’s degree of freedom, while also introducing queueing, placement, durability and recovery concerns. Optical integration reduces electrical reach and cable burden, but requires thermal, mechanical and serviceability engineering. These are system-level trade-offs, and should be evaluated with workload traces and failure behavior rather than a single aggregate bandwidth number.",
            "这一架构的收益更多来自减少无效搬运，而不是把全部资源统称为“内存”。池化扩大容量、增加调度自由度，同时引入排队、放置、持久性和恢复问题。光集成缩短电连接距离、减少线缆负担，却需要热、机械与可维护性设计。这些都是系统级权衡，应结合工作负载轨迹和故障行为评估，而不能只看一个汇总带宽数字。"
          ],
          "sources": [
            "P15",
            "E03",
            "E11"
          ]
        },
        {
          "id": "18.implementation",
          "type": "prose",
          "text": [
            "The implementation record is asymmetric. Early Hot Chips and the Kunpeng technical paper reveal die partitioning and core details. ISSCC provides independently identifiable wireline circuit disclosures, including a Huawei 60 Gb/s PAM4 ADC-DSP transceiver, but no reviewed primary link proves that exact circuit is the SerDes in a named Kunpeng or Ascend product. Recent NPU documentation exposes programming and memory mechanisms well, while foundry nodes, yield, package capacity, transistor counts and many power figures remain undisclosed. Manufacturing constraints should therefore be discussed as constraints, not filled with unattributed die-analysis claims.",
            "实现资料的公开程度并不均衡。早期 Hot Chips 和鲲鹏技术论文披露了裸片划分、核心细节；ISSCC 则有可明确识别的高速有线电路论文，包括华为 60 Gb/s PAM4 ADC-DSP 收发器，但已审阅一手资料没有证明该电路就是某款鲲鹏或昇腾的 SerDes。近期 NPU 文档较充分地公开编程与内存机制，制造节点、良率、封装产能、晶体管数和许多功耗指标仍未公开。因此，制造限制应作为限制来讨论，不能用未注明来源的拆解传言填空。"
          ],
          "sources": [
            "C01",
            "P01",
            "C05",
            "P15"
          ]
        },
        {
          "id": "18.openness",
          "type": "prose",
          "text": [
            "Opening software and publishing a protocol can broaden adoption, but ecosystem compatibility remains an engineering property. Kernel coverage, compiler quality, collective behavior, device management and the licensing/implementation status of an interconnect all matter. Huawei’s combination of CANN, its own system fabric, cloud services and partner boards supplies an increasingly complete stack. Its differentiation is the coordination of these layers; the unresolved comparison is how much useful workload performance and operational resilience that coordination delivers per unit of cost and power.",
            "开放软件与发布协议有助于扩大采用，但生态兼容性仍是工程属性，取决于内核覆盖、编译质量、集合通信行为、设备管理，以及互联协议的许可与实现状态。CANN、自有系统互联、云服务和合作伙伴主板使华为形成越来越完整的技术栈。差异化在于这些层次的协同；仍需进一步比较的是，协同最终能以多少成本和功耗换取有效负载性能与运行韧性。"
          ],
          "sources": [
            "E09",
            "E17",
            "P08",
            "P15",
            "E12"
          ]
        }
      ]
    },
    {
      "id": "19",
      "title": [
        "Conference-to-product index",
        "会议与产品对应索引"
      ],
      "blocks": [
        {
          "id": "conferences",
          "type": "table",
          "table": "conferences"
        },
        {
          "id": "19.coverage",
          "type": "prose",
          "text": [
            "The index is a verified conference-to-product map, not a claim to enumerate every Huawei-affiliated publication. No reviewed primary disclosure establishes a generation-by-generation Kunpeng/Ascend product paper at DAC, VLSI, IEDM, ECTC, OFC, SC or ISC. Likewise, Computex, OCP, GTC, re:Invent, Ignite and Google Cloud Next are not automatically Huawei product disclosure channels. They remain search targets rather than invented entries. MWC, WAIC, HUAWEI CONNECT and Huawei’s developer events have direct, useful records for this portfolio.",
            "该索引是经过核验的会议—产品映射，不声称穷尽所有华为作者论文。已审阅一手资料没有建立 DAC、VLSI、IEDM、ECTC、OFC、SC、ISC 上按代际连续披露鲲鹏／昇腾产品的记录。同样，Computex、OCP、GTC、re:Invent、Ignite、Google Cloud Next 也不能自动视为华为产品披露渠道；它们仍是检索目标，而不是凭空填入的条目。MWC、WAIC、华为全联接大会和开发者活动，则有直接且有用的产品记录。"
          ],
          "sources": [
            "C01",
            "C05",
            "R03",
            "R06",
            "E05",
            "E18",
            "E01"
          ]
        }
      ]
    },
    {
      "id": "20",
      "title": [
        "Names, reuse and items that must not be merged",
        "名称、复用与不能合并的项目"
      ],
      "blocks": [
        {
          "id": "crosswalk",
          "type": "table",
          "table": "crosswalk"
        }
      ]
    }
  ],
  "tables": {
    "headline": {
      "id": "headline",
      "title": [
        "Flagship milestones and comparable quantities",
        "旗舰里程碑与可比指标"
      ],
      "headers": [
        [
          "Milestone",
          "里程碑"
        ],
        [
          "CPU / memory",
          "CPU／内存"
        ],
        [
          "Accelerator matrix BF16 / FP8",
          "加速器矩阵 BF16／FP8"
        ],
        [
          "Accelerator memory",
          "加速器内存"
        ],
        [
          "Scale-up scope",
          "纵向扩展范围"
        ]
      ],
      "rows": [
        {
          "id": "2019",
          "values": [
            [
              "2019",
              "2019"
            ],
            [
              "Kunpeng 920: 64 cores; 187.7 GB/s DDR4",
              "鲲鹏 920：64 核；DDR4 187.7 GB/s"
            ],
            [
              "Ascend 910: BF16 n/d; FP16 256 TFLOPS",
              "昇腾 910：BF16 n/d；FP16 256 TFLOPS"
            ],
            [
              "4 HBM2 stacks; ~1.2 TB/s",
              "4 个 HBM2 堆栈；约 1.2 TB/s"
            ],
            [
              "HCCS-connected accelerator nodes",
              "HCCS 加速器节点"
            ]
          ],
          "sources": [
            "P01",
            "C01"
          ]
        },
        {
          "id": "2025",
          "values": [
            [
              "2025",
              "2025"
            ],
            [
              "CloudMatrix384: 192 Kunpeng CPUs",
              "CloudMatrix384：192 颗鲲鹏 CPU"
            ],
            [
              "910C reference: BF16 supported; peak n/d in reviewed system paper",
              "910C 参考：支持 BF16；已审阅系统论文未给峰值"
            ],
            [
              "2 compute dies, 8 memory stacks per NPU",
              "每 NPU：2 颗计算裸片、8 个内存堆栈"
            ],
            [
              "384 NPUs",
              "384 NPUs"
            ]
          ],
          "sources": [
            "R02",
            "E02"
          ]
        },
        {
          "id": "950pr",
          "values": [
            [
              "950PR",
              "950PR"
            ],
            [
              "8C/16T Linx816 on maximum NPU configuration",
              "NPU 最大配置集成 8 核／16 线程 Linx816"
            ],
            [
              "432 / 865 TFLOPS",
              "432 / 865 TFLOPS"
            ],
            [
              "128 GB; 1.6 TB/s maximum",
              "最高 128 GB；1.6 TB/s"
            ],
            [
              "8,192 architectural domain; products vary",
              "架构域支持 8192 卡；产品配置不同"
            ]
          ],
          "sources": [
            "P15"
          ]
        },
        {
          "id": "950dt",
          "values": [
            [
              "950DT",
              "950DT"
            ],
            [
              "Host Kunpeng 950: 64/96-core server configurations",
              "主机鲲鹏 950：64／96 核服务器配置"
            ],
            [
              "486 / 973 TFLOPS",
              "486 / 973 TFLOPS"
            ],
            [
              "144 GB; 4 TB/s",
              "144 GB; 4 TB/s"
            ],
            [
              "8,192 architectural domain; products vary",
              "架构域支持 8192 卡；产品配置不同"
            ]
          ],
          "sources": [
            "P15",
            "P08"
          ]
        },
        {
          "id": "960",
          "values": [
            [
              "960 / 960E",
              "960 / 960E"
            ],
            [
              "Kunpeng memory pools accompany NPU domains",
              "鲲鹏内存池与 NPU 域协同"
            ],
            [
              "8 EFLOPS FP8 per announced 960E system",
              "已公布 960E 系统：FP8 8 EFLOPS"
            ],
            [
              "Up to 1 PB per system",
              "每系统最高 1 PB"
            ],
            [
              "4,096 NPUs",
              "4,096 NPUs"
            ]
          ],
          "sources": [
            "E03",
            "E11"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3,
          4
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "cpu": {
      "id": "cpu",
      "title": [
        "Kunpeng: reference configurations and disclosure boundaries",
        "鲲鹏：参考配置与披露边界"
      ],
      "headers": [
        [
          "Generation / reference SKU",
          "代际／参考 SKU"
        ],
        [
          "Codename",
          "代号"
        ],
        [
          "GA",
          "正式商用"
        ],
        [
          "Status",
          "状态"
        ],
        [
          "Core µarch",
          "核心微架构"
        ],
        [
          "Cores / threads",
          "核心／线程"
        ],
        [
          "Process per die",
          "各裸片工艺"
        ],
        [
          "Dies / packaging",
          "裸片／封装"
        ],
        [
          "L2 per core",
          "每核 L2"
        ],
        [
          "L3 / domain",
          "L3／共享域"
        ],
        [
          "Memory: channels; rate; GB/s",
          "内存：通道；速率；GB/s"
        ],
        [
          "Sockets / links",
          "插槽／互联"
        ],
        [
          "PCIe / CXL",
          "PCIe／CXL"
        ],
        [
          "TDP",
          "TDP"
        ],
        [
          "Vector / matrix ISA",
          "向量／矩阵 ISA"
        ]
      ],
      "rows": [
        {
          "id": "early",
          "values": [
            [
              "Hi1610 / Hi1612 baseline",
              "Hi1610／Hi1612 基线"
            ],
            [
              "Hi1610 / Hi1612",
              "Hi1610 / Hi1612"
            ],
            [
              "2015 driver record; GA n/d",
              "2015 年驱动记录；GA n/d"
            ],
            [
              "Historical shipping",
              "历史已商用"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ]
          ],
          "sources": [
            "R07"
          ]
        },
        {
          "id": "916",
          "values": [
            [
              "Kunpeng 916",
              "Kunpeng 916"
            ],
            [
              "Hi1616",
              "Hi1616"
            ],
            [
              "Pre-2019 generation",
              "2019 年以前代际"
            ],
            [
              "Historical shipping",
              "历史已商用"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "32 / 32",
              "32 / 32"
            ],
            [
              "16 nm",
              "16 nm"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "DDR4; 4 channels; 2400 MT/s; 76.8 GB/s",
              "DDR4；4 通道；2400 MT/s；76.8 GB/s"
            ],
            [
              "2P boards",
              "双路主板"
            ],
            [
              "PCIe 3.0; CXL n/a",
              "PCIe 3.0; CXL n/a"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Arm NEON",
              "Arm NEON"
            ]
          ],
          "sources": [
            "C03",
            "P10",
            "P16"
          ]
        },
        {
          "id": "920",
          "values": [
            [
              "Kunpeng 920",
              "Kunpeng 920"
            ],
            [
              "Hi1620",
              "Hi1620"
            ],
            [
              "2019",
              "2019"
            ],
            [
              "Historical shipping",
              "历史已商用"
            ],
            [
              "TaiShan V110",
              "TaiShan V110"
            ],
            [
              "64 / 64",
              "64 / 64"
            ],
            [
              "Compute 7 nm; I/O 16 nm",
              "计算 7 nm；I/O 16 nm"
            ],
            [
              "2 compute + 1 I/O; CoWoS reference",
              "2 计算＋1 I/O；CoWoS 参考实现"
            ],
            [
              "512 KiB",
              "512 KiB"
            ],
            [
              "64 MB; sliced, ~1 MB/core",
              "64 MB；分片，约 1 MB／核"
            ],
            [
              "DDR4; 8 channels; 2933 MT/s; 187.7 GB/s",
              "DDR4；8 通道；2933 MT/s；187.7 GB/s"
            ],
            [
              "2P / 4P; HCCS",
              "双路／四路；HCCS"
            ],
            [
              "PCIe 4.0 ×40; CXL n/a",
              "PCIe 4.0 ×40; CXL n/a"
            ],
            [
              "200 W paper reference",
              "论文参考配置 200 W"
            ],
            [
              "128-bit NEON",
              "128-bit NEON"
            ]
          ],
          "sources": [
            "P01",
            "C03",
            "P13"
          ]
        },
        {
          "id": "920new",
          "values": [
            [
              "Kunpeng 920 new models",
              "鲲鹏 920 新型号"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Current motherboard portfolio; GA n/d",
              "当前主板产品线；GA n/d"
            ],
            [
              "Shipping / available",
              "已商用／可获取"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "SMT2; SKU core count n/d here",
              "SMT2；此处 SKU 核数 n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "DDR5; channels / bandwidth n/d",
              "DDR5；通道／带宽 n/d"
            ],
            [
              "2P / 4P boards",
              "双路／四路主板"
            ],
            [
              "PCIe 5.0; CXL n/d",
              "PCIe 5.0; CXL n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ]
          ],
          "sources": [
            "P09"
          ]
        },
        {
          "id": "950",
          "values": [
            [
              "Kunpeng 950",
              "Kunpeng 950"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "2026 H1 server brief",
              "2026 上半年服务器资料"
            ],
            [
              "Shipping / available",
              "已商用／可获取"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "64 / 96 cores per socket; SMT2",
              "每插槽 64／96 核；SMT2"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "DDR5 RDIMM 7200 / MRDIMM 8800; channels n/d",
              "DDR5 RDIMM 7200／MRDIMM 8800；通道 n/d"
            ],
            [
              "2P reference board",
              "双路参考主板"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ]
          ],
          "sources": [
            "P08",
            "E02"
          ]
        },
        {
          "id": "950max",
          "values": [
            [
              "Kunpeng 950 larger configuration",
              "鲲鹏 950 更高配置"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "2025 roadmap; GA n/d",
              "2025 年路线图；GA n/d"
            ],
            [
              "Roadmap",
              "路线图"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "192 / 384",
              "192 / 384"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ]
          ],
          "sources": [
            "E02"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3,
          4,
          5
        ],
        [
          0,
          6,
          7,
          8,
          9
        ],
        [
          0,
          10,
          11,
          12,
          13,
          14
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "accelerator": {
      "id": "accelerator",
      "title": [
        "Ascend NPUs: chip and card scopes are explicit",
        "昇腾 NPU：明确芯片与加速卡口径"
      ],
      "headers": [
        [
          "Product",
          "产品"
        ],
        [
          "Architecture",
          "架构"
        ],
        [
          "GA / milestone",
          "商用／里程碑"
        ],
        [
          "Status",
          "状态"
        ],
        [
          "Process",
          "工艺"
        ],
        [
          "Dies / packaging",
          "裸片／封装"
        ],
        [
          "Compute units",
          "计算单元"
        ],
        [
          "Dense BF16",
          "稠密 BF16"
        ],
        [
          "Dense FP8",
          "稠密 FP8"
        ],
        [
          "Dense FP6 / FP4",
          "稠密 FP6／FP4"
        ],
        [
          "FP64 vector / matrix",
          "FP64 向量／矩阵"
        ],
        [
          "Memory: type; stacks; GB; TB/s",
          "内存：类型；堆栈；GB；TB/s"
        ],
        [
          "LLC / SRAM",
          "末级缓存／SRAM"
        ],
        [
          "Scale-up: links; GB/s per direction; domain",
          "纵向扩展：链路；单向 GB/s；域"
        ],
        [
          "Host link",
          "主机连接"
        ],
        [
          "Power / cooling",
          "功耗／散热"
        ],
        [
          "Form factor",
          "形态"
        ]
      ],
      "rows": [
        {
          "id": "310",
          "values": [
            [
              "Ascend 310",
              "Ascend 310"
            ],
            [
              "DaVinci",
              "DaVinci"
            ],
            [
              "2018",
              "2018"
            ],
            [
              "Historical shipping",
              "历史已商用"
            ],
            [
              "12 nm",
              "12 nm"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "2 AI cores",
              "2 个 AI 核"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "External LPDDR; board-dependent",
              "外部 LPDDR；依板卡"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "PCIe",
              "PCIe"
            ],
            [
              "8 W chip",
              "芯片 8 W"
            ],
            [
              "Chip / Atlas modules",
              "芯片／Atlas 模组"
            ]
          ],
          "sources": [
            "C01",
            "P01",
            "E07"
          ]
        },
        {
          "id": "910",
          "values": [
            [
              "Ascend 910",
              "Ascend 910"
            ],
            [
              "DaVinci",
              "DaVinci"
            ],
            [
              "2019",
              "2019"
            ],
            [
              "Historical shipping",
              "历史已商用"
            ],
            [
              "Compute N7+; other die nodes n/d",
              "计算裸片 N7+；其他裸片工艺 n/d"
            ],
            [
              "Compute + Nimbus I/O + 4 HBM2 + dummy dies",
              "计算＋Nimbus I/O＋4 HBM2＋填充裸片"
            ],
            [
              "32 AI cores",
              "32 个 AI 核"
            ],
            [
              "n/d; FP16 256 TFLOPS",
              "n/d；FP16 256 TFLOPS"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "HBM2; 4 stacks; capacity SKU-dependent; ~1.2 TB/s",
              "HBM2；4 堆栈；容量依 SKU；约 1.2 TB/s"
            ],
            [
              "L2 fabric 4 TB/s in HC talk",
              "HC 演讲：L2 互联 4 TB/s"
            ],
            [
              "3 × 240 Gb/s HCCS; direction n/d",
              "3×240 Gb/s HCCS；方向 n/d"
            ],
            [
              "PCIe 4.0",
              "PCIe 4.0"
            ],
            [
              "350 W HC target; launch 310 W",
              "HC 目标 350 W；发布值 310 W"
            ],
            [
              "Atlas accelerator / server",
              "Atlas 加速器／服务器"
            ]
          ],
          "sources": [
            "C01",
            "P01",
            "E20"
          ]
        },
        {
          "id": "310p",
          "values": [
            [
              "Ascend 310P",
              "Ascend 310P"
            ],
            [
              "Inference branch",
              "推理分支"
            ],
            [
              "Atlas 300I Pro / Duo generation",
              "Atlas 300I Pro／Duo 代际"
            ],
            [
              "Historical shipping",
              "历史已商用"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "LPDDR; configuration-dependent",
              "LPDDR；依配置"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "PCIe",
              "PCIe"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Inference cards / edge systems",
              "推理卡／边缘系统"
            ]
          ],
          "sources": [
            "P12"
          ]
        },
        {
          "id": "910b",
          "values": [
            [
              "Ascend 910B2 / A2",
              "Ascend 910B2 / A2"
            ],
            [
              "DaVinci",
              "DaVinci"
            ],
            [
              "2023-era A2 systems",
              "2023 年前后 A2 系统"
            ],
            [
              "Historical shipping",
              "历史已商用"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "24 AIC + 48 AIV",
              "24 AIC + 48 AIV"
            ],
            [
              "Supported; SKU peak n/d",
              "支持；SKU 峰值 n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "64 GB HBM in ENEC 910B2 test system; rate n/d",
              "ENEC 的 910B2 测试系统为 64 GB HBM；速率 n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "HCCS; configuration-dependent",
              "HCCS；依配置"
            ],
            [
              "PCIe",
              "PCIe"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Atlas A2 servers / modules",
              "Atlas A2 服务器／模组"
            ]
          ],
          "sources": [
            "P12",
            "R01",
            "R05"
          ]
        },
        {
          "id": "910c",
          "values": [
            [
              "Ascend 910C / A3",
              "Ascend 910C / A3"
            ],
            [
              "DaVinci",
              "DaVinci"
            ],
            [
              "2025-03",
              "2025-03"
            ],
            [
              "Shipping / available",
              "已商用／可获取"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "2 compute dies; 8 memory stacks",
              "2 计算裸片；8 内存堆栈"
            ],
            [
              "48 AIC + 96 AIV",
              "48 AIC + 96 AIV"
            ],
            [
              "Supported; peak n/d in R02",
              "支持；R02 未给峰值"
            ],
            [
              "INT8 path; native FP8 not established",
              "INT8 路径；原生 FP8 未确定"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "8 stacks; capacity / rate n/d in R02",
              "8 堆栈；R02 未给容量／速率"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "7 UB transceivers per die; 384-NPU domain",
              "每裸片 7 个 UB 收发器；384 NPU 域"
            ],
            [
              "Kunpeng / UB system",
              "鲲鹏／UB 系统"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Atlas 900 A3 / CloudMatrix384",
              "Atlas 900 A3／CloudMatrix384"
            ]
          ],
          "sources": [
            "R02",
            "E02"
          ]
        },
        {
          "id": "950pr",
          "values": [
            [
              "Ascend 950PR",
              "Ascend 950PR"
            ],
            [
              "DaVinci 3",
              "DaVinci 3"
            ],
            [
              "2026; Atlas 350 product",
              "2026；Atlas 350 产品"
            ],
            [
              "Shipping / available",
              "已商用／可获取"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "2 AI + 2 I/O dies; 8 memory modules",
              "2 AI＋2 I/O 裸片；8 内存模组"
            ],
            [
              "32 AIC + 64 AIV",
              "32 AIC + 64 AIV"
            ],
            [
              "432 TFLOPS",
              "432 TFLOPS"
            ],
            [
              "865 TFLOPS",
              "865 TFLOPS"
            ],
            [
              "MXFP4 1730 TFLOPS; FP6 n/d",
              "MXFP4 1730 TFLOPS；FP6 n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "128 GB; 1.6 TB/s; stack generation n/d",
              "128 GB；1.6 TB/s；堆栈代际 n/d"
            ],
            [
              "128 MB",
              "128 MB"
            ],
            [
              "18 ×4 ports; 56 GB/s raw/link/direction; 1008 GB/s total/direction before port reuse",
              "18 个 ×4 端口；每链路原始单向 56 GB/s；复用前单向合计 1008 GB/s"
            ],
            [
              "PCIe 5.0 ×16",
              "PCIe 5.0 ×16"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Chip; several bins",
              "芯片；多种配置"
            ]
          ],
          "sources": [
            "P15",
            "P14"
          ]
        },
        {
          "id": "350",
          "values": [
            [
              "Atlas 350",
              "Atlas 350"
            ],
            [
              "950PR / DaVinci 3",
              "950PR / DaVinci 3"
            ],
            [
              "2026 product listing",
              "2026 年产品目录"
            ],
            [
              "Shipping / available",
              "已商用／可获取"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "950PR card configuration",
              "950PR 加速卡配置"
            ],
            [
              "28 AIC + 56 AIV",
              "28 AIC + 56 AIV"
            ],
            [
              "378 TFLOPS",
              "378 TFLOPS"
            ],
            [
              "756 TFLOPS",
              "756 TFLOPS"
            ],
            [
              "MXFP4 1513 TFLOPS",
              "MXFP4 1513 TFLOPS"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "112 GB HBM; 1.4 TB/s",
              "112 GB HBM; 1.4 TB/s"
            ],
            [
              "112 MB",
              "112 MB"
            ],
            [
              "4 cards: 159 GB/s/direction/card; 2 cards: 212 GB/s/direction/card",
              "4 卡：每卡单向 159 GB/s；2 卡：每卡单向 212 GB/s"
            ],
            [
              "PCIe 5.0 ×16",
              "PCIe 5.0 ×16"
            ],
            [
              "≤600 W; passive heatsink",
              "≤600 W；被动散热"
            ],
            [
              "PCIe OH FL DW",
              "PCIe OH FL DW"
            ]
          ],
          "sources": [
            "P14",
            "P15"
          ]
        },
        {
          "id": "950dt",
          "values": [
            [
              "Ascend 950DT",
              "Ascend 950DT"
            ],
            [
              "DaVinci 3",
              "DaVinci 3"
            ],
            [
              "2026 systems listed; earlier Q4 target",
              "2026 已列系统；早期目标 Q4"
            ],
            [
              "Product-listed; chip GA date n/d",
              "已列产品；芯片 GA 日期 n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "2 AI + 2 I/O dies; 4 memory modules",
              "2 AI＋2 I/O 裸片；4 内存模组"
            ],
            [
              "36 AIC + 72 AIV",
              "36 AIC + 72 AIV"
            ],
            [
              "486 TFLOPS",
              "486 TFLOPS"
            ],
            [
              "973 TFLOPS",
              "973 TFLOPS"
            ],
            [
              "MXFP4 1946 TFLOPS",
              "MXFP4 1946 TFLOPS"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "144 GB max; 4 TB/s; 96 GB variant",
              "最高 144 GB；4 TB/s；另有 96 GB 配置"
            ],
            [
              "128 MB",
              "128 MB"
            ],
            [
              "18 ×4 ports; 56 GB/s raw/link/direction; 1008 GB/s total/direction before port reuse",
              "18 个 ×4 端口；每链路原始单向 56 GB/s；复用前单向合计 1008 GB/s"
            ],
            [
              "PCIe 5.0 ×16",
              "PCIe 5.0 ×16"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Chip; several bins",
              "芯片；多种配置"
            ]
          ],
          "sources": [
            "P15",
            "P12",
            "E18",
            "E02"
          ]
        },
        {
          "id": "960",
          "values": [
            [
              "Ascend 960DT / PR",
              "Ascend 960DT / PR"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "DT Q1 2027; PR Q3 2027 readiness",
              "DT 2027 Q1；PR 2027 Q3 就绪"
            ],
            [
              "Roadmap",
              "路线图"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Future chips; Atlas 960E system announced",
              "未来芯片；Atlas 960E 系统已发布"
            ]
          ],
          "sources": [
            "E11",
            "E03"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3,
          4,
          5,
          6
        ],
        [
          0,
          7,
          8,
          9,
          10,
          11,
          12
        ],
        [
          0,
          13,
          14,
          15,
          16
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "interconnect": {
      "id": "interconnect",
      "title": [
        "Interconnect lineage and normalized directions",
        "互联谱系与带宽方向归一化"
      ],
      "headers": [
        [
          "Interconnect",
          "互联"
        ],
        [
          "Year / generation",
          "年份／代际"
        ],
        [
          "Lane rate",
          "通道速率"
        ],
        [
          "Lanes / link",
          "每链路通道"
        ],
        [
          "GB/s per link per direction",
          "每链路单向 GB/s"
        ],
        [
          "Links / device",
          "每设备链路"
        ],
        [
          "Topology",
          "拓扑"
        ],
        [
          "Domain limit",
          "域规模"
        ],
        [
          "Coherence / semantics",
          "一致性／语义"
        ]
      ],
      "rows": [
        {
          "id": "kpdd",
          "values": [
            [
              "Kunpeng 920 D2D",
              "Kunpeng 920 D2D"
            ],
            [
              "2019",
              "2019"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "400 GB/s quoted aggregate; direction n/d",
              "公布合计 400 GB/s；方向 n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Compute / I/O chiplet links",
              "计算／I/O 芯粒连接"
            ],
            [
              "Processor package",
              "处理器封装"
            ],
            [
              "Coherent on-package fabric",
              "封装内一致性互联"
            ]
          ],
          "sources": [
            "P01"
          ]
        },
        {
          "id": "hccs",
          "values": [
            [
              "Ascend 910 HCCS",
              "Ascend 910 HCCS"
            ],
            [
              "2019",
              "2019"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "240 Gb/s = 30 GB/s quoted link; direction n/d",
              "每链路公布 240 Gb/s＝30 GB/s；方向 n/d"
            ],
            [
              "3",
              "3"
            ],
            [
              "Board/system dependent",
              "依板卡／系统"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Accelerator communication; do not assume general CPU coherence",
              "加速器通信；不推定通用 CPU 一致性"
            ]
          ],
          "sources": [
            "C01"
          ]
        },
        {
          "id": "ub1",
          "values": [
            [
              "UnifiedBus 1.0",
              "UnifiedBus 1.0"
            ],
            [
              "2025",
              "2025"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "7 transceivers per 910C die",
              "每 910C 裸片 7 收发器"
            ],
            [
              "Two-tier switched; 7 subplanes",
              "两级交换；7 子平面"
            ],
            [
              "384 NPUs",
              "384 NPUs"
            ],
            [
              "Peer access; pooled CPU/NPU memory",
              "对等访问；CPU／NPU 内存池"
            ]
          ],
          "sources": [
            "R02",
            "E02"
          ]
        },
        {
          "id": "ub2",
          "values": [
            [
              "UnifiedBus 2.0 / 950",
              "UnifiedBus 2.0 / 950"
            ],
            [
              "2026",
              "2026"
            ],
            [
              "112 Gb/s",
              "112 Gb/s"
            ],
            [
              "4",
              "4"
            ],
            [
              "56 raw; 1008 aggregate/device",
              "原始 56；每设备合计 1008"
            ],
            [
              "18",
              "18"
            ],
            [
              "nD mesh / Clos",
              "n 维网格／Clos"
            ],
            [
              "8,192 NPUs",
              "8,192 NPUs"
            ],
            [
              "URMA; load/store/atomic; on-package coherence separately documented",
              "URMA；load/store/atomic；封装内一致性另有说明"
            ]
          ],
          "sources": [
            "P15"
          ]
        },
        {
          "id": "350link",
          "values": [
            [
              "Atlas 350 UB",
              "Atlas 350 UB"
            ],
            [
              "2026",
              "2026"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "4",
              "4"
            ],
            [
              "53 from card bidirectional rating",
              "按板卡双向值换算为 53"
            ],
            [
              "3 in 4-card mesh; 4 in 2-card mode",
              "四卡网格用 3；双卡模式用 4"
            ],
            [
              "Full mesh / paired",
              "全互连／双卡"
            ],
            [
              "4 / 2 cards",
              "4 / 2 cards"
            ],
            [
              "Card UB links",
              "板级 UB 链路"
            ]
          ],
          "sources": [
            "P14"
          ]
        },
        {
          "id": "uboe",
          "values": [
            [
              "950 UBoE",
              "950 UBoE"
            ],
            [
              "2026",
              "2026"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "50 raw per 400G port",
              "每 400G 端口原始 50"
            ],
            [
              "2",
              "2"
            ],
            [
              "Ethernet fabric",
              "以太网互联"
            ],
            [
              "Cluster architecture >128K cards",
              "集群架构超过 128K 卡"
            ],
            [
              "UB over Ethernet; consumes shared ports",
              "以太网承载 UB；占用复用端口"
            ]
          ],
          "sources": [
            "P15"
          ]
        },
        {
          "id": "optical",
          "values": [
            [
              "2026 UB optical device",
              "2026 UB optical device"
            ],
            [
              "2026",
              "2026"
            ],
            [
              "1.6 Tb/s per port",
              "1.6 Tb/s per port"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "200 raw/port; direction basis of 280T total unspecified",
              "每端口原始 200；280T 合计方向口径未给"
            ],
            [
              "176",
              "176"
            ],
            [
              "Inter-cabinet optical fabric",
              "跨柜光互联"
            ],
            [
              "System-dependent",
              "依系统"
            ],
            [
              "UnifiedBus; advertised RTT 2 µs",
              "灵衢；公布 RTT 2 µs"
            ]
          ],
          "sources": [
            "E04"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3,
          4
        ],
        [
          0,
          5,
          6,
          7,
          8
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "network": {
      "id": "network",
      "title": [
        "Network products and infrastructure offload",
        "网络产品与基础设施卸载"
      ],
      "headers": [
        [
          "Product",
          "产品"
        ],
        [
          "GA / milestone",
          "商用／里程碑"
        ],
        [
          "Status",
          "状态"
        ],
        [
          "Class",
          "类别"
        ],
        [
          "Ports × speed",
          "端口×速率"
        ],
        [
          "SerDes",
          "SerDes"
        ],
        [
          "Host interface",
          "主机接口"
        ],
        [
          "Programmable engine",
          "可编程引擎"
        ],
        [
          "Embedded CPU",
          "嵌入式 CPU"
        ],
        [
          "On-card memory",
          "板载内存"
        ],
        [
          "Transport / RDMA",
          "传输／RDMA"
        ],
        [
          "Congestion control",
          "拥塞控制"
        ],
        [
          "Key offloads",
          "主要卸载"
        ],
        [
          "Power",
          "功耗"
        ]
      ],
      "rows": [
        {
          "id": "sp681",
          "values": [
            [
              "SP681",
              "SP681"
            ],
            [
              "Current portfolio; GA n/d",
              "当前产品线；GA n/d"
            ],
            [
              "Shipping / available",
              "已商用／可获取"
            ],
            [
              "NIC",
              "NIC"
            ],
            [
              "2 ×25GE",
              "2 ×25GE"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "PCIe 3.0 ×8",
              "PCIe 3.0 ×8"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "RoCE v2",
              "RoCE v2"
            ],
            [
              "PFC / ETS",
              "PFC / ETS"
            ],
            [
              "Checksum; virtualization; network offload",
              "校验和；虚拟化；网络卸载"
            ],
            [
              "n/d",
              "n/d"
            ]
          ],
          "sources": [
            "P06"
          ]
        },
        {
          "id": "sp670",
          "values": [
            [
              "SP670",
              "SP670"
            ],
            [
              "Current portfolio; GA n/d",
              "当前产品线；GA n/d"
            ],
            [
              "Shipping / available",
              "已商用／可获取"
            ],
            [
              "NIC",
              "NIC"
            ],
            [
              "2 ×100GE",
              "2 ×100GE"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "PCIe 4.0 ×16",
              "PCIe 4.0 ×16"
            ],
            [
              "Hi1822; engine ISA n/d",
              "Hi1822；引擎 ISA n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "RoCE v2",
              "RoCE v2"
            ],
            [
              "PFC / ETS",
              "PFC / ETS"
            ],
            [
              "Virtualization and network offload",
              "虚拟化与网络卸载"
            ],
            [
              "n/d",
              "n/d"
            ]
          ],
          "sources": [
            "P06"
          ]
        },
        {
          "id": "sp680",
          "values": [
            [
              "SP680 / SP623Q",
              "SP680 / SP623Q"
            ],
            [
              "Current portfolio; GA n/d",
              "当前产品线；GA n/d"
            ],
            [
              "Shipping / available",
              "已商用／可获取"
            ],
            [
              "NIC / SmartNIC",
              "网卡／智能网卡"
            ],
            [
              "4 ×25GE",
              "4 ×25GE"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "PCIe 4.0 ×16",
              "PCIe 4.0 ×16"
            ],
            [
              "Hi1822; DPU Solution ecosystem",
              "Hi1822；DPU Solution 生态"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Ethernet; RoCE depends on model",
              "以太网；RoCE 依型号"
            ],
            [
              "PFC / ETS",
              "PFC / ETS"
            ],
            [
              "OVS / DPI / virtualization ecosystem",
              "OVS／DPI／虚拟化生态"
            ],
            [
              "n/d",
              "n/d"
            ]
          ],
          "sources": [
            "P06"
          ]
        },
        {
          "id": "sp923",
          "values": [
            [
              "SP923Q / SP900",
              "SP923Q / SP900"
            ],
            [
              "Current product brief; GA n/d",
              "当前产品资料；GA n/d"
            ],
            [
              "Shipping / available",
              "已商用／可获取"
            ],
            [
              "DPU",
              "DPU"
            ],
            [
              "4 ×25GE",
              "4 ×25GE"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "PCIe 4.0 ×16",
              "PCIe 4.0 ×16"
            ],
            [
              "DPAK",
              "DPAK"
            ],
            [
              "Hi1822; 24 cores",
              "Hi1822; 24 cores"
            ],
            [
              "32 GB DDR4-2400; 4 channels",
              "32 GB DDR4-2400; 4 channels"
            ],
            [
              "Ethernet; storage/network offload",
              "以太网；存储／网络卸载"
            ],
            [
              "PFC / ETS",
              "PFC / ETS"
            ],
            [
              "Bare-metal network/storage; management",
              "裸金属网络／存储；管理"
            ],
            [
              "n/d",
              "n/d"
            ]
          ],
          "sources": [
            "P04",
            "P05"
          ]
        },
        {
          "id": "qingtian",
          "values": [
            [
              "QingTian card",
              "擎天卡"
            ],
            [
              "2025 documented system",
              "2025 年系统披露"
            ],
            [
              "Shipping / available",
              "已商用／可获取"
            ],
            [
              "Cloud infrastructure DPU",
              "云基础设施 DPU"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "VPC / Ethernet; UB integration by platform",
              "VPC／以太网；UB 集成依平台"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Virtualization, I/O offload, isolation, trust",
              "虚拟化、I/O 卸载、隔离、可信"
            ],
            [
              "n/d",
              "n/d"
            ]
          ],
          "sources": [
            "P07",
            "R02"
          ]
        },
        {
          "id": "sp230",
          "values": [
            [
              "SP230",
              "SP230"
            ],
            [
              "WAIC 2026",
              "WAIC 2026"
            ],
            [
              "Announced; GA n/d",
              "已公布；GA n/d"
            ],
            [
              "Standard NIC",
              "标准网卡"
            ],
            [
              "25–200GE family; port count n/d",
              "25—200GE 家族；端口数 n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Ethernet",
              "Ethernet"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Host networking",
              "主机网络"
            ],
            [
              "n/d",
              "n/d"
            ]
          ],
          "sources": [
            "E13"
          ]
        },
        {
          "id": "sp560",
          "values": [
            [
              "SP560 AI NIC",
              "SP560 AI NIC"
            ],
            [
              "WAIC 2026",
              "WAIC 2026"
            ],
            [
              "Announced; GA n/d",
              "已公布；GA n/d"
            ],
            [
              "AI NIC",
              "AI 网卡"
            ],
            [
              "800G advertised; port mapping n/d",
              "公布 800G；端口映射 n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "UnifiedBus + PCIe",
              "UnifiedBus + PCIe"
            ],
            [
              "Programmable protocol; ISA n/d",
              "协议可编程；ISA n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "RDMA",
              "RDMA"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Direct NPU/GPU memory access; collective submission",
              "直访 NPU／GPU 内存；集合通信聚合下发"
            ],
            [
              "n/d",
              "n/d"
            ]
          ],
          "sources": [
            "E13"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3,
          4,
          5
        ],
        [
          0,
          6,
          7,
          8,
          9
        ],
        [
          0,
          10,
          11,
          12,
          13
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "systems": {
      "id": "systems",
      "title": [
        "From server nodes to SuperPoD and SuperCluster",
        "从服务器节点到 SuperPoD、SuperCluster"
      ],
      "headers": [
        [
          "Platform",
          "平台"
        ],
        [
          "Year / milestone",
          "年份／里程碑"
        ],
        [
          "CPU / accelerator count",
          "CPU／加速器数量"
        ],
        [
          "Scale-up domain",
          "纵向扩展域"
        ],
        [
          "Scale-out per accelerator",
          "每加速器横向带宽"
        ],
        [
          "Rack power",
          "机架功耗"
        ],
        [
          "Cooling",
          "散热"
        ]
      ],
      "rows": [
        {
          "id": "atlas19",
          "values": [
            [
              "Atlas 2019 systems",
              "Atlas 2019 系统"
            ],
            [
              "2019",
              "2019"
            ],
            [
              "Configuration-dependent Ascend nodes",
              "依配置的昇腾节点"
            ],
            [
              "HCCS-connected nodes",
              "HCCS 连接节点"
            ],
            [
              "910 integrates 2 ×100Gb/s Ethernet; 25 GB/s raw aggregate",
              "910 集成 2×100Gb/s 以太网；原始合计 25 GB/s"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "System-dependent",
              "依系统"
            ]
          ],
          "sources": [
            "C01",
            "E07"
          ]
        },
        {
          "id": "a2",
          "values": [
            [
              "Atlas A2",
              "Atlas A2"
            ],
            [
              "2023-era",
              "2023 年前后"
            ],
            [
              "Server/module-dependent",
              "依服务器／模组"
            ],
            [
              "HCCS; system-dependent",
              "HCCS；依系统"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Air / liquid by product",
              "依产品风冷／液冷"
            ]
          ],
          "sources": [
            "P12"
          ]
        },
        {
          "id": "cm384",
          "values": [
            [
              "CloudMatrix384 / Atlas 900 A3",
              "CloudMatrix384 / Atlas 900 A3"
            ],
            [
              "2025",
              "2025"
            ],
            [
              "192 CPUs + 384 NPUs; 48 nodes",
              "192 CPU＋384 NPU；48 节点"
            ],
            [
              "384 NPUs",
              "384 NPUs"
            ],
            [
              "Dedicated RoCE per NPU die; rate n/d",
              "每 NPU 裸片独立 RoCE；速率 n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Liquid-cooled SuperPoD",
              "液冷超节点"
            ]
          ],
          "sources": [
            "R02",
            "E02",
            "E05"
          ]
        },
        {
          "id": "950road",
          "values": [
            [
              "Atlas 950 2025 design point",
              "Atlas 950 2025 设计点"
            ],
            [
              "2025 roadmap for 2026",
              "2025 公布、目标 2026"
            ],
            [
              "8,192 NPUs; 160 cabinets",
              "8192 NPU；160 柜"
            ],
            [
              "8,192 NPUs",
              "8,192 NPUs"
            ],
            [
              "UBoE / RoCE; port allocation dependent",
              "UBoE／RoCE；依端口分配"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Liquid",
              "液冷"
            ]
          ],
          "sources": [
            "E02"
          ]
        },
        {
          "id": "950waic",
          "values": [
            [
              "Atlas 950 WAIC configuration",
              "Atlas 950 WAIC 配置"
            ],
            [
              "2026-07",
              "2026-07"
            ],
            [
              "1,024 NPUs",
              "1,024 NPUs"
            ],
            [
              "1,024 NPUs",
              "1,024 NPUs"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Liquid",
              "液冷"
            ]
          ],
          "sources": [
            "E18"
          ]
        },
        {
          "id": "850",
          "values": [
            [
              "Atlas 850E",
              "Atlas 850E"
            ],
            [
              "2026-07",
              "2026-07"
            ],
            [
              "Up to 96 cards",
              "最高 96 卡"
            ],
            [
              "96 cards",
              "96 cards"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Air; VCE phase-change technology",
              "风冷；VCE 相变技术"
            ]
          ],
          "sources": [
            "E18"
          ]
        },
        {
          "id": "960e",
          "values": [
            [
              "Atlas 960E",
              "Atlas 960E"
            ],
            [
              "2026 announcement; 960 chips 2027",
              "2026 发布；960 芯片目标 2027"
            ],
            [
              "4,096 NPUs",
              "4,096 NPUs"
            ],
            [
              "4,096 NPUs",
              "4,096 NPUs"
            ],
            [
              "UB network / RoCE; per-NPU rate n/d",
              "UB 网络／RoCE；每 NPU 速率 n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Full liquid; NPO",
              "全液冷；NPO"
            ]
          ],
          "sources": [
            "E03",
            "E11"
          ]
        },
        {
          "id": "kp950pod",
          "values": [
            [
              "Kunpeng SuperPoD update",
              "鲲鹏超节点更新"
            ],
            [
              "2026-09",
              "2026-09"
            ],
            [
              "Up to 4,096 nodes",
              "最高 4096 节点"
            ],
            [
              "256 TB unified pool disclosed",
              "公布 256 TB 统一内存池"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ]
          ],
          "sources": [
            "E11"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3
        ],
        [
          0,
          4,
          5,
          6
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "software": {
      "id": "software",
      "title": [
        "Software capabilities aligned with hardware",
        "与硬件对齐的软件能力"
      ],
      "headers": [
        [
          "Release / layer",
          "版本／层次"
        ],
        [
          "Date",
          "时间"
        ],
        [
          "Hardware enabled",
          "对应硬件"
        ],
        [
          "Key features",
          "关键能力"
        ]
      ],
      "rows": [
        {
          "id": "initial",
          "values": [
            [
              "CANN / MindSpore launch",
              "CANN／MindSpore 发布"
            ],
            [
              "2019",
              "2019"
            ],
            [
              "Ascend 310 / 910",
              "Ascend 310 / 910"
            ],
            [
              "Graph compilation, operators, runtime and framework",
              "图编译、算子、运行时与框架"
            ]
          ],
          "sources": [
            "P01",
            "E20"
          ]
        },
        {
          "id": "cann3",
          "values": [
            [
              "CANN 3.0",
              "CANN 3.0"
            ],
            [
              "2020",
              "2020"
            ],
            [
              "Ascend",
              "Ascend"
            ],
            [
              "Broader developer interfaces and operator optimization",
              "扩展开发接口与算子优化"
            ]
          ],
          "sources": [
            "E08"
          ]
        },
        {
          "id": "ascendc",
          "values": [
            [
              "Ascend C",
              "Ascend C"
            ],
            [
              "Current documentation",
              "当前文档"
            ],
            [
              "Ascend AI cores",
              "Ascend AI cores"
            ],
            [
              "Explicit tiling, queue/buffer management, pipelined compute and transfer",
              "显式分块、队列／缓冲管理、计算与搬运流水化"
            ]
          ],
          "sources": [
            "P03"
          ]
        },
        {
          "id": "infer",
          "values": [
            [
              "CloudMatrix-Infer",
              "CloudMatrix-Infer"
            ],
            [
              "2025",
              "2025"
            ],
            [
              "CloudMatrix384",
              "CloudMatrix384"
            ],
            [
              "Prefill/decode/cache separation; expert parallelism; INT8 kernels",
              "预填充／解码／缓存分离；专家并行；INT8 内核"
            ]
          ],
          "sources": [
            "R02"
          ]
        },
        {
          "id": "open",
          "values": [
            [
              "CANN / Mind open source",
              "CANN / Mind open source"
            ],
            [
              "2025–2026",
              "2025–2026"
            ],
            [
              "Ascend",
              "Ascend"
            ],
            [
              "Compiler/runtime/kernel ecosystem opening; framework integration",
              "编译器／运行时／算子生态开放；框架集成"
            ]
          ],
          "sources": [
            "E09",
            "E18"
          ]
        },
        {
          "id": "950soft",
          "values": [
            [
              "DaVinci 3 / STARS 2.0 / CCU",
              "DaVinci 3 / STARS 2.0 / CCU"
            ],
            [
              "2026",
              "2026"
            ],
            [
              "Ascend 950",
              "Ascend 950"
            ],
            [
              "SIMD/SIMT; NDDMA; collective offload; cache hints; low-precision formats",
              "SIMD／SIMT；NDDMA；集合通信卸载；缓存提示；低精度格式"
            ]
          ],
          "sources": [
            "P15"
          ]
        },
        {
          "id": "infra",
          "values": [
            [
              "DPAK / QingTian / openEuler",
              "DPAK / QingTian / openEuler"
            ],
            [
              "Generation-dependent",
              "依代际"
            ],
            [
              "Kunpeng / SP900 / cloud",
              "Kunpeng / SP900 / cloud"
            ],
            [
              "Host OS, network/storage offload and tenant isolation",
              "主机操作系统、网络／存储卸载与租户隔离"
            ]
          ],
          "sources": [
            "P04",
            "P07",
            "P08"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "bandwidth": {
      "id": "bandwidth",
      "title": [
        "Bandwidth by era: scopes are intentionally separate",
        "分时期带宽层级：严格区分范围"
      ],
      "headers": [
        [
          "Era / reference",
          "时期／参考产品"
        ],
        [
          "On die / die-to-die",
          "片内／裸片间"
        ],
        [
          "Memory",
          "内存"
        ],
        [
          "Host attachment",
          "主机连接"
        ],
        [
          "Scale-up per accelerator",
          "每加速器纵向扩展"
        ],
        [
          "Scale-out per accelerator",
          "每加速器横向扩展"
        ]
      ],
      "rows": [
        {
          "id": "early",
          "values": [
            [
              "2015–2018 / 310",
              "2015—2018／310"
            ],
            [
              "Explicit local buffers; numeric rate n/d",
              "显式局部缓冲；速率 n/d"
            ],
            [
              "LPDDR; board-dependent",
              "LPDDR；依板卡"
            ],
            [
              "PCIe; n/d",
              "PCIe; n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ]
          ],
          "sources": [
            "C01",
            "P01"
          ]
        },
        {
          "id": "2019",
          "values": [
            [
              "2019–2022 / 910",
              "2019—2022／910"
            ],
            [
              "L2 fabric 4 TB/s; per-AI-core 128 GB/s read + 128 GB/s write",
              "L2 互联 4 TB/s；每 AI 核读 128 GB/s＋写 128 GB/s"
            ],
            [
              "~1.2 TB/s HBM2",
              "~1.2 TB/s HBM2"
            ],
            [
              "PCIe 4.0",
              "PCIe 4.0"
            ],
            [
              "3 ×240 Gb/s HCCS; direction n/d",
              "3×240 Gb/s HCCS；方向 n/d"
            ],
            [
              "2 ×100 Gb/s Ethernet = 25 GB/s raw aggregate",
              "2×100 Gb/s 以太网＝原始合计 25 GB/s"
            ]
          ],
          "sources": [
            "C01"
          ]
        },
        {
          "id": "2025",
          "values": [
            [
              "2023–2025 / 910C",
              "2023—2025／910C"
            ],
            [
              "Dual compute die; D2D rate n/d",
              "双计算裸片；D2D 速率 n/d"
            ],
            [
              "8 memory stacks; R02 rate n/d",
              "8 内存堆栈；R02 未给速率"
            ],
            [
              "Kunpeng / UB",
              "鲲鹏／UB"
            ],
            [
              "7 UB transceivers per die; rate n/d",
              "每裸片 7 UB 收发器；速率 n/d"
            ],
            [
              "Separate RoCE interface per die; rate n/d",
              "每裸片独立 RoCE 接口；速率 n/d"
            ]
          ],
          "sources": [
            "R02"
          ]
        },
        {
          "id": "950",
          "values": [
            [
              "2026 / maximum 950",
              "2026／最大配置 950"
            ],
            [
              "2 AI + 2 I/O; D2D rate n/d",
              "2 AI＋2 I/O；D2D 速率 n/d"
            ],
            [
              "PR 1.6; DT 4 TB/s",
              "PR 1.6; DT 4 TB/s"
            ],
            [
              "PCIe 5.0 ×16: nominal 64 GB/s/direction",
              "PCIe 5.0 ×16：标称单向 64 GB/s"
            ],
            [
              "1008 GB/s raw/direction before port reuse",
              "端口复用前原始单向 1008 GB/s"
            ],
            [
              "2 ×400G UBoE: 100 GB/s raw aggregate; shared ports",
              "2×400G UBoE：原始合计 100 GB/s；复用端口"
            ]
          ],
          "sources": [
            "P15"
          ]
        },
        {
          "id": "350",
          "values": [
            [
              "2026 / Atlas 350 card",
              "2026／Atlas 350 卡"
            ],
            [
              "28-Cube bin; D2D rate n/d",
              "28 Cube 配置；D2D 速率 n/d"
            ],
            [
              "1.4 TB/s",
              "1.4 TB/s"
            ],
            [
              "PCIe 5.0 ×16: nominal 64 GB/s/direction",
              "PCIe 5.0 ×16：标称单向 64 GB/s"
            ],
            [
              "159 GB/s/direction at 4 cards; 212 at 2 cards",
              "四卡时单向 159 GB/s；双卡 212"
            ],
            [
              "Server NIC-dependent",
              "依服务器网卡"
            ]
          ],
          "sources": [
            "P14",
            "P15"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2
        ],
        [
          0,
          3,
          4,
          5
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "ratios": {
      "id": "ratios",
      "title": [
        "Derived balance metrics, not measured application performance",
        "派生平衡指标：不是应用实测性能"
      ],
      "headers": [
        [
          "Reference",
          "参考配置"
        ],
        [
          "Calculation",
          "计算"
        ],
        [
          "Result",
          "结果"
        ],
        [
          "Interpretation / boundary",
          "含义／边界"
        ]
      ],
      "rows": [
        {
          "id": "cpu_bw",
          "values": [
            [
              "Kunpeng 920",
              "Kunpeng 920"
            ],
            [
              "8 × 8 × 2.933 / 64",
              "8 × 8 × 2.933 / 64"
            ],
            [
              "2.933 GB/s/core",
              "2.933 GB/s/core"
            ],
            [
              "Theoretical DDR4 payload; controller/workload efficiency excluded",
              "DDR4 理论数据带宽；未计控制器／工作负载效率"
            ]
          ],
          "sources": [
            "P01"
          ]
        },
        {
          "id": "cpu_llc",
          "values": [
            [
              "Kunpeng 920",
              "Kunpeng 920"
            ],
            [
              "64 MB / 64",
              "64 MB / 64"
            ],
            [
              "1 MB/core",
              "1 MB/core"
            ],
            [
              "Average shared LLC budget, not private allocation",
              "共享 LLC 平均预算，不是私有分配"
            ]
          ],
          "sources": [
            "P01"
          ]
        },
        {
          "id": "910bpf",
          "values": [
            [
              "Ascend 910",
              "Ascend 910"
            ],
            [
              "1.2e12 / 256e12",
              "1.2e12 / 256e12"
            ],
            [
              "0.00469 byte/FP16 FLOP",
              "0.00469 byte/FP16 FLOP"
            ],
            [
              "FP16; not a BF16 comparison",
              "FP16；不是 BF16 比较"
            ]
          ],
          "sources": [
            "C01"
          ]
        },
        {
          "id": "pr_bf",
          "values": [
            [
              "950PR max",
              "950PR max"
            ],
            [
              "1.6e12 / 432e12",
              "1.6e12 / 432e12"
            ],
            [
              "0.00370 byte/BF16 FLOP",
              "0.00370 byte/BF16 FLOP"
            ],
            [
              "Cube-only dense peak",
              "仅 Cube 稠密峰值"
            ]
          ],
          "sources": [
            "P15"
          ]
        },
        {
          "id": "pr_fp8",
          "values": [
            [
              "950PR max",
              "950PR max"
            ],
            [
              "1.6e12 / 865e12",
              "1.6e12 / 865e12"
            ],
            [
              "0.00185 byte/FP8 FLOP",
              "0.00185 byte/FP8 FLOP"
            ],
            [
              "Cube-only dense peak",
              "仅 Cube 稠密峰值"
            ]
          ],
          "sources": [
            "P15"
          ]
        },
        {
          "id": "dt_bf",
          "values": [
            [
              "950DT max",
              "950DT max"
            ],
            [
              "4e12 / 486e12",
              "4e12 / 486e12"
            ],
            [
              "0.00823 byte/BF16 FLOP",
              "0.00823 byte/BF16 FLOP"
            ],
            [
              "2.22× PR bandwidth per BF16 FLOP",
              "每 BF16 FLOP 的带宽为 PR 的 2.22 倍"
            ]
          ],
          "sources": [
            "P15"
          ]
        },
        {
          "id": "dt_fp8",
          "values": [
            [
              "950DT max",
              "950DT max"
            ],
            [
              "4e12 / 973e12",
              "4e12 / 973e12"
            ],
            [
              "0.00411 byte/FP8 FLOP",
              "0.00411 byte/FP8 FLOP"
            ],
            [
              "Cube-only dense peak",
              "仅 Cube 稠密峰值"
            ]
          ],
          "sources": [
            "P15"
          ]
        },
        {
          "id": "350_ratio",
          "values": [
            [
              "Atlas 350, 4 cards",
              "Atlas 350, 4 cards"
            ],
            [
              "159 / 1400",
              "159 / 1400"
            ],
            [
              "0.114",
              "0.114"
            ],
            [
              "One-way card scale-up / HBM; ~11.4%",
              "板卡单向纵向带宽／HBM；约 11.4%"
            ]
          ],
          "sources": [
            "P14"
          ]
        },
        {
          "id": "350_power",
          "values": [
            [
              "Atlas 350",
              "Atlas 350"
            ],
            [
              "378 TFLOPS / 600 W",
              "378 TFLOPS / 600 W"
            ],
            [
              "0.630 TFLOPS/W",
              "0.630 TFLOPS/W"
            ],
            [
              "BF16 Cube peak / maximum board power; not measured efficiency",
              "BF16 Cube 峰值／最大板功耗；不是实测能效"
            ]
          ],
          "sources": [
            "P14",
            "P15"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "conferences": {
      "id": "conferences",
      "title": [
        "Verified disclosures and related research",
        "已核验披露与相关研究"
      ],
      "headers": [
        [
          "Venue",
          "会议／活动"
        ],
        [
          "Year",
          "年份"
        ],
        [
          "Paper / talk / disclosure",
          "论文／演讲／披露"
        ],
        [
          "Presenter / authors",
          "报告人／作者"
        ],
        [
          "Product",
          "产品"
        ],
        [
          "Evidence type",
          "证据类型"
        ],
        [
          "Source",
          "来源"
        ]
      ],
      "rows": [
        {
          "id": "hc",
          "values": [
            [
              "Hot Chips 31",
              "Hot Chips 31"
            ],
            [
              "2019",
              "2019"
            ],
            [
              "DaVinci: A Scalable Architecture for Neural Network Computing",
              "DaVinci: A Scalable Architecture for Neural Network Computing"
            ],
            [
              "Heng Liao; Jiajin Tu; Jing Xia; Xiping Zhou",
              "Heng Liao; Jiajin Tu; Jing Xia; Xiping Zhou"
            ],
            [
              "Ascend 310 / 910",
              "Ascend 310 / 910"
            ],
            [
              "Architecture, die/package, memory, links",
              "架构、裸片／封装、内存、链路"
            ],
            [
              "C01",
              "C01"
            ]
          ],
          "sources": [
            "C01"
          ]
        },
        {
          "id": "hpca",
          "values": [
            [
              "HPCA industry track",
              "HPCA industry track"
            ],
            [
              "2021",
              "2021"
            ],
            [
              "Ascend: a scalable and unified architecture for ubiquitous deep neural network computing",
              "Ascend 可扩展统一神经网络计算架构"
            ],
            [
              "Heng Liao et al.",
              "Heng Liao et al."
            ],
            [
              "Ascend / DaVinci",
              "Ascend / DaVinci"
            ],
            [
              "Product architecture; vendor reprint read",
              "产品架构；阅读厂商重印版本"
            ],
            [
              "C04 / P01",
              "C04 / P01"
            ]
          ],
          "sources": [
            "C04",
            "P01"
          ]
        },
        {
          "id": "microjournal",
          "values": [
            [
              "IEEE Micro journal",
              "IEEE Micro journal"
            ],
            [
              "2021",
              "2021"
            ],
            [
              "HiSilicon Kunpeng 920: First 7-nm Chiplet-Based 64-Core Server CPU With Arm Ecosystem",
              "HiSilicon Kunpeng 920: First 7-nm Chiplet-Based 64-Core Server CPU With Arm Ecosystem"
            ],
            [
              "Jing Xia; Chuanning Cheng; Xiping Zhou; Yuxing Hu; Peter Chun",
              "Jing Xia；Chuanning Cheng；Xiping Zhou；Yuxing Hu；Peter Chun"
            ],
            [
              "Kunpeng 920",
              "Kunpeng 920"
            ],
            [
              "Core, cache, die partitioning; journal, not MICRO conference",
              "核心、缓存、裸片划分；期刊而非 MICRO 会议"
            ],
            [
              "P01 / C02",
              "P01 / C02"
            ]
          ],
          "sources": [
            "P01",
            "C02"
          ]
        },
        {
          "id": "isscc",
          "values": [
            [
              "ISSCC",
              "ISSCC"
            ],
            [
              "2019",
              "2019"
            ],
            [
              "6.2: 60Gb/s PAM-4 ADC-DSP Transceiver; 7nm; adaptive power scaling",
              "6.2: 60Gb/s PAM-4 ADC-DSP Transceiver; 7nm; adaptive power scaling"
            ],
            [
              "M.-A. LaCroix et al., Huawei Ottawa",
              "M.-A. LaCroix et al., Huawei Ottawa"
            ],
            [
              "Wireline IP; product adoption unproven",
              "高速有线 IP；未证明具体产品采用"
            ],
            [
              "Circuit; program reports 6.9 pJ/b at 32 dB loss",
              "电路；会议程序公布 32 dB 损耗下 6.9 pJ/b"
            ],
            [
              "C05",
              "C05"
            ]
          ],
          "sources": [
            "C05"
          ]
        },
        {
          "id": "asplos",
          "values": [
            [
              "ASPLOS",
              "ASPLOS"
            ],
            [
              "2025",
              "2025"
            ],
            [
              "Squeezing Operator Performance Potential for the Ascend Architecture",
              "Squeezing Operator Performance Potential for the Ascend Architecture"
            ],
            [
              "Yuhang Zhou et al.",
              "Yuhang Zhou et al."
            ],
            [
              "Ascend",
              "Ascend"
            ],
            [
              "Operator characterization and optimization research",
              "算子特征分析与优化研究"
            ],
            [
              "R01",
              "R01"
            ]
          ],
          "sources": [
            "R01"
          ]
        },
        {
          "id": "micro",
          "values": [
            [
              "MICRO",
              "MICRO"
            ],
            [
              "2025",
              "2025"
            ],
            [
              "RICH Prefetcher: Storing Rich Information in Memory to Trade Capacity and Bandwidth for Latency Hiding",
              "RICH Prefetcher: Storing Rich Information in Memory to Trade Capacity and Bandwidth for Latency Hiding"
            ],
            [
              "Ningzhi Ai et al.",
              "Ningzhi Ai et al."
            ],
            [
              "Related CPU research",
              "相关 CPU 研究"
            ],
            [
              "Research; no confirmed Kunpeng adoption",
              "研究；未确认鲲鹏采用"
            ],
            [
              "R06",
              "R06"
            ]
          ],
          "sources": [
            "R06"
          ]
        },
        {
          "id": "isca",
          "values": [
            [
              "ISCA",
              "ISCA"
            ],
            [
              "2026",
              "2026"
            ],
            [
              "ENEC: A Lossless AI Model Compression Method Enabling Fast Inference on Ascend NPUs",
              "ENEC: A Lossless AI Model Compression Method Enabling Fast Inference on Ascend NPUs"
            ],
            [
              "Jinwu Yang et al.",
              "Jinwu Yang et al."
            ],
            [
              "Ascend 910B2 study",
              "Ascend 910B2 study"
            ],
            [
              "Model compression research",
              "模型压缩研究"
            ],
            [
              "R03 / R05",
              "R03 / R05"
            ]
          ],
          "sources": [
            "R03",
            "R05"
          ]
        },
        {
          "id": "rccs",
          "values": [
            [
              "R-CCS Symposium",
              "R-CCS Symposium"
            ],
            [
              "2020",
              "2020"
            ],
            [
              "Kunpeng platform presentation",
              "鲲鹏平台演讲"
            ],
            [
              "Zhaohui",
              "Zhaohui"
            ],
            [
              "Hi161x / Kunpeng 916 / 920",
              "Hi161x／鲲鹏 916／920"
            ],
            [
              "CPU roadmap and platform; historical future targets",
              "CPU 路线图与平台；包含历史未来目标"
            ],
            [
              "C03",
              "C03"
            ]
          ],
          "sources": [
            "C03"
          ]
        },
        {
          "id": "hdc",
          "values": [
            [
              "Huawei Developer Conference",
              "Huawei Developer Conference"
            ],
            [
              "2025",
              "2025"
            ],
            [
              "CloudMatrix384 cloud service",
              "CloudMatrix384 云服务"
            ],
            [
              "Huawei Cloud",
              "华为云"
            ],
            [
              "CloudMatrix384",
              "CloudMatrix384"
            ],
            [
              "Cloud/system availability",
              "云／系统可用性"
            ],
            [
              "E17 / R02",
              "E17 / R02"
            ]
          ],
          "sources": [
            "E17",
            "R02"
          ]
        },
        {
          "id": "hc25",
          "values": [
            [
              "HUAWEI CONNECT",
              "HUAWEI CONNECT"
            ],
            [
              "2025",
              "2025"
            ],
            [
              "SuperPoD, 950/960 roadmap, UnifiedBus 2.0, CANN opening",
              "超节点、950／960 路线图、灵衢 2.0、CANN 开放"
            ],
            [
              "Eric Xu; Yang Chaobin; Zhang Dixuan",
              "Eric Xu; Yang Chaobin; Zhang Dixuan"
            ],
            [
              "Kunpeng / Ascend / UB",
              "Kunpeng / Ascend / UB"
            ],
            [
              "Architecture roadmap and ecosystem",
              "架构路线图与生态"
            ],
            [
              "E02 / E09 / E16",
              "E02 / E09 / E16"
            ]
          ],
          "sources": [
            "E02",
            "E09",
            "E16"
          ]
        },
        {
          "id": "mwc",
          "values": [
            [
              "MWC Barcelona",
              "MWC Barcelona"
            ],
            [
              "2026",
              "2026"
            ],
            [
              "SuperPoD and AI infrastructure showcase",
              "超节点与 AI 基础设施展示"
            ],
            [
              "Huawei",
              "华为"
            ],
            [
              "Atlas / Kunpeng",
              "Atlas / Kunpeng"
            ],
            [
              "System and industry deployment",
              "系统与行业部署"
            ],
            [
              "E05",
              "E05"
            ]
          ],
          "sources": [
            "E05"
          ]
        },
        {
          "id": "waic",
          "values": [
            [
              "WAIC",
              "WAIC"
            ],
            [
              "2026",
              "2026"
            ],
            [
              "Atlas 950, Atlas 850E, SP560 AI NIC, compute modules",
              "Atlas 950、Atlas 850E、SP560 AI 网卡、计算模组"
            ],
            [
              "Huawei",
              "华为"
            ],
            [
              "Ascend / networking",
              "Ascend / networking"
            ],
            [
              "System and product launch",
              "系统与产品发布"
            ],
            [
              "E18 / E13",
              "E18 / E13"
            ]
          ],
          "sources": [
            "E18",
            "E13"
          ]
        },
        {
          "id": "iscas",
          "values": [
            [
              "IEEE ISCAS",
              "IEEE ISCAS"
            ],
            [
              "2026",
              "2026"
            ],
            [
              "Tau scaling and logic folding",
              "τ 定律与逻辑折叠"
            ],
            [
              "Huawei researchers",
              "华为研究人员"
            ],
            [
              "Related scaling research",
              "相关扩展研究"
            ],
            [
              "Research direction; not ISSCC or a product node disclosure",
              "研究方向；不是 ISSCC，也不是产品工艺节点披露"
            ],
            [
              "E06",
              "E06"
            ]
          ],
          "sources": [
            "E06"
          ]
        },
        {
          "id": "hc26",
          "values": [
            [
              "HUAWEI CONNECT",
              "HUAWEI CONNECT"
            ],
            [
              "2026",
              "2026"
            ],
            [
              "960E, Hi-ONE, Peerium, M900, Kunpeng pools",
              "960E、Hi-ONE、Peerium、M900、鲲鹏内存池"
            ],
            [
              "David Wang; Huawei",
              "David Wang; Huawei"
            ],
            [
              "AI infrastructure stack",
              "AI infrastructure stack"
            ],
            [
              "System launch, roadmap update, optics/storage architecture",
              "系统发布、路线图更新、光学／存储架构"
            ],
            [
              "E01 / E03 / E04 / E10 / E11 / E12",
              "E01 / E03 / E04 / E10 / E11 / E12"
            ]
          ],
          "sources": [
            "E01",
            "E03",
            "E04",
            "E10",
            "E11",
            "E12"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3
        ],
        [
          0,
          4,
          5,
          6
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "crosswalk": {
      "id": "crosswalk",
      "title": [
        "Product and architecture crosswalk",
        "产品与架构名称对照"
      ],
      "headers": [
        [
          "Name / identifier",
          "名称／标识"
        ],
        [
          "Meaning",
          "含义"
        ],
        [
          "Important boundary",
          "重要边界"
        ]
      ],
      "rows": [
        {
          "id": "920",
          "values": [
            [
              "Hi1620 / Kunpeng 920 / TaiShan V110",
              "Hi1620 / Kunpeng 920 / TaiShan V110"
            ],
            [
              "Original 2019 CPU / product / core",
              "原 2019 CPU／产品／核心"
            ],
            [
              "New-model 920 platforms have separate specifications",
              "920 新型号平台规格另列"
            ]
          ],
          "sources": [
            "P01",
            "P09"
          ]
        },
        {
          "id": "950",
          "values": [
            [
              "Kunpeng 950 / Linx816",
              "Kunpeng 950 / Linx816"
            ],
            [
              "Host CPU family / embedded Ascend CPU core",
              "主机 CPU 家族／昇腾内嵌 CPU 核"
            ],
            [
              "Do not equate the two microarchitectures",
              "不能认定二者微架构相同"
            ]
          ],
          "sources": [
            "P08",
            "P15"
          ]
        },
        {
          "id": "davinci",
          "values": [
            [
              "DaVinci / Ascend / Atlas",
              "DaVinci / Ascend / Atlas"
            ],
            [
              "Architecture / processor / hardware system",
              "架构／处理器／硬件系统"
            ],
            [
              "One architecture spans multiple chips and boards",
              "同一架构覆盖多款芯片与板卡"
            ]
          ],
          "sources": [
            "C01",
            "P15",
            "P12"
          ]
        },
        {
          "id": "a3",
          "values": [
            [
              "910C / Atlas 900 A3 / CloudMatrix384",
              "910C / Atlas 900 A3 / CloudMatrix384"
            ],
            [
              "NPU / SuperPoD product / cloud-system architecture",
              "NPU／超节点产品／云系统架构"
            ],
            [
              "The paper abbreviates the processor to Ascend 910; launch identifies 910C",
              "论文简写 Ascend 910；发布资料明确为 910C"
            ]
          ],
          "sources": [
            "R02",
            "E02"
          ]
        },
        {
          "id": "pr",
          "values": [
            [
              "950PR / Atlas 350",
              "950PR / Atlas 350"
            ],
            [
              "Prefill/recommendation processor / 28-Cube PCIe card",
              "预填充／推荐处理器／28 Cube PCIe 卡"
            ],
            [
              "128 GB chip maximum vs 112 GB card configuration",
              "芯片最高 128 GB；板卡配置 112 GB"
            ]
          ],
          "sources": [
            "P15",
            "P14"
          ]
        },
        {
          "id": "ub",
          "values": [
            [
              "UB buffer / UnifiedBus",
              "UB buffer / UnifiedBus"
            ],
            [
              "AI-core local memory / system interconnect",
              "AI 核局部存储／系统互联"
            ],
            [
              "Same acronym, different layers",
              "缩写相同，层次不同"
            ]
          ],
          "sources": [
            "P15"
          ]
        },
        {
          "id": "hccs",
          "values": [
            [
              "HCCS / HCCL",
              "HCCS / HCCL"
            ],
            [
              "Hardware interconnect / collective software library",
              "硬件互联／集合通信软件库"
            ],
            [
              "A library name does not specify link bandwidth",
              "库名称不决定链路带宽"
            ]
          ],
          "sources": [
            "C01",
            "P15"
          ]
        },
        {
          "id": "sp",
          "values": [
            [
              "SP600 / SP900 / SP560 AI NIC",
              "SP600 / SP900 / SP560 AI NIC"
            ],
            [
              "NIC family / DPU family / AI NIC",
              "网卡家族／DPU 家族／AI 网卡"
            ],
            [
              "Do not infer the AI NIC from a similarly named SSD",
              "不能从同名 SSD 推定 AI 网卡规格"
            ]
          ],
          "sources": [
            "P04",
            "P06",
            "E13"
          ]
        },
        {
          "id": "optics",
          "values": [
            [
              "Hi-ONE / NPO",
              "Hi-ONE / NPO"
            ],
            [
              "Optical engine / near-packaged optics",
              "光引擎／近封装光学"
            ],
            [
              "Not a blanket synonym for CPO",
              "不能笼统等同于 CPO"
            ]
          ],
          "sources": [
            "E03"
          ]
        },
        {
          "id": "kv",
          "values": [
            [
              "OceanStor M900 / L3.5",
              "OceanStor M900 / L3.5"
            ],
            [
              "KV storage system / system-tier label",
              "KV 存储系统／系统分层名称"
            ],
            [
              "Not a CPU L3 cache or on-chip SRAM",
              "不是 CPU L3 或片内 SRAM"
            ]
          ],
          "sources": [
            "E11"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    }
  },
  "figures": {
    "era1": {
      "id": "era1",
      "title": [
        "2015–2018: host-led inference",
        "2015—2018：主机驱动的推理"
      ],
      "nodes": [
        [
          "cpu",
          [
            "Hi161x / Kunpeng 916\nHost software",
            "Hi161x／鲲鹏 916\n主机软件"
          ],
          0,
          0
        ],
        [
          "memory",
          [
            "DDR memory\nCPU working set",
            "DDR 内存\nCPU 工作集"
          ],
          1,
          0
        ],
        [
          "gpu",
          [
            "Ascend 310 / Atlas\nDaVinci inference",
            "昇腾 310／Atlas\n达芬奇推理"
          ],
          0,
          1
        ],
        [
          "local",
          [
            "LPDDR + local buffers\nVideo preprocessing",
            "LPDDR＋局部缓冲\n视频预处理"
          ],
          1,
          1
        ],
        [
          "nic",
          [
            "Host Ethernet\nNetwork / storage",
            "主机以太网\n网络／存储"
          ],
          0,
          2
        ],
        [
          "sw",
          [
            "Drivers + AI runtime\nOperator compilation",
            "驱动＋AI 运行时\n算子编译"
          ],
          1,
          2
        ]
      ],
      "edges": [
        [
          "cpu",
          "memory",
          [
            "DDR",
            "DDR"
          ]
        ],
        [
          "cpu",
          "gpu",
          [
            "PCIe",
            "PCIe"
          ]
        ],
        [
          "gpu",
          "local",
          [
            "local",
            "本地"
          ]
        ],
        [
          "gpu",
          "nic",
          [
            "via host",
            "经主机"
          ]
        ],
        [
          "nic",
          "sw",
          [
            "system",
            "系统"
          ]
        ]
      ],
      "caption": [
        "A small NPU augments a server or edge host; this is not yet a large shared accelerator domain.",
        "小型 NPU 为服务器或边缘主机提供加速，此时尚未形成大规模共享加速器域。"
      ]
    },
    "era2": {
      "id": "era2",
      "title": [
        "2019–2022: chiplets and accelerator nodes",
        "2019—2022：芯粒与加速器节点"
      ],
      "nodes": [
        [
          "cpu",
          [
            "Kunpeng 920\nCompute + I/O dies",
            "鲲鹏 920\n计算＋I/O 裸片"
          ],
          0,
          0
        ],
        [
          "memory",
          [
            "8-channel DDR4\n187.7 GB/s reference",
            "8 通道 DDR4\n参考带宽 187.7 GB/s"
          ],
          1,
          0
        ],
        [
          "gpu",
          [
            "Ascend 910 node\nCube / Vector / Scalar",
            "昇腾 910 节点\nCube／Vector／Scalar"
          ],
          0,
          1
        ],
        [
          "local",
          [
            "HBM2 + local buffers\nHCCS peer links",
            "HBM2＋局部缓冲\nHCCS 对等链路"
          ],
          1,
          1
        ],
        [
          "nic",
          [
            "RoCE / Ethernet\nCloudEngine fabric",
            "RoCE／以太网\nCloudEngine 互联"
          ],
          0,
          2
        ],
        [
          "sw",
          [
            "CANN + MindSpore\nAtlas system integration",
            "CANN＋MindSpore\nAtlas 系统集成"
          ],
          1,
          2
        ]
      ],
      "edges": [
        [
          "cpu",
          "memory",
          [
            "DDR4",
            "DDR4"
          ]
        ],
        [
          "cpu",
          "gpu",
          [
            "PCIe",
            "PCIe"
          ]
        ],
        [
          "gpu",
          "local",
          [
            "memory / peers",
            "内存／对等"
          ]
        ],
        [
          "gpu",
          "nic",
          [
            "network",
            "网络"
          ]
        ],
        [
          "nic",
          "sw",
          [
            "runtime",
            "运行时"
          ]
        ]
      ],
      "caption": [
        "Reusable silicon blocks coexist with explicit accelerator data movement; scale-out remains a network problem.",
        "可复用硅模块与显式加速器搬运并存，横向扩展仍主要通过网络完成。"
      ]
    },
    "era3": {
      "id": "era3",
      "title": [
        "2023–2025: CloudMatrix384 resource pooling",
        "2023—2025：CloudMatrix384 资源池化"
      ],
      "nodes": [
        [
          "cpu",
          [
            "192 Kunpeng CPUs\nHost DRAM pools",
            "192 颗鲲鹏 CPU\n主机 DRAM 池"
          ],
          0,
          0
        ],
        [
          "fabric",
          [
            "UB two-tier fabric\n7 switching subplanes",
            "UB 两级互联\n7 个交换子平面"
          ],
          1,
          0
        ],
        [
          "gpu",
          [
            "384 Ascend 910C NPUs\n48 nodes; dual-die NPUs",
            "384 颗昇腾 910C\n48 节点；双裸片 NPU"
          ],
          0,
          1
        ],
        [
          "local",
          [
            "HBM per package\nPrefill / decode / cache",
            "每封装 HBM\n预填充／解码／缓存"
          ],
          1,
          1
        ],
        [
          "nic",
          [
            "Separate RoCE plane\nNPU scale-out",
            "独立 RoCE 平面\nNPU 横向扩展"
          ],
          0,
          2
        ],
        [
          "dpu",
          [
            "QingTian DPU / VPC\nStorage + control",
            "擎天 DPU／VPC\n存储＋控制"
          ],
          1,
          2
        ]
      ],
      "edges": [
        [
          "cpu",
          "fabric",
          [
            "UB",
            "UB"
          ]
        ],
        [
          "cpu",
          "gpu",
          [
            "shared domain",
            "共享域"
          ]
        ],
        [
          "fabric",
          "local",
          [
            "peer access",
            "对等访问"
          ]
        ],
        [
          "gpu",
          "local",
          [
            "local / pooled",
            "本地／池化"
          ]
        ],
        [
          "gpu",
          "nic",
          [
            "RDMA",
            "RDMA"
          ]
        ],
        [
          "local",
          "dpu",
          [
            "system I/O",
            "系统 I/O"
          ]
        ]
      ],
      "caption": [
        "The UB, RoCE and VPC planes have different roles; CloudMatrix-Infer maps serving stages across the pooled resources.",
        "UB、RoCE、VPC 平面职责不同，CloudMatrix-Infer 将服务阶段映射到池化资源。"
      ]
    },
    "era4": {
      "id": "era4",
      "title": [
        "2026 disclosures: differentiated NPUs and optical scale",
        "2026 年披露：分化 NPU 与光互联扩展"
      ],
      "nodes": [
        [
          "cpu",
          [
            "Kunpeng 950\nCPU memory pools",
            "鲲鹏 950\nCPU 内存池"
          ],
          0,
          0
        ],
        [
          "fabric",
          [
            "UnifiedBus 2.0 / UBG\nHi-ONE for 960E",
            "灵衢 2.0／UBG\n960E 采用 Hi-ONE"
          ],
          1,
          0
        ],
        [
          "gpu",
          [
            "950PR / 950DT\n960E: announced system",
            "950PR／950DT\n960E：已发布系统方案"
          ],
          0,
          1
        ],
        [
          "local",
          [
            "Package memory + L2\nM900 KV tier",
            "封装内存＋L2\nM900 KV 层"
          ],
          1,
          1
        ],
        [
          "nic",
          [
            "UBoE / RoCE / SP560\nEthernet scale-out",
            "UBoE／RoCE／SP560\n以太网横向扩展"
          ],
          0,
          2
        ],
        [
          "sw",
          [
            "CANN / STARS / CCU\nSIMD + SIMT + collectives",
            "CANN／STARS／CCU\nSIMD＋SIMT＋集合通信"
          ],
          1,
          2
        ]
      ],
      "edges": [
        [
          "cpu",
          "fabric",
          [
            "UB",
            "UB"
          ]
        ],
        [
          "cpu",
          "gpu",
          [
            "host / peer",
            "主机／对等"
          ]
        ],
        [
          "fabric",
          "local",
          [
            "memory tiers",
            "内存分层"
          ]
        ],
        [
          "gpu",
          "local",
          [
            "local / remote",
            "本地／远端"
          ]
        ],
        [
          "gpu",
          "nic",
          [
            "shared ports",
            "复用端口"
          ]
        ],
        [
          "nic",
          "sw",
          [
            "schedule",
            "调度"
          ]
        ]
      ],
      "caption": [
        "This combines product roles, not a claim that every listed component ships in one SKU. 960 chips remain on the 2027 roadmap.",
        "图中组合的是产品职责，不表示所有部件已在同一 SKU 中交付；960 芯片仍处于 2027 年路线图。"
      ]
    }
  },
  "claims": {
    "headline.2019.0": {
      "value": "2019",
      "field": "Milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "C01"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "2019"
    },
    "headline.2019.1": {
      "value": "Kunpeng 920: 64 cores; 187.7 GB/s DDR4",
      "field": "CPU / memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "C01"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "2019"
    },
    "headline.2019.2": {
      "value": "Ascend 910: BF16 n/d; FP16 256 TFLOPS",
      "field": "Accelerator matrix BF16 / FP8",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "C01"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "2019"
    },
    "headline.2019.3": {
      "value": "4 HBM2 stacks; ~1.2 TB/s",
      "field": "Accelerator memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "C01"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "2019"
    },
    "headline.2019.4": {
      "value": "HCCS-connected accelerator nodes",
      "field": "Scale-up scope",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "C01"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "2019"
    },
    "headline.2025.0": {
      "value": "2025",
      "field": "Milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "2025"
    },
    "headline.2025.1": {
      "value": "CloudMatrix384: 192 Kunpeng CPUs",
      "field": "CPU / memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "2025"
    },
    "headline.2025.2": {
      "value": "910C reference: BF16 supported; peak n/d in reviewed system paper",
      "field": "Accelerator matrix BF16 / FP8",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "2025"
    },
    "headline.2025.3": {
      "value": "2 compute dies, 8 memory stacks per NPU",
      "field": "Accelerator memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "2025"
    },
    "headline.2025.4": {
      "value": "384 NPUs",
      "field": "Scale-up scope",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "2025"
    },
    "headline.950pr.0": {
      "value": "950PR",
      "field": "Milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "950pr"
    },
    "headline.950pr.1": {
      "value": "8C/16T Linx816 on maximum NPU configuration",
      "field": "CPU / memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "950pr"
    },
    "headline.950pr.2": {
      "value": "432 / 865 TFLOPS",
      "field": "Accelerator matrix BF16 / FP8",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "950pr"
    },
    "headline.950pr.3": {
      "value": "128 GB; 1.6 TB/s maximum",
      "field": "Accelerator memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "950pr"
    },
    "headline.950pr.4": {
      "value": "8,192 architectural domain; products vary",
      "field": "Scale-up scope",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "950pr"
    },
    "headline.950dt.0": {
      "value": "950DT",
      "field": "Milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P08"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "950dt"
    },
    "headline.950dt.1": {
      "value": "Host Kunpeng 950: 64/96-core server configurations",
      "field": "CPU / memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P08"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "950dt"
    },
    "headline.950dt.2": {
      "value": "486 / 973 TFLOPS",
      "field": "Accelerator matrix BF16 / FP8",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P08"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "950dt"
    },
    "headline.950dt.3": {
      "value": "144 GB; 4 TB/s",
      "field": "Accelerator memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P08"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "950dt"
    },
    "headline.950dt.4": {
      "value": "8,192 architectural domain; products vary",
      "field": "Scale-up scope",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P08"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "950dt"
    },
    "headline.960.0": {
      "value": "960 / 960E",
      "field": "Milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "E11"
      ],
      "disclosure_date": "2026-09",
      "status": "roadmap",
      "scope": "960"
    },
    "headline.960.1": {
      "value": "Kunpeng memory pools accompany NPU domains",
      "field": "CPU / memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "E11"
      ],
      "disclosure_date": "2026-09",
      "status": "roadmap",
      "scope": "960"
    },
    "headline.960.2": {
      "value": "8 EFLOPS FP8 per announced 960E system",
      "field": "Accelerator matrix BF16 / FP8",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "E11"
      ],
      "disclosure_date": "2026-09",
      "status": "roadmap",
      "scope": "960"
    },
    "headline.960.3": {
      "value": "Up to 1 PB per system",
      "field": "Accelerator memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "E11"
      ],
      "disclosure_date": "2026-09",
      "status": "roadmap",
      "scope": "960"
    },
    "headline.960.4": {
      "value": "4,096 NPUs",
      "field": "Scale-up scope",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "E11"
      ],
      "disclosure_date": "2026-09",
      "status": "roadmap",
      "scope": "960"
    },
    "cpu.early.0": {
      "value": "Hi1610 / Hi1612 baseline",
      "field": "Generation / reference SKU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R07"
      ],
      "disclosure_date": "2015",
      "status": "historical",
      "scope": "early"
    },
    "cpu.early.1": {
      "value": "Hi1610 / Hi1612",
      "field": "Codename",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R07"
      ],
      "disclosure_date": "2015",
      "status": "historical",
      "scope": "early"
    },
    "cpu.early.2": {
      "value": "2015 driver record; GA n/d",
      "field": "GA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R07"
      ],
      "disclosure_date": "2015",
      "status": "historical",
      "scope": "early"
    },
    "cpu.early.3": {
      "value": "Historical shipping",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R07"
      ],
      "disclosure_date": "2015",
      "status": "historical",
      "scope": "early"
    },
    "cpu.early.4": {
      "value": "n/d",
      "field": "Core µarch",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R07"
      ],
      "disclosure_date": "2015",
      "status": "historical",
      "scope": "early"
    },
    "cpu.early.5": {
      "value": "n/d",
      "field": "Cores / threads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R07"
      ],
      "disclosure_date": "2015",
      "status": "historical",
      "scope": "early"
    },
    "cpu.early.6": {
      "value": "n/d",
      "field": "Process per die",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R07"
      ],
      "disclosure_date": "2015",
      "status": "historical",
      "scope": "early"
    },
    "cpu.early.7": {
      "value": "n/d",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R07"
      ],
      "disclosure_date": "2015",
      "status": "historical",
      "scope": "early"
    },
    "cpu.early.8": {
      "value": "n/d",
      "field": "L2 per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R07"
      ],
      "disclosure_date": "2015",
      "status": "historical",
      "scope": "early"
    },
    "cpu.early.9": {
      "value": "n/d",
      "field": "L3 / domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R07"
      ],
      "disclosure_date": "2015",
      "status": "historical",
      "scope": "early"
    },
    "cpu.early.10": {
      "value": "n/d",
      "field": "Memory: channels; rate; GB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R07"
      ],
      "disclosure_date": "2015",
      "status": "historical",
      "scope": "early"
    },
    "cpu.early.11": {
      "value": "n/d",
      "field": "Sockets / links",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R07"
      ],
      "disclosure_date": "2015",
      "status": "historical",
      "scope": "early"
    },
    "cpu.early.12": {
      "value": "n/d",
      "field": "PCIe / CXL",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R07"
      ],
      "disclosure_date": "2015",
      "status": "historical",
      "scope": "early"
    },
    "cpu.early.13": {
      "value": "n/d",
      "field": "TDP",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R07"
      ],
      "disclosure_date": "2015",
      "status": "historical",
      "scope": "early"
    },
    "cpu.early.14": {
      "value": "n/d",
      "field": "Vector / matrix ISA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R07"
      ],
      "disclosure_date": "2015",
      "status": "historical",
      "scope": "early"
    },
    "cpu.916.0": {
      "value": "Kunpeng 916",
      "field": "Generation / reference SKU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03",
        "P10",
        "P16"
      ],
      "disclosure_date": "2017",
      "status": "shipping",
      "scope": "916"
    },
    "cpu.916.1": {
      "value": "Hi1616",
      "field": "Codename",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03",
        "P10",
        "P16"
      ],
      "disclosure_date": "2017",
      "status": "shipping",
      "scope": "916"
    },
    "cpu.916.2": {
      "value": "Pre-2019 generation",
      "field": "GA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03",
        "P10",
        "P16"
      ],
      "disclosure_date": "2017",
      "status": "shipping",
      "scope": "916"
    },
    "cpu.916.3": {
      "value": "Historical shipping",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03",
        "P10",
        "P16"
      ],
      "disclosure_date": "2017",
      "status": "shipping",
      "scope": "916"
    },
    "cpu.916.4": {
      "value": "n/d",
      "field": "Core µarch",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03",
        "P10",
        "P16"
      ],
      "disclosure_date": "2017",
      "status": "shipping",
      "scope": "916"
    },
    "cpu.916.5": {
      "value": "32 / 32",
      "field": "Cores / threads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03",
        "P10",
        "P16"
      ],
      "disclosure_date": "2017",
      "status": "shipping",
      "scope": "916"
    },
    "cpu.916.6": {
      "value": "16 nm",
      "field": "Process per die",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03",
        "P10",
        "P16"
      ],
      "disclosure_date": "2017",
      "status": "shipping",
      "scope": "916"
    },
    "cpu.916.7": {
      "value": "n/d",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03",
        "P10",
        "P16"
      ],
      "disclosure_date": "2017",
      "status": "shipping",
      "scope": "916"
    },
    "cpu.916.8": {
      "value": "n/d",
      "field": "L2 per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03",
        "P10",
        "P16"
      ],
      "disclosure_date": "2017",
      "status": "shipping",
      "scope": "916"
    },
    "cpu.916.9": {
      "value": "n/d",
      "field": "L3 / domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03",
        "P10",
        "P16"
      ],
      "disclosure_date": "2017",
      "status": "shipping",
      "scope": "916"
    },
    "cpu.916.10": {
      "value": "DDR4; 4 channels; 2400 MT/s; 76.8 GB/s",
      "field": "Memory: channels; rate; GB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03",
        "P10",
        "P16"
      ],
      "disclosure_date": "2017",
      "status": "shipping",
      "scope": "916"
    },
    "cpu.916.11": {
      "value": "2P boards",
      "field": "Sockets / links",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03",
        "P10",
        "P16"
      ],
      "disclosure_date": "2017",
      "status": "shipping",
      "scope": "916"
    },
    "cpu.916.12": {
      "value": "PCIe 3.0; CXL n/a",
      "field": "PCIe / CXL",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03",
        "P10",
        "P16"
      ],
      "disclosure_date": "2017",
      "status": "shipping",
      "scope": "916"
    },
    "cpu.916.13": {
      "value": "n/d",
      "field": "TDP",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03",
        "P10",
        "P16"
      ],
      "disclosure_date": "2017",
      "status": "shipping",
      "scope": "916"
    },
    "cpu.916.14": {
      "value": "Arm NEON",
      "field": "Vector / matrix ISA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03",
        "P10",
        "P16"
      ],
      "disclosure_date": "2017",
      "status": "shipping",
      "scope": "916"
    },
    "cpu.920.0": {
      "value": "Kunpeng 920",
      "field": "Generation / reference SKU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "C03",
        "P13"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "920"
    },
    "cpu.920.1": {
      "value": "Hi1620",
      "field": "Codename",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "C03",
        "P13"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "920"
    },
    "cpu.920.2": {
      "value": "2019",
      "field": "GA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "C03",
        "P13"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "920"
    },
    "cpu.920.3": {
      "value": "Historical shipping",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "C03",
        "P13"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "920"
    },
    "cpu.920.4": {
      "value": "TaiShan V110",
      "field": "Core µarch",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "C03",
        "P13"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "920"
    },
    "cpu.920.5": {
      "value": "64 / 64",
      "field": "Cores / threads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "C03",
        "P13"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "920"
    },
    "cpu.920.6": {
      "value": "Compute 7 nm; I/O 16 nm",
      "field": "Process per die",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "C03",
        "P13"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "920"
    },
    "cpu.920.7": {
      "value": "2 compute + 1 I/O; CoWoS reference",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "C03",
        "P13"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "920"
    },
    "cpu.920.8": {
      "value": "512 KiB",
      "field": "L2 per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "C03",
        "P13"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "920"
    },
    "cpu.920.9": {
      "value": "64 MB; sliced, ~1 MB/core",
      "field": "L3 / domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "C03",
        "P13"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "920"
    },
    "cpu.920.10": {
      "value": "DDR4; 8 channels; 2933 MT/s; 187.7 GB/s",
      "field": "Memory: channels; rate; GB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "C03",
        "P13"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "920"
    },
    "cpu.920.11": {
      "value": "2P / 4P; HCCS",
      "field": "Sockets / links",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "C03",
        "P13"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "920"
    },
    "cpu.920.12": {
      "value": "PCIe 4.0 ×40; CXL n/a",
      "field": "PCIe / CXL",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "C03",
        "P13"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "920"
    },
    "cpu.920.13": {
      "value": "200 W paper reference",
      "field": "TDP",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "C03",
        "P13"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "920"
    },
    "cpu.920.14": {
      "value": "128-bit NEON",
      "field": "Vector / matrix ISA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "C03",
        "P13"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "920"
    },
    "cpu.920new.0": {
      "value": "Kunpeng 920 new models",
      "field": "Generation / reference SKU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P09"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "920new"
    },
    "cpu.920new.1": {
      "value": "n/d",
      "field": "Codename",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P09"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "920new"
    },
    "cpu.920new.2": {
      "value": "Current motherboard portfolio; GA n/d",
      "field": "GA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P09"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "920new"
    },
    "cpu.920new.3": {
      "value": "Shipping / available",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P09"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "920new"
    },
    "cpu.920new.4": {
      "value": "n/d",
      "field": "Core µarch",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P09"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "920new"
    },
    "cpu.920new.5": {
      "value": "SMT2; SKU core count n/d here",
      "field": "Cores / threads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P09"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "920new"
    },
    "cpu.920new.6": {
      "value": "n/d",
      "field": "Process per die",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P09"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "920new"
    },
    "cpu.920new.7": {
      "value": "n/d",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P09"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "920new"
    },
    "cpu.920new.8": {
      "value": "n/d",
      "field": "L2 per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P09"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "920new"
    },
    "cpu.920new.9": {
      "value": "n/d",
      "field": "L3 / domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P09"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "920new"
    },
    "cpu.920new.10": {
      "value": "DDR5; channels / bandwidth n/d",
      "field": "Memory: channels; rate; GB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P09"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "920new"
    },
    "cpu.920new.11": {
      "value": "2P / 4P boards",
      "field": "Sockets / links",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P09"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "920new"
    },
    "cpu.920new.12": {
      "value": "PCIe 5.0; CXL n/d",
      "field": "PCIe / CXL",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P09"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "920new"
    },
    "cpu.920new.13": {
      "value": "n/d",
      "field": "TDP",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P09"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "920new"
    },
    "cpu.920new.14": {
      "value": "n/d",
      "field": "Vector / matrix ISA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P09"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "920new"
    },
    "cpu.950.0": {
      "value": "Kunpeng 950",
      "field": "Generation / reference SKU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P08",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950"
    },
    "cpu.950.1": {
      "value": "n/d",
      "field": "Codename",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P08",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950"
    },
    "cpu.950.2": {
      "value": "2026 H1 server brief",
      "field": "GA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P08",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950"
    },
    "cpu.950.3": {
      "value": "Shipping / available",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P08",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950"
    },
    "cpu.950.4": {
      "value": "n/d",
      "field": "Core µarch",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P08",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950"
    },
    "cpu.950.5": {
      "value": "64 / 96 cores per socket; SMT2",
      "field": "Cores / threads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P08",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950"
    },
    "cpu.950.6": {
      "value": "n/d",
      "field": "Process per die",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P08",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950"
    },
    "cpu.950.7": {
      "value": "n/d",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P08",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950"
    },
    "cpu.950.8": {
      "value": "n/d",
      "field": "L2 per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P08",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950"
    },
    "cpu.950.9": {
      "value": "n/d",
      "field": "L3 / domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P08",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950"
    },
    "cpu.950.10": {
      "value": "DDR5 RDIMM 7200 / MRDIMM 8800; channels n/d",
      "field": "Memory: channels; rate; GB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P08",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950"
    },
    "cpu.950.11": {
      "value": "2P reference board",
      "field": "Sockets / links",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P08",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950"
    },
    "cpu.950.12": {
      "value": "n/d",
      "field": "PCIe / CXL",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P08",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950"
    },
    "cpu.950.13": {
      "value": "n/d",
      "field": "TDP",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P08",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950"
    },
    "cpu.950.14": {
      "value": "n/d",
      "field": "Vector / matrix ISA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P08",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950"
    },
    "cpu.950max.0": {
      "value": "Kunpeng 950 larger configuration",
      "field": "Generation / reference SKU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2025-09",
      "status": "roadmap",
      "scope": "950max"
    },
    "cpu.950max.1": {
      "value": "n/d",
      "field": "Codename",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2025-09",
      "status": "roadmap",
      "scope": "950max"
    },
    "cpu.950max.2": {
      "value": "2025 roadmap; GA n/d",
      "field": "GA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2025-09",
      "status": "roadmap",
      "scope": "950max"
    },
    "cpu.950max.3": {
      "value": "Roadmap",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2025-09",
      "status": "roadmap",
      "scope": "950max"
    },
    "cpu.950max.4": {
      "value": "n/d",
      "field": "Core µarch",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2025-09",
      "status": "roadmap",
      "scope": "950max"
    },
    "cpu.950max.5": {
      "value": "192 / 384",
      "field": "Cores / threads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2025-09",
      "status": "roadmap",
      "scope": "950max"
    },
    "cpu.950max.6": {
      "value": "n/d",
      "field": "Process per die",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2025-09",
      "status": "roadmap",
      "scope": "950max"
    },
    "cpu.950max.7": {
      "value": "n/d",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2025-09",
      "status": "roadmap",
      "scope": "950max"
    },
    "cpu.950max.8": {
      "value": "n/d",
      "field": "L2 per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2025-09",
      "status": "roadmap",
      "scope": "950max"
    },
    "cpu.950max.9": {
      "value": "n/d",
      "field": "L3 / domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2025-09",
      "status": "roadmap",
      "scope": "950max"
    },
    "cpu.950max.10": {
      "value": "n/d",
      "field": "Memory: channels; rate; GB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2025-09",
      "status": "roadmap",
      "scope": "950max"
    },
    "cpu.950max.11": {
      "value": "n/d",
      "field": "Sockets / links",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2025-09",
      "status": "roadmap",
      "scope": "950max"
    },
    "cpu.950max.12": {
      "value": "n/d",
      "field": "PCIe / CXL",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2025-09",
      "status": "roadmap",
      "scope": "950max"
    },
    "cpu.950max.13": {
      "value": "n/d",
      "field": "TDP",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2025-09",
      "status": "roadmap",
      "scope": "950max"
    },
    "cpu.950max.14": {
      "value": "n/d",
      "field": "Vector / matrix ISA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2025-09",
      "status": "roadmap",
      "scope": "950max"
    },
    "accelerator.310.0": {
      "value": "Ascend 310",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E07"
      ],
      "disclosure_date": "2018",
      "status": "shipping",
      "scope": "310"
    },
    "accelerator.310.1": {
      "value": "DaVinci",
      "field": "Architecture",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E07"
      ],
      "disclosure_date": "2018",
      "status": "shipping",
      "scope": "310"
    },
    "accelerator.310.2": {
      "value": "2018",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E07"
      ],
      "disclosure_date": "2018",
      "status": "shipping",
      "scope": "310"
    },
    "accelerator.310.3": {
      "value": "Historical shipping",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E07"
      ],
      "disclosure_date": "2018",
      "status": "shipping",
      "scope": "310"
    },
    "accelerator.310.4": {
      "value": "12 nm",
      "field": "Process",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E07"
      ],
      "disclosure_date": "2018",
      "status": "shipping",
      "scope": "310"
    },
    "accelerator.310.5": {
      "value": "n/d",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E07"
      ],
      "disclosure_date": "2018",
      "status": "shipping",
      "scope": "310"
    },
    "accelerator.310.6": {
      "value": "2 AI cores",
      "field": "Compute units",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E07"
      ],
      "disclosure_date": "2018",
      "status": "shipping",
      "scope": "310"
    },
    "accelerator.310.7": {
      "value": "n/d",
      "field": "Dense BF16",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E07"
      ],
      "disclosure_date": "2018",
      "status": "shipping",
      "scope": "310"
    },
    "accelerator.310.8": {
      "value": "n/d",
      "field": "Dense FP8",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E07"
      ],
      "disclosure_date": "2018",
      "status": "shipping",
      "scope": "310"
    },
    "accelerator.310.9": {
      "value": "n/d",
      "field": "Dense FP6 / FP4",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E07"
      ],
      "disclosure_date": "2018",
      "status": "shipping",
      "scope": "310"
    },
    "accelerator.310.10": {
      "value": "n/d",
      "field": "FP64 vector / matrix",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E07"
      ],
      "disclosure_date": "2018",
      "status": "shipping",
      "scope": "310"
    },
    "accelerator.310.11": {
      "value": "External LPDDR; board-dependent",
      "field": "Memory: type; stacks; GB; TB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E07"
      ],
      "disclosure_date": "2018",
      "status": "shipping",
      "scope": "310"
    },
    "accelerator.310.12": {
      "value": "n/d",
      "field": "LLC / SRAM",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E07"
      ],
      "disclosure_date": "2018",
      "status": "shipping",
      "scope": "310"
    },
    "accelerator.310.13": {
      "value": "n/d",
      "field": "Scale-up: links; GB/s per direction; domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E07"
      ],
      "disclosure_date": "2018",
      "status": "shipping",
      "scope": "310"
    },
    "accelerator.310.14": {
      "value": "PCIe",
      "field": "Host link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E07"
      ],
      "disclosure_date": "2018",
      "status": "shipping",
      "scope": "310"
    },
    "accelerator.310.15": {
      "value": "8 W chip",
      "field": "Power / cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E07"
      ],
      "disclosure_date": "2018",
      "status": "shipping",
      "scope": "310"
    },
    "accelerator.310.16": {
      "value": "Chip / Atlas modules",
      "field": "Form factor",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E07"
      ],
      "disclosure_date": "2018",
      "status": "shipping",
      "scope": "310"
    },
    "accelerator.910.0": {
      "value": "Ascend 910",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E20"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "910"
    },
    "accelerator.910.1": {
      "value": "DaVinci",
      "field": "Architecture",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E20"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "910"
    },
    "accelerator.910.2": {
      "value": "2019",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E20"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "910"
    },
    "accelerator.910.3": {
      "value": "Historical shipping",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E20"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "910"
    },
    "accelerator.910.4": {
      "value": "Compute N7+; other die nodes n/d",
      "field": "Process",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E20"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "910"
    },
    "accelerator.910.5": {
      "value": "Compute + Nimbus I/O + 4 HBM2 + dummy dies",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E20"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "910"
    },
    "accelerator.910.6": {
      "value": "32 AI cores",
      "field": "Compute units",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E20"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "910"
    },
    "accelerator.910.7": {
      "value": "n/d; FP16 256 TFLOPS",
      "field": "Dense BF16",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E20"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "910"
    },
    "accelerator.910.8": {
      "value": "n/d",
      "field": "Dense FP8",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E20"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "910"
    },
    "accelerator.910.9": {
      "value": "n/d",
      "field": "Dense FP6 / FP4",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E20"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "910"
    },
    "accelerator.910.10": {
      "value": "n/d",
      "field": "FP64 vector / matrix",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E20"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "910"
    },
    "accelerator.910.11": {
      "value": "HBM2; 4 stacks; capacity SKU-dependent; ~1.2 TB/s",
      "field": "Memory: type; stacks; GB; TB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E20"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "910"
    },
    "accelerator.910.12": {
      "value": "L2 fabric 4 TB/s in HC talk",
      "field": "LLC / SRAM",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E20"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "910"
    },
    "accelerator.910.13": {
      "value": "3 × 240 Gb/s HCCS; direction n/d",
      "field": "Scale-up: links; GB/s per direction; domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E20"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "910"
    },
    "accelerator.910.14": {
      "value": "PCIe 4.0",
      "field": "Host link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E20"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "910"
    },
    "accelerator.910.15": {
      "value": "350 W HC target; launch 310 W",
      "field": "Power / cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E20"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "910"
    },
    "accelerator.910.16": {
      "value": "Atlas accelerator / server",
      "field": "Form factor",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01",
        "E20"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "910"
    },
    "accelerator.310p.0": {
      "value": "Ascend 310P",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "310p"
    },
    "accelerator.310p.1": {
      "value": "Inference branch",
      "field": "Architecture",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "310p"
    },
    "accelerator.310p.2": {
      "value": "Atlas 300I Pro / Duo generation",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "310p"
    },
    "accelerator.310p.3": {
      "value": "Historical shipping",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "310p"
    },
    "accelerator.310p.4": {
      "value": "n/d",
      "field": "Process",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "310p"
    },
    "accelerator.310p.5": {
      "value": "n/d",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "310p"
    },
    "accelerator.310p.6": {
      "value": "n/d",
      "field": "Compute units",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "310p"
    },
    "accelerator.310p.7": {
      "value": "n/d",
      "field": "Dense BF16",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "310p"
    },
    "accelerator.310p.8": {
      "value": "n/d",
      "field": "Dense FP8",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "310p"
    },
    "accelerator.310p.9": {
      "value": "n/d",
      "field": "Dense FP6 / FP4",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "310p"
    },
    "accelerator.310p.10": {
      "value": "n/d",
      "field": "FP64 vector / matrix",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "310p"
    },
    "accelerator.310p.11": {
      "value": "LPDDR; configuration-dependent",
      "field": "Memory: type; stacks; GB; TB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "310p"
    },
    "accelerator.310p.12": {
      "value": "n/d",
      "field": "LLC / SRAM",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "310p"
    },
    "accelerator.310p.13": {
      "value": "n/d",
      "field": "Scale-up: links; GB/s per direction; domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "310p"
    },
    "accelerator.310p.14": {
      "value": "PCIe",
      "field": "Host link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "310p"
    },
    "accelerator.310p.15": {
      "value": "n/d",
      "field": "Power / cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "310p"
    },
    "accelerator.310p.16": {
      "value": "Inference cards / edge systems",
      "field": "Form factor",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12"
      ],
      "disclosure_date": "2026",
      "status": "shipping",
      "scope": "310p"
    },
    "accelerator.910b.0": {
      "value": "Ascend 910B2 / A2",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12",
        "R01",
        "R05"
      ],
      "disclosure_date": "2023",
      "status": "shipping",
      "scope": "910b"
    },
    "accelerator.910b.1": {
      "value": "DaVinci",
      "field": "Architecture",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12",
        "R01",
        "R05"
      ],
      "disclosure_date": "2023",
      "status": "shipping",
      "scope": "910b"
    },
    "accelerator.910b.2": {
      "value": "2023-era A2 systems",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12",
        "R01",
        "R05"
      ],
      "disclosure_date": "2023",
      "status": "shipping",
      "scope": "910b"
    },
    "accelerator.910b.3": {
      "value": "Historical shipping",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12",
        "R01",
        "R05"
      ],
      "disclosure_date": "2023",
      "status": "shipping",
      "scope": "910b"
    },
    "accelerator.910b.4": {
      "value": "n/d",
      "field": "Process",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12",
        "R01",
        "R05"
      ],
      "disclosure_date": "2023",
      "status": "shipping",
      "scope": "910b"
    },
    "accelerator.910b.5": {
      "value": "n/d",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12",
        "R01",
        "R05"
      ],
      "disclosure_date": "2023",
      "status": "shipping",
      "scope": "910b"
    },
    "accelerator.910b.6": {
      "value": "24 AIC + 48 AIV",
      "field": "Compute units",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12",
        "R01",
        "R05"
      ],
      "disclosure_date": "2023",
      "status": "shipping",
      "scope": "910b"
    },
    "accelerator.910b.7": {
      "value": "Supported; SKU peak n/d",
      "field": "Dense BF16",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12",
        "R01",
        "R05"
      ],
      "disclosure_date": "2023",
      "status": "shipping",
      "scope": "910b"
    },
    "accelerator.910b.8": {
      "value": "n/d",
      "field": "Dense FP8",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12",
        "R01",
        "R05"
      ],
      "disclosure_date": "2023",
      "status": "shipping",
      "scope": "910b"
    },
    "accelerator.910b.9": {
      "value": "n/d",
      "field": "Dense FP6 / FP4",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12",
        "R01",
        "R05"
      ],
      "disclosure_date": "2023",
      "status": "shipping",
      "scope": "910b"
    },
    "accelerator.910b.10": {
      "value": "n/d",
      "field": "FP64 vector / matrix",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12",
        "R01",
        "R05"
      ],
      "disclosure_date": "2023",
      "status": "shipping",
      "scope": "910b"
    },
    "accelerator.910b.11": {
      "value": "64 GB HBM in ENEC 910B2 test system; rate n/d",
      "field": "Memory: type; stacks; GB; TB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12",
        "R01",
        "R05"
      ],
      "disclosure_date": "2023",
      "status": "shipping",
      "scope": "910b"
    },
    "accelerator.910b.12": {
      "value": "n/d",
      "field": "LLC / SRAM",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12",
        "R01",
        "R05"
      ],
      "disclosure_date": "2023",
      "status": "shipping",
      "scope": "910b"
    },
    "accelerator.910b.13": {
      "value": "HCCS; configuration-dependent",
      "field": "Scale-up: links; GB/s per direction; domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12",
        "R01",
        "R05"
      ],
      "disclosure_date": "2023",
      "status": "shipping",
      "scope": "910b"
    },
    "accelerator.910b.14": {
      "value": "PCIe",
      "field": "Host link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12",
        "R01",
        "R05"
      ],
      "disclosure_date": "2023",
      "status": "shipping",
      "scope": "910b"
    },
    "accelerator.910b.15": {
      "value": "n/d",
      "field": "Power / cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12",
        "R01",
        "R05"
      ],
      "disclosure_date": "2023",
      "status": "shipping",
      "scope": "910b"
    },
    "accelerator.910b.16": {
      "value": "Atlas A2 servers / modules",
      "field": "Form factor",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12",
        "R01",
        "R05"
      ],
      "disclosure_date": "2023",
      "status": "shipping",
      "scope": "910b"
    },
    "accelerator.910c.0": {
      "value": "Ascend 910C / A3",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "910c"
    },
    "accelerator.910c.1": {
      "value": "DaVinci",
      "field": "Architecture",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "910c"
    },
    "accelerator.910c.2": {
      "value": "2025-03",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "910c"
    },
    "accelerator.910c.3": {
      "value": "Shipping / available",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "910c"
    },
    "accelerator.910c.4": {
      "value": "n/d",
      "field": "Process",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "910c"
    },
    "accelerator.910c.5": {
      "value": "2 compute dies; 8 memory stacks",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "910c"
    },
    "accelerator.910c.6": {
      "value": "48 AIC + 96 AIV",
      "field": "Compute units",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "910c"
    },
    "accelerator.910c.7": {
      "value": "Supported; peak n/d in R02",
      "field": "Dense BF16",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "910c"
    },
    "accelerator.910c.8": {
      "value": "INT8 path; native FP8 not established",
      "field": "Dense FP8",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "910c"
    },
    "accelerator.910c.9": {
      "value": "n/d",
      "field": "Dense FP6 / FP4",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "910c"
    },
    "accelerator.910c.10": {
      "value": "n/d",
      "field": "FP64 vector / matrix",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "910c"
    },
    "accelerator.910c.11": {
      "value": "8 stacks; capacity / rate n/d in R02",
      "field": "Memory: type; stacks; GB; TB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "910c"
    },
    "accelerator.910c.12": {
      "value": "n/d",
      "field": "LLC / SRAM",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "910c"
    },
    "accelerator.910c.13": {
      "value": "7 UB transceivers per die; 384-NPU domain",
      "field": "Scale-up: links; GB/s per direction; domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "910c"
    },
    "accelerator.910c.14": {
      "value": "Kunpeng / UB system",
      "field": "Host link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "910c"
    },
    "accelerator.910c.15": {
      "value": "n/d",
      "field": "Power / cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "910c"
    },
    "accelerator.910c.16": {
      "value": "Atlas 900 A3 / CloudMatrix384",
      "field": "Form factor",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "shipping",
      "scope": "910c"
    },
    "accelerator.950pr.0": {
      "value": "Ascend 950PR",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950pr"
    },
    "accelerator.950pr.1": {
      "value": "DaVinci 3",
      "field": "Architecture",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950pr"
    },
    "accelerator.950pr.2": {
      "value": "2026; Atlas 350 product",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950pr"
    },
    "accelerator.950pr.3": {
      "value": "Shipping / available",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950pr"
    },
    "accelerator.950pr.4": {
      "value": "n/d",
      "field": "Process",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950pr"
    },
    "accelerator.950pr.5": {
      "value": "2 AI + 2 I/O dies; 8 memory modules",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950pr"
    },
    "accelerator.950pr.6": {
      "value": "32 AIC + 64 AIV",
      "field": "Compute units",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950pr"
    },
    "accelerator.950pr.7": {
      "value": "432 TFLOPS",
      "field": "Dense BF16",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950pr"
    },
    "accelerator.950pr.8": {
      "value": "865 TFLOPS",
      "field": "Dense FP8",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950pr"
    },
    "accelerator.950pr.9": {
      "value": "MXFP4 1730 TFLOPS; FP6 n/d",
      "field": "Dense FP6 / FP4",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950pr"
    },
    "accelerator.950pr.10": {
      "value": "n/d",
      "field": "FP64 vector / matrix",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950pr"
    },
    "accelerator.950pr.11": {
      "value": "128 GB; 1.6 TB/s; stack generation n/d",
      "field": "Memory: type; stacks; GB; TB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950pr"
    },
    "accelerator.950pr.12": {
      "value": "128 MB",
      "field": "LLC / SRAM",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950pr"
    },
    "accelerator.950pr.13": {
      "value": "18 ×4 ports; 56 GB/s raw/link/direction; 1008 GB/s total/direction before port reuse",
      "field": "Scale-up: links; GB/s per direction; domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950pr"
    },
    "accelerator.950pr.14": {
      "value": "PCIe 5.0 ×16",
      "field": "Host link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950pr"
    },
    "accelerator.950pr.15": {
      "value": "n/d",
      "field": "Power / cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950pr"
    },
    "accelerator.950pr.16": {
      "value": "Chip; several bins",
      "field": "Form factor",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "950pr"
    },
    "accelerator.350.0": {
      "value": "Atlas 350",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14",
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "350"
    },
    "accelerator.350.1": {
      "value": "950PR / DaVinci 3",
      "field": "Architecture",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14",
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "350"
    },
    "accelerator.350.2": {
      "value": "2026 product listing",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14",
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "350"
    },
    "accelerator.350.3": {
      "value": "Shipping / available",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14",
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "350"
    },
    "accelerator.350.4": {
      "value": "n/d",
      "field": "Process",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14",
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "350"
    },
    "accelerator.350.5": {
      "value": "950PR card configuration",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14",
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "350"
    },
    "accelerator.350.6": {
      "value": "28 AIC + 56 AIV",
      "field": "Compute units",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14",
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "350"
    },
    "accelerator.350.7": {
      "value": "378 TFLOPS",
      "field": "Dense BF16",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14",
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "350"
    },
    "accelerator.350.8": {
      "value": "756 TFLOPS",
      "field": "Dense FP8",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14",
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "350"
    },
    "accelerator.350.9": {
      "value": "MXFP4 1513 TFLOPS",
      "field": "Dense FP6 / FP4",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14",
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "350"
    },
    "accelerator.350.10": {
      "value": "n/d",
      "field": "FP64 vector / matrix",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14",
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "350"
    },
    "accelerator.350.11": {
      "value": "112 GB HBM; 1.4 TB/s",
      "field": "Memory: type; stacks; GB; TB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14",
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "350"
    },
    "accelerator.350.12": {
      "value": "112 MB",
      "field": "LLC / SRAM",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14",
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "350"
    },
    "accelerator.350.13": {
      "value": "4 cards: 159 GB/s/direction/card; 2 cards: 212 GB/s/direction/card",
      "field": "Scale-up: links; GB/s per direction; domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14",
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "350"
    },
    "accelerator.350.14": {
      "value": "PCIe 5.0 ×16",
      "field": "Host link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14",
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "350"
    },
    "accelerator.350.15": {
      "value": "≤600 W; passive heatsink",
      "field": "Power / cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14",
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "350"
    },
    "accelerator.350.16": {
      "value": "PCIe OH FL DW",
      "field": "Form factor",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14",
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "available",
      "scope": "350"
    },
    "accelerator.950dt.0": {
      "value": "Ascend 950DT",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P12",
        "E18",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "product-listed",
      "scope": "950dt"
    },
    "accelerator.950dt.1": {
      "value": "DaVinci 3",
      "field": "Architecture",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P12",
        "E18",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "product-listed",
      "scope": "950dt"
    },
    "accelerator.950dt.2": {
      "value": "2026 systems listed; earlier Q4 target",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P12",
        "E18",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "product-listed",
      "scope": "950dt"
    },
    "accelerator.950dt.3": {
      "value": "Product-listed; chip GA date n/d",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P12",
        "E18",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "product-listed",
      "scope": "950dt"
    },
    "accelerator.950dt.4": {
      "value": "n/d",
      "field": "Process",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P12",
        "E18",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "product-listed",
      "scope": "950dt"
    },
    "accelerator.950dt.5": {
      "value": "2 AI + 2 I/O dies; 4 memory modules",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P12",
        "E18",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "product-listed",
      "scope": "950dt"
    },
    "accelerator.950dt.6": {
      "value": "36 AIC + 72 AIV",
      "field": "Compute units",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P12",
        "E18",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "product-listed",
      "scope": "950dt"
    },
    "accelerator.950dt.7": {
      "value": "486 TFLOPS",
      "field": "Dense BF16",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P12",
        "E18",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "product-listed",
      "scope": "950dt"
    },
    "accelerator.950dt.8": {
      "value": "973 TFLOPS",
      "field": "Dense FP8",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P12",
        "E18",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "product-listed",
      "scope": "950dt"
    },
    "accelerator.950dt.9": {
      "value": "MXFP4 1946 TFLOPS",
      "field": "Dense FP6 / FP4",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P12",
        "E18",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "product-listed",
      "scope": "950dt"
    },
    "accelerator.950dt.10": {
      "value": "n/d",
      "field": "FP64 vector / matrix",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P12",
        "E18",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "product-listed",
      "scope": "950dt"
    },
    "accelerator.950dt.11": {
      "value": "144 GB max; 4 TB/s; 96 GB variant",
      "field": "Memory: type; stacks; GB; TB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P12",
        "E18",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "product-listed",
      "scope": "950dt"
    },
    "accelerator.950dt.12": {
      "value": "128 MB",
      "field": "LLC / SRAM",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P12",
        "E18",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "product-listed",
      "scope": "950dt"
    },
    "accelerator.950dt.13": {
      "value": "18 ×4 ports; 56 GB/s raw/link/direction; 1008 GB/s total/direction before port reuse",
      "field": "Scale-up: links; GB/s per direction; domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P12",
        "E18",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "product-listed",
      "scope": "950dt"
    },
    "accelerator.950dt.14": {
      "value": "PCIe 5.0 ×16",
      "field": "Host link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P12",
        "E18",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "product-listed",
      "scope": "950dt"
    },
    "accelerator.950dt.15": {
      "value": "n/d",
      "field": "Power / cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P12",
        "E18",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "product-listed",
      "scope": "950dt"
    },
    "accelerator.950dt.16": {
      "value": "Chip; several bins",
      "field": "Form factor",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P12",
        "E18",
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "product-listed",
      "scope": "950dt"
    },
    "accelerator.960.0": {
      "value": "Ascend 960DT / PR",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11",
        "E03"
      ],
      "disclosure_date": "2026-09",
      "status": "roadmap",
      "scope": "960"
    },
    "accelerator.960.1": {
      "value": "n/d",
      "field": "Architecture",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11",
        "E03"
      ],
      "disclosure_date": "2026-09",
      "status": "roadmap",
      "scope": "960"
    },
    "accelerator.960.2": {
      "value": "DT Q1 2027; PR Q3 2027 readiness",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11",
        "E03"
      ],
      "disclosure_date": "2026-09",
      "status": "roadmap",
      "scope": "960"
    },
    "accelerator.960.3": {
      "value": "Roadmap",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11",
        "E03"
      ],
      "disclosure_date": "2026-09",
      "status": "roadmap",
      "scope": "960"
    },
    "accelerator.960.4": {
      "value": "n/d",
      "field": "Process",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11",
        "E03"
      ],
      "disclosure_date": "2026-09",
      "status": "roadmap",
      "scope": "960"
    },
    "accelerator.960.5": {
      "value": "n/d",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11",
        "E03"
      ],
      "disclosure_date": "2026-09",
      "status": "roadmap",
      "scope": "960"
    },
    "accelerator.960.6": {
      "value": "n/d",
      "field": "Compute units",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11",
        "E03"
      ],
      "disclosure_date": "2026-09",
      "status": "roadmap",
      "scope": "960"
    },
    "accelerator.960.7": {
      "value": "n/d",
      "field": "Dense BF16",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11",
        "E03"
      ],
      "disclosure_date": "2026-09",
      "status": "roadmap",
      "scope": "960"
    },
    "accelerator.960.8": {
      "value": "n/d",
      "field": "Dense FP8",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11",
        "E03"
      ],
      "disclosure_date": "2026-09",
      "status": "roadmap",
      "scope": "960"
    },
    "accelerator.960.9": {
      "value": "n/d",
      "field": "Dense FP6 / FP4",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11",
        "E03"
      ],
      "disclosure_date": "2026-09",
      "status": "roadmap",
      "scope": "960"
    },
    "accelerator.960.10": {
      "value": "n/d",
      "field": "FP64 vector / matrix",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11",
        "E03"
      ],
      "disclosure_date": "2026-09",
      "status": "roadmap",
      "scope": "960"
    },
    "accelerator.960.11": {
      "value": "n/d",
      "field": "Memory: type; stacks; GB; TB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11",
        "E03"
      ],
      "disclosure_date": "2026-09",
      "status": "roadmap",
      "scope": "960"
    },
    "accelerator.960.12": {
      "value": "n/d",
      "field": "LLC / SRAM",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11",
        "E03"
      ],
      "disclosure_date": "2026-09",
      "status": "roadmap",
      "scope": "960"
    },
    "accelerator.960.13": {
      "value": "n/d",
      "field": "Scale-up: links; GB/s per direction; domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11",
        "E03"
      ],
      "disclosure_date": "2026-09",
      "status": "roadmap",
      "scope": "960"
    },
    "accelerator.960.14": {
      "value": "n/d",
      "field": "Host link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11",
        "E03"
      ],
      "disclosure_date": "2026-09",
      "status": "roadmap",
      "scope": "960"
    },
    "accelerator.960.15": {
      "value": "n/d",
      "field": "Power / cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11",
        "E03"
      ],
      "disclosure_date": "2026-09",
      "status": "roadmap",
      "scope": "960"
    },
    "accelerator.960.16": {
      "value": "Future chips; Atlas 960E system announced",
      "field": "Form factor",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11",
        "E03"
      ],
      "disclosure_date": "2026-09",
      "status": "roadmap",
      "scope": "960"
    },
    "interconnect.kpdd.0": {
      "value": "Kunpeng 920 D2D",
      "field": "Interconnect",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "kpdd"
    },
    "interconnect.kpdd.1": {
      "value": "2019",
      "field": "Year / generation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "kpdd"
    },
    "interconnect.kpdd.2": {
      "value": "n/d",
      "field": "Lane rate",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "kpdd"
    },
    "interconnect.kpdd.3": {
      "value": "n/d",
      "field": "Lanes / link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "kpdd"
    },
    "interconnect.kpdd.4": {
      "value": "400 GB/s quoted aggregate; direction n/d",
      "field": "GB/s per link per direction",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "kpdd"
    },
    "interconnect.kpdd.5": {
      "value": "n/d",
      "field": "Links / device",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "kpdd"
    },
    "interconnect.kpdd.6": {
      "value": "Compute / I/O chiplet links",
      "field": "Topology",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "kpdd"
    },
    "interconnect.kpdd.7": {
      "value": "Processor package",
      "field": "Domain limit",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "kpdd"
    },
    "interconnect.kpdd.8": {
      "value": "Coherent on-package fabric",
      "field": "Coherence / semantics",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "kpdd"
    },
    "interconnect.hccs.0": {
      "value": "Ascend 910 HCCS",
      "field": "Interconnect",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "hccs"
    },
    "interconnect.hccs.1": {
      "value": "2019",
      "field": "Year / generation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "hccs"
    },
    "interconnect.hccs.2": {
      "value": "n/d",
      "field": "Lane rate",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "hccs"
    },
    "interconnect.hccs.3": {
      "value": "n/d",
      "field": "Lanes / link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "hccs"
    },
    "interconnect.hccs.4": {
      "value": "240 Gb/s = 30 GB/s quoted link; direction n/d",
      "field": "GB/s per link per direction",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "hccs"
    },
    "interconnect.hccs.5": {
      "value": "3",
      "field": "Links / device",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "hccs"
    },
    "interconnect.hccs.6": {
      "value": "Board/system dependent",
      "field": "Topology",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "hccs"
    },
    "interconnect.hccs.7": {
      "value": "n/d",
      "field": "Domain limit",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "hccs"
    },
    "interconnect.hccs.8": {
      "value": "Accelerator communication; do not assume general CPU coherence",
      "field": "Coherence / semantics",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "hccs"
    },
    "interconnect.ub1.0": {
      "value": "UnifiedBus 1.0",
      "field": "Interconnect",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "ub1"
    },
    "interconnect.ub1.1": {
      "value": "2025",
      "field": "Year / generation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "ub1"
    },
    "interconnect.ub1.2": {
      "value": "n/d",
      "field": "Lane rate",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "ub1"
    },
    "interconnect.ub1.3": {
      "value": "n/d",
      "field": "Lanes / link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "ub1"
    },
    "interconnect.ub1.4": {
      "value": "n/d",
      "field": "GB/s per link per direction",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "ub1"
    },
    "interconnect.ub1.5": {
      "value": "7 transceivers per 910C die",
      "field": "Links / device",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "ub1"
    },
    "interconnect.ub1.6": {
      "value": "Two-tier switched; 7 subplanes",
      "field": "Topology",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "ub1"
    },
    "interconnect.ub1.7": {
      "value": "384 NPUs",
      "field": "Domain limit",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "ub1"
    },
    "interconnect.ub1.8": {
      "value": "Peer access; pooled CPU/NPU memory",
      "field": "Coherence / semantics",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "ub1"
    },
    "interconnect.ub2.0": {
      "value": "UnifiedBus 2.0 / 950",
      "field": "Interconnect",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "ub2"
    },
    "interconnect.ub2.1": {
      "value": "2026",
      "field": "Year / generation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "ub2"
    },
    "interconnect.ub2.2": {
      "value": "112 Gb/s",
      "field": "Lane rate",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "ub2"
    },
    "interconnect.ub2.3": {
      "value": "4",
      "field": "Lanes / link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "ub2"
    },
    "interconnect.ub2.4": {
      "value": "56 raw; 1008 aggregate/device",
      "field": "GB/s per link per direction",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "ub2"
    },
    "interconnect.ub2.5": {
      "value": "18",
      "field": "Links / device",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "ub2"
    },
    "interconnect.ub2.6": {
      "value": "nD mesh / Clos",
      "field": "Topology",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "ub2"
    },
    "interconnect.ub2.7": {
      "value": "8,192 NPUs",
      "field": "Domain limit",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "ub2"
    },
    "interconnect.ub2.8": {
      "value": "URMA; load/store/atomic; on-package coherence separately documented",
      "field": "Coherence / semantics",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "ub2"
    },
    "interconnect.350link.0": {
      "value": "Atlas 350 UB",
      "field": "Interconnect",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "350link"
    },
    "interconnect.350link.1": {
      "value": "2026",
      "field": "Year / generation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "350link"
    },
    "interconnect.350link.2": {
      "value": "n/d",
      "field": "Lane rate",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "350link"
    },
    "interconnect.350link.3": {
      "value": "4",
      "field": "Lanes / link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "350link"
    },
    "interconnect.350link.4": {
      "value": "53 from card bidirectional rating",
      "field": "GB/s per link per direction",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "350link"
    },
    "interconnect.350link.5": {
      "value": "3 in 4-card mesh; 4 in 2-card mode",
      "field": "Links / device",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "350link"
    },
    "interconnect.350link.6": {
      "value": "Full mesh / paired",
      "field": "Topology",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "350link"
    },
    "interconnect.350link.7": {
      "value": "4 / 2 cards",
      "field": "Domain limit",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "350link"
    },
    "interconnect.350link.8": {
      "value": "Card UB links",
      "field": "Coherence / semantics",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "350link"
    },
    "interconnect.uboe.0": {
      "value": "950 UBoE",
      "field": "Interconnect",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "uboe"
    },
    "interconnect.uboe.1": {
      "value": "2026",
      "field": "Year / generation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "uboe"
    },
    "interconnect.uboe.2": {
      "value": "n/d",
      "field": "Lane rate",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "uboe"
    },
    "interconnect.uboe.3": {
      "value": "n/d",
      "field": "Lanes / link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "uboe"
    },
    "interconnect.uboe.4": {
      "value": "50 raw per 400G port",
      "field": "GB/s per link per direction",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "uboe"
    },
    "interconnect.uboe.5": {
      "value": "2",
      "field": "Links / device",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "uboe"
    },
    "interconnect.uboe.6": {
      "value": "Ethernet fabric",
      "field": "Topology",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "uboe"
    },
    "interconnect.uboe.7": {
      "value": "Cluster architecture >128K cards",
      "field": "Domain limit",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "uboe"
    },
    "interconnect.uboe.8": {
      "value": "UB over Ethernet; consumes shared ports",
      "field": "Coherence / semantics",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "uboe"
    },
    "interconnect.optical.0": {
      "value": "2026 UB optical device",
      "field": "Interconnect",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E04"
      ],
      "disclosure_date": "2026-09",
      "status": "disclosed",
      "scope": "optical"
    },
    "interconnect.optical.1": {
      "value": "2026",
      "field": "Year / generation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E04"
      ],
      "disclosure_date": "2026-09",
      "status": "disclosed",
      "scope": "optical"
    },
    "interconnect.optical.2": {
      "value": "1.6 Tb/s per port",
      "field": "Lane rate",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E04"
      ],
      "disclosure_date": "2026-09",
      "status": "disclosed",
      "scope": "optical"
    },
    "interconnect.optical.3": {
      "value": "n/d",
      "field": "Lanes / link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E04"
      ],
      "disclosure_date": "2026-09",
      "status": "disclosed",
      "scope": "optical"
    },
    "interconnect.optical.4": {
      "value": "200 raw/port; direction basis of 280T total unspecified",
      "field": "GB/s per link per direction",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E04"
      ],
      "disclosure_date": "2026-09",
      "status": "disclosed",
      "scope": "optical"
    },
    "interconnect.optical.5": {
      "value": "176",
      "field": "Links / device",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E04"
      ],
      "disclosure_date": "2026-09",
      "status": "disclosed",
      "scope": "optical"
    },
    "interconnect.optical.6": {
      "value": "Inter-cabinet optical fabric",
      "field": "Topology",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E04"
      ],
      "disclosure_date": "2026-09",
      "status": "disclosed",
      "scope": "optical"
    },
    "interconnect.optical.7": {
      "value": "System-dependent",
      "field": "Domain limit",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E04"
      ],
      "disclosure_date": "2026-09",
      "status": "disclosed",
      "scope": "optical"
    },
    "interconnect.optical.8": {
      "value": "UnifiedBus; advertised RTT 2 µs",
      "field": "Coherence / semantics",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E04"
      ],
      "disclosure_date": "2026-09",
      "status": "disclosed",
      "scope": "optical"
    },
    "network.sp681.0": {
      "value": "SP681",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp681"
    },
    "network.sp681.1": {
      "value": "Current portfolio; GA n/d",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp681"
    },
    "network.sp681.2": {
      "value": "Shipping / available",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp681"
    },
    "network.sp681.3": {
      "value": "NIC",
      "field": "Class",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp681"
    },
    "network.sp681.4": {
      "value": "2 ×25GE",
      "field": "Ports × speed",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp681"
    },
    "network.sp681.5": {
      "value": "n/d",
      "field": "SerDes",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp681"
    },
    "network.sp681.6": {
      "value": "PCIe 3.0 ×8",
      "field": "Host interface",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp681"
    },
    "network.sp681.7": {
      "value": "n/d",
      "field": "Programmable engine",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp681"
    },
    "network.sp681.8": {
      "value": "n/d",
      "field": "Embedded CPU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp681"
    },
    "network.sp681.9": {
      "value": "n/d",
      "field": "On-card memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp681"
    },
    "network.sp681.10": {
      "value": "RoCE v2",
      "field": "Transport / RDMA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp681"
    },
    "network.sp681.11": {
      "value": "PFC / ETS",
      "field": "Congestion control",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp681"
    },
    "network.sp681.12": {
      "value": "Checksum; virtualization; network offload",
      "field": "Key offloads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp681"
    },
    "network.sp681.13": {
      "value": "n/d",
      "field": "Power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp681"
    },
    "network.sp670.0": {
      "value": "SP670",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp670"
    },
    "network.sp670.1": {
      "value": "Current portfolio; GA n/d",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp670"
    },
    "network.sp670.2": {
      "value": "Shipping / available",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp670"
    },
    "network.sp670.3": {
      "value": "NIC",
      "field": "Class",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp670"
    },
    "network.sp670.4": {
      "value": "2 ×100GE",
      "field": "Ports × speed",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp670"
    },
    "network.sp670.5": {
      "value": "n/d",
      "field": "SerDes",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp670"
    },
    "network.sp670.6": {
      "value": "PCIe 4.0 ×16",
      "field": "Host interface",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp670"
    },
    "network.sp670.7": {
      "value": "Hi1822; engine ISA n/d",
      "field": "Programmable engine",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp670"
    },
    "network.sp670.8": {
      "value": "n/d",
      "field": "Embedded CPU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp670"
    },
    "network.sp670.9": {
      "value": "n/d",
      "field": "On-card memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp670"
    },
    "network.sp670.10": {
      "value": "RoCE v2",
      "field": "Transport / RDMA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp670"
    },
    "network.sp670.11": {
      "value": "PFC / ETS",
      "field": "Congestion control",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp670"
    },
    "network.sp670.12": {
      "value": "Virtualization and network offload",
      "field": "Key offloads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp670"
    },
    "network.sp670.13": {
      "value": "n/d",
      "field": "Power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp670"
    },
    "network.sp680.0": {
      "value": "SP680 / SP623Q",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp680"
    },
    "network.sp680.1": {
      "value": "Current portfolio; GA n/d",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp680"
    },
    "network.sp680.2": {
      "value": "Shipping / available",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp680"
    },
    "network.sp680.3": {
      "value": "NIC / SmartNIC",
      "field": "Class",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp680"
    },
    "network.sp680.4": {
      "value": "4 ×25GE",
      "field": "Ports × speed",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp680"
    },
    "network.sp680.5": {
      "value": "n/d",
      "field": "SerDes",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp680"
    },
    "network.sp680.6": {
      "value": "PCIe 4.0 ×16",
      "field": "Host interface",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp680"
    },
    "network.sp680.7": {
      "value": "Hi1822; DPU Solution ecosystem",
      "field": "Programmable engine",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp680"
    },
    "network.sp680.8": {
      "value": "n/d",
      "field": "Embedded CPU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp680"
    },
    "network.sp680.9": {
      "value": "n/d",
      "field": "On-card memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp680"
    },
    "network.sp680.10": {
      "value": "Ethernet; RoCE depends on model",
      "field": "Transport / RDMA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp680"
    },
    "network.sp680.11": {
      "value": "PFC / ETS",
      "field": "Congestion control",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp680"
    },
    "network.sp680.12": {
      "value": "OVS / DPI / virtualization ecosystem",
      "field": "Key offloads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp680"
    },
    "network.sp680.13": {
      "value": "n/d",
      "field": "Power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P06"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp680"
    },
    "network.sp923.0": {
      "value": "SP923Q / SP900",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "P05"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp923"
    },
    "network.sp923.1": {
      "value": "Current product brief; GA n/d",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "P05"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp923"
    },
    "network.sp923.2": {
      "value": "Shipping / available",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "P05"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp923"
    },
    "network.sp923.3": {
      "value": "DPU",
      "field": "Class",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "P05"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp923"
    },
    "network.sp923.4": {
      "value": "4 ×25GE",
      "field": "Ports × speed",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "P05"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp923"
    },
    "network.sp923.5": {
      "value": "n/d",
      "field": "SerDes",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "P05"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp923"
    },
    "network.sp923.6": {
      "value": "PCIe 4.0 ×16",
      "field": "Host interface",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "P05"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp923"
    },
    "network.sp923.7": {
      "value": "DPAK",
      "field": "Programmable engine",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "P05"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp923"
    },
    "network.sp923.8": {
      "value": "Hi1822; 24 cores",
      "field": "Embedded CPU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "P05"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp923"
    },
    "network.sp923.9": {
      "value": "32 GB DDR4-2400; 4 channels",
      "field": "On-card memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "P05"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp923"
    },
    "network.sp923.10": {
      "value": "Ethernet; storage/network offload",
      "field": "Transport / RDMA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "P05"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp923"
    },
    "network.sp923.11": {
      "value": "PFC / ETS",
      "field": "Congestion control",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "P05"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp923"
    },
    "network.sp923.12": {
      "value": "Bare-metal network/storage; management",
      "field": "Key offloads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "P05"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp923"
    },
    "network.sp923.13": {
      "value": "n/d",
      "field": "Power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "P05"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp923"
    },
    "network.qingtian.0": {
      "value": "QingTian card",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P07",
        "R02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "qingtian"
    },
    "network.qingtian.1": {
      "value": "2025 documented system",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P07",
        "R02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "qingtian"
    },
    "network.qingtian.2": {
      "value": "Shipping / available",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P07",
        "R02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "qingtian"
    },
    "network.qingtian.3": {
      "value": "Cloud infrastructure DPU",
      "field": "Class",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P07",
        "R02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "qingtian"
    },
    "network.qingtian.4": {
      "value": "n/d",
      "field": "Ports × speed",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P07",
        "R02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "qingtian"
    },
    "network.qingtian.5": {
      "value": "n/d",
      "field": "SerDes",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P07",
        "R02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "qingtian"
    },
    "network.qingtian.6": {
      "value": "n/d",
      "field": "Host interface",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P07",
        "R02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "qingtian"
    },
    "network.qingtian.7": {
      "value": "n/d",
      "field": "Programmable engine",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P07",
        "R02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "qingtian"
    },
    "network.qingtian.8": {
      "value": "n/d",
      "field": "Embedded CPU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P07",
        "R02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "qingtian"
    },
    "network.qingtian.9": {
      "value": "n/d",
      "field": "On-card memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P07",
        "R02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "qingtian"
    },
    "network.qingtian.10": {
      "value": "VPC / Ethernet; UB integration by platform",
      "field": "Transport / RDMA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P07",
        "R02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "qingtian"
    },
    "network.qingtian.11": {
      "value": "n/d",
      "field": "Congestion control",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P07",
        "R02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "qingtian"
    },
    "network.qingtian.12": {
      "value": "Virtualization, I/O offload, isolation, trust",
      "field": "Key offloads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P07",
        "R02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "qingtian"
    },
    "network.qingtian.13": {
      "value": "n/d",
      "field": "Power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P07",
        "R02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "qingtian"
    },
    "network.sp230.0": {
      "value": "SP230",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2026-07",
      "status": "announced",
      "scope": "sp230"
    },
    "network.sp230.1": {
      "value": "WAIC 2026",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2026-07",
      "status": "announced",
      "scope": "sp230"
    },
    "network.sp230.2": {
      "value": "Announced; GA n/d",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2026-07",
      "status": "announced",
      "scope": "sp230"
    },
    "network.sp230.3": {
      "value": "Standard NIC",
      "field": "Class",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2026-07",
      "status": "announced",
      "scope": "sp230"
    },
    "network.sp230.4": {
      "value": "25–200GE family; port count n/d",
      "field": "Ports × speed",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2026-07",
      "status": "announced",
      "scope": "sp230"
    },
    "network.sp230.5": {
      "value": "n/d",
      "field": "SerDes",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2026-07",
      "status": "announced",
      "scope": "sp230"
    },
    "network.sp230.6": {
      "value": "n/d",
      "field": "Host interface",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2026-07",
      "status": "announced",
      "scope": "sp230"
    },
    "network.sp230.7": {
      "value": "n/d",
      "field": "Programmable engine",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2026-07",
      "status": "announced",
      "scope": "sp230"
    },
    "network.sp230.8": {
      "value": "n/d",
      "field": "Embedded CPU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2026-07",
      "status": "announced",
      "scope": "sp230"
    },
    "network.sp230.9": {
      "value": "n/d",
      "field": "On-card memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2026-07",
      "status": "announced",
      "scope": "sp230"
    },
    "network.sp230.10": {
      "value": "Ethernet",
      "field": "Transport / RDMA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2026-07",
      "status": "announced",
      "scope": "sp230"
    },
    "network.sp230.11": {
      "value": "n/d",
      "field": "Congestion control",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2026-07",
      "status": "announced",
      "scope": "sp230"
    },
    "network.sp230.12": {
      "value": "Host networking",
      "field": "Key offloads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2026-07",
      "status": "announced",
      "scope": "sp230"
    },
    "network.sp230.13": {
      "value": "n/d",
      "field": "Power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2026-07",
      "status": "announced",
      "scope": "sp230"
    },
    "network.sp560.0": {
      "value": "SP560 AI NIC",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2026-07",
      "status": "announced",
      "scope": "sp560"
    },
    "network.sp560.1": {
      "value": "WAIC 2026",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2026-07",
      "status": "announced",
      "scope": "sp560"
    },
    "network.sp560.2": {
      "value": "Announced; GA n/d",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2026-07",
      "status": "announced",
      "scope": "sp560"
    },
    "network.sp560.3": {
      "value": "AI NIC",
      "field": "Class",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2026-07",
      "status": "announced",
      "scope": "sp560"
    },
    "network.sp560.4": {
      "value": "800G advertised; port mapping n/d",
      "field": "Ports × speed",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2026-07",
      "status": "announced",
      "scope": "sp560"
    },
    "network.sp560.5": {
      "value": "n/d",
      "field": "SerDes",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2026-07",
      "status": "announced",
      "scope": "sp560"
    },
    "network.sp560.6": {
      "value": "UnifiedBus + PCIe",
      "field": "Host interface",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2026-07",
      "status": "announced",
      "scope": "sp560"
    },
    "network.sp560.7": {
      "value": "Programmable protocol; ISA n/d",
      "field": "Programmable engine",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2026-07",
      "status": "announced",
      "scope": "sp560"
    },
    "network.sp560.8": {
      "value": "n/d",
      "field": "Embedded CPU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2026-07",
      "status": "announced",
      "scope": "sp560"
    },
    "network.sp560.9": {
      "value": "n/d",
      "field": "On-card memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2026-07",
      "status": "announced",
      "scope": "sp560"
    },
    "network.sp560.10": {
      "value": "RDMA",
      "field": "Transport / RDMA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2026-07",
      "status": "announced",
      "scope": "sp560"
    },
    "network.sp560.11": {
      "value": "n/d",
      "field": "Congestion control",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2026-07",
      "status": "announced",
      "scope": "sp560"
    },
    "network.sp560.12": {
      "value": "Direct NPU/GPU memory access; collective submission",
      "field": "Key offloads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2026-07",
      "status": "announced",
      "scope": "sp560"
    },
    "network.sp560.13": {
      "value": "n/d",
      "field": "Power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E13"
      ],
      "disclosure_date": "2026-07",
      "status": "announced",
      "scope": "sp560"
    },
    "systems.atlas19.0": {
      "value": "Atlas 2019 systems",
      "field": "Platform",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "E07"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "atlas19"
    },
    "systems.atlas19.1": {
      "value": "2019",
      "field": "Year / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "E07"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "atlas19"
    },
    "systems.atlas19.2": {
      "value": "Configuration-dependent Ascend nodes",
      "field": "CPU / accelerator count",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "E07"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "atlas19"
    },
    "systems.atlas19.3": {
      "value": "HCCS-connected nodes",
      "field": "Scale-up domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "E07"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "atlas19"
    },
    "systems.atlas19.4": {
      "value": "910 integrates 2 ×100Gb/s Ethernet; 25 GB/s raw aggregate",
      "field": "Scale-out per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "E07"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "atlas19"
    },
    "systems.atlas19.5": {
      "value": "n/d",
      "field": "Rack power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "E07"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "atlas19"
    },
    "systems.atlas19.6": {
      "value": "System-dependent",
      "field": "Cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "E07"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "atlas19"
    },
    "systems.a2.0": {
      "value": "Atlas A2",
      "field": "Platform",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12"
      ],
      "disclosure_date": "2023",
      "status": "disclosed",
      "scope": "a2"
    },
    "systems.a2.1": {
      "value": "2023-era",
      "field": "Year / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12"
      ],
      "disclosure_date": "2023",
      "status": "disclosed",
      "scope": "a2"
    },
    "systems.a2.2": {
      "value": "Server/module-dependent",
      "field": "CPU / accelerator count",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12"
      ],
      "disclosure_date": "2023",
      "status": "disclosed",
      "scope": "a2"
    },
    "systems.a2.3": {
      "value": "HCCS; system-dependent",
      "field": "Scale-up domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12"
      ],
      "disclosure_date": "2023",
      "status": "disclosed",
      "scope": "a2"
    },
    "systems.a2.4": {
      "value": "n/d",
      "field": "Scale-out per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12"
      ],
      "disclosure_date": "2023",
      "status": "disclosed",
      "scope": "a2"
    },
    "systems.a2.5": {
      "value": "n/d",
      "field": "Rack power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12"
      ],
      "disclosure_date": "2023",
      "status": "disclosed",
      "scope": "a2"
    },
    "systems.a2.6": {
      "value": "Air / liquid by product",
      "field": "Cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P12"
      ],
      "disclosure_date": "2023",
      "status": "disclosed",
      "scope": "a2"
    },
    "systems.cm384.0": {
      "value": "CloudMatrix384 / Atlas 900 A3",
      "field": "Platform",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02",
        "E05"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "cm384"
    },
    "systems.cm384.1": {
      "value": "2025",
      "field": "Year / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02",
        "E05"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "cm384"
    },
    "systems.cm384.2": {
      "value": "192 CPUs + 384 NPUs; 48 nodes",
      "field": "CPU / accelerator count",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02",
        "E05"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "cm384"
    },
    "systems.cm384.3": {
      "value": "384 NPUs",
      "field": "Scale-up domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02",
        "E05"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "cm384"
    },
    "systems.cm384.4": {
      "value": "Dedicated RoCE per NPU die; rate n/d",
      "field": "Scale-out per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02",
        "E05"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "cm384"
    },
    "systems.cm384.5": {
      "value": "n/d",
      "field": "Rack power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02",
        "E05"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "cm384"
    },
    "systems.cm384.6": {
      "value": "Liquid-cooled SuperPoD",
      "field": "Cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02",
        "E05"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "cm384"
    },
    "systems.950road.0": {
      "value": "Atlas 950 2025 design point",
      "field": "Platform",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "roadmap",
      "scope": "950road"
    },
    "systems.950road.1": {
      "value": "2025 roadmap for 2026",
      "field": "Year / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "roadmap",
      "scope": "950road"
    },
    "systems.950road.2": {
      "value": "8,192 NPUs; 160 cabinets",
      "field": "CPU / accelerator count",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "roadmap",
      "scope": "950road"
    },
    "systems.950road.3": {
      "value": "8,192 NPUs",
      "field": "Scale-up domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "roadmap",
      "scope": "950road"
    },
    "systems.950road.4": {
      "value": "UBoE / RoCE; port allocation dependent",
      "field": "Scale-out per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "roadmap",
      "scope": "950road"
    },
    "systems.950road.5": {
      "value": "n/d",
      "field": "Rack power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "roadmap",
      "scope": "950road"
    },
    "systems.950road.6": {
      "value": "Liquid",
      "field": "Cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2025",
      "status": "roadmap",
      "scope": "950road"
    },
    "systems.950waic.0": {
      "value": "Atlas 950 WAIC configuration",
      "field": "Platform",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E18"
      ],
      "disclosure_date": "2026-07",
      "status": "disclosed",
      "scope": "950waic"
    },
    "systems.950waic.1": {
      "value": "2026-07",
      "field": "Year / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E18"
      ],
      "disclosure_date": "2026-07",
      "status": "disclosed",
      "scope": "950waic"
    },
    "systems.950waic.2": {
      "value": "1,024 NPUs",
      "field": "CPU / accelerator count",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E18"
      ],
      "disclosure_date": "2026-07",
      "status": "disclosed",
      "scope": "950waic"
    },
    "systems.950waic.3": {
      "value": "1,024 NPUs",
      "field": "Scale-up domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E18"
      ],
      "disclosure_date": "2026-07",
      "status": "disclosed",
      "scope": "950waic"
    },
    "systems.950waic.4": {
      "value": "n/d",
      "field": "Scale-out per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E18"
      ],
      "disclosure_date": "2026-07",
      "status": "disclosed",
      "scope": "950waic"
    },
    "systems.950waic.5": {
      "value": "n/d",
      "field": "Rack power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E18"
      ],
      "disclosure_date": "2026-07",
      "status": "disclosed",
      "scope": "950waic"
    },
    "systems.950waic.6": {
      "value": "Liquid",
      "field": "Cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E18"
      ],
      "disclosure_date": "2026-07",
      "status": "disclosed",
      "scope": "950waic"
    },
    "systems.850.0": {
      "value": "Atlas 850E",
      "field": "Platform",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E18"
      ],
      "disclosure_date": "2026-07",
      "status": "available",
      "scope": "850"
    },
    "systems.850.1": {
      "value": "2026-07",
      "field": "Year / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E18"
      ],
      "disclosure_date": "2026-07",
      "status": "available",
      "scope": "850"
    },
    "systems.850.2": {
      "value": "Up to 96 cards",
      "field": "CPU / accelerator count",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E18"
      ],
      "disclosure_date": "2026-07",
      "status": "available",
      "scope": "850"
    },
    "systems.850.3": {
      "value": "96 cards",
      "field": "Scale-up domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E18"
      ],
      "disclosure_date": "2026-07",
      "status": "available",
      "scope": "850"
    },
    "systems.850.4": {
      "value": "n/d",
      "field": "Scale-out per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E18"
      ],
      "disclosure_date": "2026-07",
      "status": "available",
      "scope": "850"
    },
    "systems.850.5": {
      "value": "n/d",
      "field": "Rack power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E18"
      ],
      "disclosure_date": "2026-07",
      "status": "available",
      "scope": "850"
    },
    "systems.850.6": {
      "value": "Air; VCE phase-change technology",
      "field": "Cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E18"
      ],
      "disclosure_date": "2026-07",
      "status": "available",
      "scope": "850"
    },
    "systems.960e.0": {
      "value": "Atlas 960E",
      "field": "Platform",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "E11"
      ],
      "disclosure_date": "2026-09",
      "status": "announced",
      "scope": "960e"
    },
    "systems.960e.1": {
      "value": "2026 announcement; 960 chips 2027",
      "field": "Year / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "E11"
      ],
      "disclosure_date": "2026-09",
      "status": "announced",
      "scope": "960e"
    },
    "systems.960e.2": {
      "value": "4,096 NPUs",
      "field": "CPU / accelerator count",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "E11"
      ],
      "disclosure_date": "2026-09",
      "status": "announced",
      "scope": "960e"
    },
    "systems.960e.3": {
      "value": "4,096 NPUs",
      "field": "Scale-up domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "E11"
      ],
      "disclosure_date": "2026-09",
      "status": "announced",
      "scope": "960e"
    },
    "systems.960e.4": {
      "value": "UB network / RoCE; per-NPU rate n/d",
      "field": "Scale-out per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "E11"
      ],
      "disclosure_date": "2026-09",
      "status": "announced",
      "scope": "960e"
    },
    "systems.960e.5": {
      "value": "n/d",
      "field": "Rack power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "E11"
      ],
      "disclosure_date": "2026-09",
      "status": "announced",
      "scope": "960e"
    },
    "systems.960e.6": {
      "value": "Full liquid; NPO",
      "field": "Cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "E11"
      ],
      "disclosure_date": "2026-09",
      "status": "announced",
      "scope": "960e"
    },
    "systems.kp950pod.0": {
      "value": "Kunpeng SuperPoD update",
      "field": "Platform",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11"
      ],
      "disclosure_date": "2026-09",
      "status": "announced",
      "scope": "kp950pod"
    },
    "systems.kp950pod.1": {
      "value": "2026-09",
      "field": "Year / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11"
      ],
      "disclosure_date": "2026-09",
      "status": "announced",
      "scope": "kp950pod"
    },
    "systems.kp950pod.2": {
      "value": "Up to 4,096 nodes",
      "field": "CPU / accelerator count",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11"
      ],
      "disclosure_date": "2026-09",
      "status": "announced",
      "scope": "kp950pod"
    },
    "systems.kp950pod.3": {
      "value": "256 TB unified pool disclosed",
      "field": "Scale-up domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11"
      ],
      "disclosure_date": "2026-09",
      "status": "announced",
      "scope": "kp950pod"
    },
    "systems.kp950pod.4": {
      "value": "n/a",
      "field": "Scale-out per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11"
      ],
      "disclosure_date": "2026-09",
      "status": "announced",
      "scope": "kp950pod"
    },
    "systems.kp950pod.5": {
      "value": "n/d",
      "field": "Rack power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11"
      ],
      "disclosure_date": "2026-09",
      "status": "announced",
      "scope": "kp950pod"
    },
    "systems.kp950pod.6": {
      "value": "n/d",
      "field": "Cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11"
      ],
      "disclosure_date": "2026-09",
      "status": "announced",
      "scope": "kp950pod"
    },
    "software.initial.0": {
      "value": "CANN / MindSpore launch",
      "field": "Release / layer",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "E20"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "initial"
    },
    "software.initial.1": {
      "value": "2019",
      "field": "Date",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "E20"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "initial"
    },
    "software.initial.2": {
      "value": "Ascend 310 / 910",
      "field": "Hardware enabled",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "E20"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "initial"
    },
    "software.initial.3": {
      "value": "Graph compilation, operators, runtime and framework",
      "field": "Key features",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "E20"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "initial"
    },
    "software.cann3.0": {
      "value": "CANN 3.0",
      "field": "Release / layer",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E08"
      ],
      "disclosure_date": "2020",
      "status": "disclosed",
      "scope": "cann3"
    },
    "software.cann3.1": {
      "value": "2020",
      "field": "Date",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E08"
      ],
      "disclosure_date": "2020",
      "status": "disclosed",
      "scope": "cann3"
    },
    "software.cann3.2": {
      "value": "Ascend",
      "field": "Hardware enabled",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E08"
      ],
      "disclosure_date": "2020",
      "status": "disclosed",
      "scope": "cann3"
    },
    "software.cann3.3": {
      "value": "Broader developer interfaces and operator optimization",
      "field": "Key features",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E08"
      ],
      "disclosure_date": "2020",
      "status": "disclosed",
      "scope": "cann3"
    },
    "software.ascendc.0": {
      "value": "Ascend C",
      "field": "Release / layer",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "ascendc"
    },
    "software.ascendc.1": {
      "value": "Current documentation",
      "field": "Date",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "ascendc"
    },
    "software.ascendc.2": {
      "value": "Ascend AI cores",
      "field": "Hardware enabled",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "ascendc"
    },
    "software.ascendc.3": {
      "value": "Explicit tiling, queue/buffer management, pipelined compute and transfer",
      "field": "Key features",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "ascendc"
    },
    "software.infer.0": {
      "value": "CloudMatrix-Infer",
      "field": "Release / layer",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "infer"
    },
    "software.infer.1": {
      "value": "2025",
      "field": "Date",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "infer"
    },
    "software.infer.2": {
      "value": "CloudMatrix384",
      "field": "Hardware enabled",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "infer"
    },
    "software.infer.3": {
      "value": "Prefill/decode/cache separation; expert parallelism; INT8 kernels",
      "field": "Key features",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "infer"
    },
    "software.open.0": {
      "value": "CANN / Mind open source",
      "field": "Release / layer",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E09",
        "E18"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "open"
    },
    "software.open.1": {
      "value": "2025–2026",
      "field": "Date",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E09",
        "E18"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "open"
    },
    "software.open.2": {
      "value": "Ascend",
      "field": "Hardware enabled",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E09",
        "E18"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "open"
    },
    "software.open.3": {
      "value": "Compiler/runtime/kernel ecosystem opening; framework integration",
      "field": "Key features",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E09",
        "E18"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "open"
    },
    "software.950soft.0": {
      "value": "DaVinci 3 / STARS 2.0 / CCU",
      "field": "Release / layer",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "950soft"
    },
    "software.950soft.1": {
      "value": "2026",
      "field": "Date",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "950soft"
    },
    "software.950soft.2": {
      "value": "Ascend 950",
      "field": "Hardware enabled",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "950soft"
    },
    "software.950soft.3": {
      "value": "SIMD/SIMT; NDDMA; collective offload; cache hints; low-precision formats",
      "field": "Key features",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "950soft"
    },
    "software.infra.0": {
      "value": "DPAK / QingTian / openEuler",
      "field": "Release / layer",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "P07",
        "P08"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "infra"
    },
    "software.infra.1": {
      "value": "Generation-dependent",
      "field": "Date",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "P07",
        "P08"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "infra"
    },
    "software.infra.2": {
      "value": "Kunpeng / SP900 / cloud",
      "field": "Hardware enabled",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "P07",
        "P08"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "infra"
    },
    "software.infra.3": {
      "value": "Host OS, network/storage offload and tenant isolation",
      "field": "Key features",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "P07",
        "P08"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "infra"
    },
    "bandwidth.early.0": {
      "value": "2015–2018 / 310",
      "field": "Era / reference",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "early"
    },
    "bandwidth.early.1": {
      "value": "Explicit local buffers; numeric rate n/d",
      "field": "On die / die-to-die",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "early"
    },
    "bandwidth.early.2": {
      "value": "LPDDR; board-dependent",
      "field": "Memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "early"
    },
    "bandwidth.early.3": {
      "value": "PCIe; n/d",
      "field": "Host attachment",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "early"
    },
    "bandwidth.early.4": {
      "value": "n/d",
      "field": "Scale-up per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "early"
    },
    "bandwidth.early.5": {
      "value": "n/d",
      "field": "Scale-out per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "early"
    },
    "bandwidth.2019.0": {
      "value": "2019–2022 / 910",
      "field": "Era / reference",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "2019"
    },
    "bandwidth.2019.1": {
      "value": "L2 fabric 4 TB/s; per-AI-core 128 GB/s read + 128 GB/s write",
      "field": "On die / die-to-die",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "2019"
    },
    "bandwidth.2019.2": {
      "value": "~1.2 TB/s HBM2",
      "field": "Memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "2019"
    },
    "bandwidth.2019.3": {
      "value": "PCIe 4.0",
      "field": "Host attachment",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "2019"
    },
    "bandwidth.2019.4": {
      "value": "3 ×240 Gb/s HCCS; direction n/d",
      "field": "Scale-up per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "2019"
    },
    "bandwidth.2019.5": {
      "value": "2 ×100 Gb/s Ethernet = 25 GB/s raw aggregate",
      "field": "Scale-out per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "2019"
    },
    "bandwidth.2025.0": {
      "value": "2023–2025 / 910C",
      "field": "Era / reference",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "2025"
    },
    "bandwidth.2025.1": {
      "value": "Dual compute die; D2D rate n/d",
      "field": "On die / die-to-die",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "2025"
    },
    "bandwidth.2025.2": {
      "value": "8 memory stacks; R02 rate n/d",
      "field": "Memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "2025"
    },
    "bandwidth.2025.3": {
      "value": "Kunpeng / UB",
      "field": "Host attachment",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "2025"
    },
    "bandwidth.2025.4": {
      "value": "7 UB transceivers per die; rate n/d",
      "field": "Scale-up per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "2025"
    },
    "bandwidth.2025.5": {
      "value": "Separate RoCE interface per die; rate n/d",
      "field": "Scale-out per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "2025"
    },
    "bandwidth.950.0": {
      "value": "2026 / maximum 950",
      "field": "Era / reference",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "950"
    },
    "bandwidth.950.1": {
      "value": "2 AI + 2 I/O; D2D rate n/d",
      "field": "On die / die-to-die",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "950"
    },
    "bandwidth.950.2": {
      "value": "PR 1.6; DT 4 TB/s",
      "field": "Memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "950"
    },
    "bandwidth.950.3": {
      "value": "PCIe 5.0 ×16: nominal 64 GB/s/direction",
      "field": "Host attachment",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "950"
    },
    "bandwidth.950.4": {
      "value": "1008 GB/s raw/direction before port reuse",
      "field": "Scale-up per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "950"
    },
    "bandwidth.950.5": {
      "value": "2 ×400G UBoE: 100 GB/s raw aggregate; shared ports",
      "field": "Scale-out per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "950"
    },
    "bandwidth.350.0": {
      "value": "2026 / Atlas 350 card",
      "field": "Era / reference",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14",
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "350"
    },
    "bandwidth.350.1": {
      "value": "28-Cube bin; D2D rate n/d",
      "field": "On die / die-to-die",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14",
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "350"
    },
    "bandwidth.350.2": {
      "value": "1.4 TB/s",
      "field": "Memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14",
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "350"
    },
    "bandwidth.350.3": {
      "value": "PCIe 5.0 ×16: nominal 64 GB/s/direction",
      "field": "Host attachment",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14",
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "350"
    },
    "bandwidth.350.4": {
      "value": "159 GB/s/direction at 4 cards; 212 at 2 cards",
      "field": "Scale-up per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14",
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "350"
    },
    "bandwidth.350.5": {
      "value": "Server NIC-dependent",
      "field": "Scale-out per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14",
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "350"
    },
    "ratios.cpu_bw.0": {
      "value": "Kunpeng 920",
      "field": "Reference",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "cpu_bw"
    },
    "ratios.cpu_bw.1": {
      "value": "8 × 8 × 2.933 / 64",
      "field": "Calculation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "cpu_bw"
    },
    "ratios.cpu_bw.2": {
      "value": "2.933 GB/s/core",
      "field": "Result",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "cpu_bw"
    },
    "ratios.cpu_bw.3": {
      "value": "Theoretical DDR4 payload; controller/workload efficiency excluded",
      "field": "Interpretation / boundary",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "cpu_bw"
    },
    "ratios.cpu_llc.0": {
      "value": "Kunpeng 920",
      "field": "Reference",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "cpu_llc"
    },
    "ratios.cpu_llc.1": {
      "value": "64 MB / 64",
      "field": "Calculation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "cpu_llc"
    },
    "ratios.cpu_llc.2": {
      "value": "1 MB/core",
      "field": "Result",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "cpu_llc"
    },
    "ratios.cpu_llc.3": {
      "value": "Average shared LLC budget, not private allocation",
      "field": "Interpretation / boundary",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "cpu_llc"
    },
    "ratios.910bpf.0": {
      "value": "Ascend 910",
      "field": "Reference",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "910bpf"
    },
    "ratios.910bpf.1": {
      "value": "1.2e12 / 256e12",
      "field": "Calculation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "910bpf"
    },
    "ratios.910bpf.2": {
      "value": "0.00469 byte/FP16 FLOP",
      "field": "Result",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "910bpf"
    },
    "ratios.910bpf.3": {
      "value": "FP16; not a BF16 comparison",
      "field": "Interpretation / boundary",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "910bpf"
    },
    "ratios.pr_bf.0": {
      "value": "950PR max",
      "field": "Reference",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "pr_bf"
    },
    "ratios.pr_bf.1": {
      "value": "1.6e12 / 432e12",
      "field": "Calculation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "pr_bf"
    },
    "ratios.pr_bf.2": {
      "value": "0.00370 byte/BF16 FLOP",
      "field": "Result",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "pr_bf"
    },
    "ratios.pr_bf.3": {
      "value": "Cube-only dense peak",
      "field": "Interpretation / boundary",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "pr_bf"
    },
    "ratios.pr_fp8.0": {
      "value": "950PR max",
      "field": "Reference",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "pr_fp8"
    },
    "ratios.pr_fp8.1": {
      "value": "1.6e12 / 865e12",
      "field": "Calculation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "pr_fp8"
    },
    "ratios.pr_fp8.2": {
      "value": "0.00185 byte/FP8 FLOP",
      "field": "Result",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "pr_fp8"
    },
    "ratios.pr_fp8.3": {
      "value": "Cube-only dense peak",
      "field": "Interpretation / boundary",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "pr_fp8"
    },
    "ratios.dt_bf.0": {
      "value": "950DT max",
      "field": "Reference",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "dt_bf"
    },
    "ratios.dt_bf.1": {
      "value": "4e12 / 486e12",
      "field": "Calculation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "dt_bf"
    },
    "ratios.dt_bf.2": {
      "value": "0.00823 byte/BF16 FLOP",
      "field": "Result",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "dt_bf"
    },
    "ratios.dt_bf.3": {
      "value": "2.22× PR bandwidth per BF16 FLOP",
      "field": "Interpretation / boundary",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "dt_bf"
    },
    "ratios.dt_fp8.0": {
      "value": "950DT max",
      "field": "Reference",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "dt_fp8"
    },
    "ratios.dt_fp8.1": {
      "value": "4e12 / 973e12",
      "field": "Calculation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "dt_fp8"
    },
    "ratios.dt_fp8.2": {
      "value": "0.00411 byte/FP8 FLOP",
      "field": "Result",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "dt_fp8"
    },
    "ratios.dt_fp8.3": {
      "value": "Cube-only dense peak",
      "field": "Interpretation / boundary",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "dt_fp8"
    },
    "ratios.350_ratio.0": {
      "value": "Atlas 350, 4 cards",
      "field": "Reference",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "350_ratio"
    },
    "ratios.350_ratio.1": {
      "value": "159 / 1400",
      "field": "Calculation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "350_ratio"
    },
    "ratios.350_ratio.2": {
      "value": "0.114",
      "field": "Result",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "350_ratio"
    },
    "ratios.350_ratio.3": {
      "value": "One-way card scale-up / HBM; ~11.4%",
      "field": "Interpretation / boundary",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "350_ratio"
    },
    "ratios.350_power.0": {
      "value": "Atlas 350",
      "field": "Reference",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14",
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "350_power"
    },
    "ratios.350_power.1": {
      "value": "378 TFLOPS / 600 W",
      "field": "Calculation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14",
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "350_power"
    },
    "ratios.350_power.2": {
      "value": "0.630 TFLOPS/W",
      "field": "Result",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14",
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "350_power"
    },
    "ratios.350_power.3": {
      "value": "BF16 Cube peak / maximum board power; not measured efficiency",
      "field": "Interpretation / boundary",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P14",
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "350_power"
    },
    "conferences.hc.0": {
      "value": "Hot Chips 31",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "hc"
    },
    "conferences.hc.1": {
      "value": "2019",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "hc"
    },
    "conferences.hc.2": {
      "value": "DaVinci: A Scalable Architecture for Neural Network Computing",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "hc"
    },
    "conferences.hc.3": {
      "value": "Heng Liao; Jiajin Tu; Jing Xia; Xiping Zhou",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "hc"
    },
    "conferences.hc.4": {
      "value": "Ascend 310 / 910",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "hc"
    },
    "conferences.hc.5": {
      "value": "Architecture, die/package, memory, links",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "hc"
    },
    "conferences.hc.6": {
      "value": "C01",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "hc"
    },
    "conferences.hpca.0": {
      "value": "HPCA industry track",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "disclosed",
      "scope": "hpca"
    },
    "conferences.hpca.1": {
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      "field": "Year",
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      "source": [
        "C04",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "disclosed",
      "scope": "hpca"
    },
    "conferences.hpca.2": {
      "value": "Ascend: a scalable and unified architecture for ubiquitous deep neural network computing",
      "field": "Paper / talk / disclosure",
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      "source": [
        "C04",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "disclosed",
      "scope": "hpca"
    },
    "conferences.hpca.3": {
      "value": "Heng Liao et al.",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "disclosed",
      "scope": "hpca"
    },
    "conferences.hpca.4": {
      "value": "Ascend / DaVinci",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "disclosed",
      "scope": "hpca"
    },
    "conferences.hpca.5": {
      "value": "Product architecture; vendor reprint read",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "disclosed",
      "scope": "hpca"
    },
    "conferences.hpca.6": {
      "value": "C04 / P01",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "disclosed",
      "scope": "hpca"
    },
    "conferences.microjournal.0": {
      "value": "IEEE Micro journal",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "C02"
      ],
      "disclosure_date": "2021",
      "status": "disclosed",
      "scope": "microjournal"
    },
    "conferences.microjournal.1": {
      "value": "2021",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "C02"
      ],
      "disclosure_date": "2021",
      "status": "disclosed",
      "scope": "microjournal"
    },
    "conferences.microjournal.2": {
      "value": "HiSilicon Kunpeng 920: First 7-nm Chiplet-Based 64-Core Server CPU With Arm Ecosystem",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "C02"
      ],
      "disclosure_date": "2021",
      "status": "disclosed",
      "scope": "microjournal"
    },
    "conferences.microjournal.3": {
      "value": "Jing Xia; Chuanning Cheng; Xiping Zhou; Yuxing Hu; Peter Chun",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "C02"
      ],
      "disclosure_date": "2021",
      "status": "disclosed",
      "scope": "microjournal"
    },
    "conferences.microjournal.4": {
      "value": "Kunpeng 920",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "C02"
      ],
      "disclosure_date": "2021",
      "status": "disclosed",
      "scope": "microjournal"
    },
    "conferences.microjournal.5": {
      "value": "Core, cache, die partitioning; journal, not MICRO conference",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "C02"
      ],
      "disclosure_date": "2021",
      "status": "disclosed",
      "scope": "microjournal"
    },
    "conferences.microjournal.6": {
      "value": "P01 / C02",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "C02"
      ],
      "disclosure_date": "2021",
      "status": "disclosed",
      "scope": "microjournal"
    },
    "conferences.isscc.0": {
      "value": "ISSCC",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C05"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "isscc"
    },
    "conferences.isscc.1": {
      "value": "2019",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C05"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "isscc"
    },
    "conferences.isscc.2": {
      "value": "6.2: 60Gb/s PAM-4 ADC-DSP Transceiver; 7nm; adaptive power scaling",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C05"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "isscc"
    },
    "conferences.isscc.3": {
      "value": "M.-A. LaCroix et al., Huawei Ottawa",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C05"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "isscc"
    },
    "conferences.isscc.4": {
      "value": "Wireline IP; product adoption unproven",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C05"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "isscc"
    },
    "conferences.isscc.5": {
      "value": "Circuit; program reports 6.9 pJ/b at 32 dB loss",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C05"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "isscc"
    },
    "conferences.isscc.6": {
      "value": "C05",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C05"
      ],
      "disclosure_date": "2019",
      "status": "disclosed",
      "scope": "isscc"
    },
    "conferences.asplos.0": {
      "value": "ASPLOS",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R01"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "asplos"
    },
    "conferences.asplos.1": {
      "value": "2025",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R01"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "asplos"
    },
    "conferences.asplos.2": {
      "value": "Squeezing Operator Performance Potential for the Ascend Architecture",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R01"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "asplos"
    },
    "conferences.asplos.3": {
      "value": "Yuhang Zhou et al.",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R01"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "asplos"
    },
    "conferences.asplos.4": {
      "value": "Ascend",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R01"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "asplos"
    },
    "conferences.asplos.5": {
      "value": "Operator characterization and optimization research",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R01"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "asplos"
    },
    "conferences.asplos.6": {
      "value": "R01",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R01"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "asplos"
    },
    "conferences.micro.0": {
      "value": "MICRO",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R06"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "micro"
    },
    "conferences.micro.1": {
      "value": "2025",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R06"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "micro"
    },
    "conferences.micro.2": {
      "value": "RICH Prefetcher: Storing Rich Information in Memory to Trade Capacity and Bandwidth for Latency Hiding",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R06"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "micro"
    },
    "conferences.micro.3": {
      "value": "Ningzhi Ai et al.",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R06"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "micro"
    },
    "conferences.micro.4": {
      "value": "Related CPU research",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R06"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "micro"
    },
    "conferences.micro.5": {
      "value": "Research; no confirmed Kunpeng adoption",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R06"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "micro"
    },
    "conferences.micro.6": {
      "value": "R06",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R06"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "micro"
    },
    "conferences.isca.0": {
      "value": "ISCA",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R03",
        "R05"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "isca"
    },
    "conferences.isca.1": {
      "value": "2026",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R03",
        "R05"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "isca"
    },
    "conferences.isca.2": {
      "value": "ENEC: A Lossless AI Model Compression Method Enabling Fast Inference on Ascend NPUs",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R03",
        "R05"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "isca"
    },
    "conferences.isca.3": {
      "value": "Jinwu Yang et al.",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R03",
        "R05"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "isca"
    },
    "conferences.isca.4": {
      "value": "Ascend 910B2 study",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R03",
        "R05"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "isca"
    },
    "conferences.isca.5": {
      "value": "Model compression research",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R03",
        "R05"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "isca"
    },
    "conferences.isca.6": {
      "value": "R03 / R05",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R03",
        "R05"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "isca"
    },
    "conferences.rccs.0": {
      "value": "R-CCS Symposium",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03"
      ],
      "disclosure_date": "2020",
      "status": "disclosed",
      "scope": "rccs"
    },
    "conferences.rccs.1": {
      "value": "2020",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03"
      ],
      "disclosure_date": "2020",
      "status": "disclosed",
      "scope": "rccs"
    },
    "conferences.rccs.2": {
      "value": "Kunpeng platform presentation",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03"
      ],
      "disclosure_date": "2020",
      "status": "disclosed",
      "scope": "rccs"
    },
    "conferences.rccs.3": {
      "value": "Zhaohui",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03"
      ],
      "disclosure_date": "2020",
      "status": "disclosed",
      "scope": "rccs"
    },
    "conferences.rccs.4": {
      "value": "Hi161x / Kunpeng 916 / 920",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03"
      ],
      "disclosure_date": "2020",
      "status": "disclosed",
      "scope": "rccs"
    },
    "conferences.rccs.5": {
      "value": "CPU roadmap and platform; historical future targets",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03"
      ],
      "disclosure_date": "2020",
      "status": "disclosed",
      "scope": "rccs"
    },
    "conferences.rccs.6": {
      "value": "C03",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03"
      ],
      "disclosure_date": "2020",
      "status": "disclosed",
      "scope": "rccs"
    },
    "conferences.hdc.0": {
      "value": "Huawei Developer Conference",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E17",
        "R02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "hdc"
    },
    "conferences.hdc.1": {
      "value": "2025",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E17",
        "R02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "hdc"
    },
    "conferences.hdc.2": {
      "value": "CloudMatrix384 cloud service",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E17",
        "R02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "hdc"
    },
    "conferences.hdc.3": {
      "value": "Huawei Cloud",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E17",
        "R02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "hdc"
    },
    "conferences.hdc.4": {
      "value": "CloudMatrix384",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E17",
        "R02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "hdc"
    },
    "conferences.hdc.5": {
      "value": "Cloud/system availability",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E17",
        "R02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "hdc"
    },
    "conferences.hdc.6": {
      "value": "E17 / R02",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E17",
        "R02"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "hdc"
    },
    "conferences.hc25.0": {
      "value": "HUAWEI CONNECT",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02",
        "E09",
        "E16"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "hc25"
    },
    "conferences.hc25.1": {
      "value": "2025",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02",
        "E09",
        "E16"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "hc25"
    },
    "conferences.hc25.2": {
      "value": "SuperPoD, 950/960 roadmap, UnifiedBus 2.0, CANN opening",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02",
        "E09",
        "E16"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "hc25"
    },
    "conferences.hc25.3": {
      "value": "Eric Xu; Yang Chaobin; Zhang Dixuan",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02",
        "E09",
        "E16"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "hc25"
    },
    "conferences.hc25.4": {
      "value": "Kunpeng / Ascend / UB",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02",
        "E09",
        "E16"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "hc25"
    },
    "conferences.hc25.5": {
      "value": "Architecture roadmap and ecosystem",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02",
        "E09",
        "E16"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "hc25"
    },
    "conferences.hc25.6": {
      "value": "E02 / E09 / E16",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02",
        "E09",
        "E16"
      ],
      "disclosure_date": "2025",
      "status": "disclosed",
      "scope": "hc25"
    },
    "conferences.mwc.0": {
      "value": "MWC Barcelona",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "mwc"
    },
    "conferences.mwc.1": {
      "value": "2026",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "mwc"
    },
    "conferences.mwc.2": {
      "value": "SuperPoD and AI infrastructure showcase",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "mwc"
    },
    "conferences.mwc.3": {
      "value": "Huawei",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "mwc"
    },
    "conferences.mwc.4": {
      "value": "Atlas / Kunpeng",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "mwc"
    },
    "conferences.mwc.5": {
      "value": "System and industry deployment",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "mwc"
    },
    "conferences.mwc.6": {
      "value": "E05",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "mwc"
    },
    "conferences.waic.0": {
      "value": "WAIC",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E18",
        "E13"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "waic"
    },
    "conferences.waic.1": {
      "value": "2026",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E18",
        "E13"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "waic"
    },
    "conferences.waic.2": {
      "value": "Atlas 950, Atlas 850E, SP560 AI NIC, compute modules",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E18",
        "E13"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "waic"
    },
    "conferences.waic.3": {
      "value": "Huawei",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E18",
        "E13"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "waic"
    },
    "conferences.waic.4": {
      "value": "Ascend / networking",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E18",
        "E13"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "waic"
    },
    "conferences.waic.5": {
      "value": "System and product launch",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E18",
        "E13"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "waic"
    },
    "conferences.waic.6": {
      "value": "E18 / E13",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E18",
        "E13"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "waic"
    },
    "conferences.iscas.0": {
      "value": "IEEE ISCAS",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E06"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "iscas"
    },
    "conferences.iscas.1": {
      "value": "2026",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E06"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "iscas"
    },
    "conferences.iscas.2": {
      "value": "Tau scaling and logic folding",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E06"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "iscas"
    },
    "conferences.iscas.3": {
      "value": "Huawei researchers",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E06"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "iscas"
    },
    "conferences.iscas.4": {
      "value": "Related scaling research",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E06"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "iscas"
    },
    "conferences.iscas.5": {
      "value": "Research direction; not ISSCC or a product node disclosure",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E06"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "iscas"
    },
    "conferences.iscas.6": {
      "value": "E06",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E06"
      ],
      "disclosure_date": "2026",
      "status": "disclosed",
      "scope": "iscas"
    },
    "conferences.hc26.0": {
      "value": "HUAWEI CONNECT",
      "field": "Venue",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "E03",
        "E04",
        "E10",
        "E11",
        "E12"
      ],
      "disclosure_date": "2026-09",
      "status": "disclosed",
      "scope": "hc26"
    },
    "conferences.hc26.1": {
      "value": "2026",
      "field": "Year",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "E03",
        "E04",
        "E10",
        "E11",
        "E12"
      ],
      "disclosure_date": "2026-09",
      "status": "disclosed",
      "scope": "hc26"
    },
    "conferences.hc26.2": {
      "value": "960E, Hi-ONE, Peerium, M900, Kunpeng pools",
      "field": "Paper / talk / disclosure",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "E03",
        "E04",
        "E10",
        "E11",
        "E12"
      ],
      "disclosure_date": "2026-09",
      "status": "disclosed",
      "scope": "hc26"
    },
    "conferences.hc26.3": {
      "value": "David Wang; Huawei",
      "field": "Presenter / authors",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "E03",
        "E04",
        "E10",
        "E11",
        "E12"
      ],
      "disclosure_date": "2026-09",
      "status": "disclosed",
      "scope": "hc26"
    },
    "conferences.hc26.4": {
      "value": "AI infrastructure stack",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "E03",
        "E04",
        "E10",
        "E11",
        "E12"
      ],
      "disclosure_date": "2026-09",
      "status": "disclosed",
      "scope": "hc26"
    },
    "conferences.hc26.5": {
      "value": "System launch, roadmap update, optics/storage architecture",
      "field": "Evidence type",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "E03",
        "E04",
        "E10",
        "E11",
        "E12"
      ],
      "disclosure_date": "2026-09",
      "status": "disclosed",
      "scope": "hc26"
    },
    "conferences.hc26.6": {
      "value": "E01 / E03 / E04 / E10 / E11 / E12",
      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "E03",
        "E04",
        "E10",
        "E11",
        "E12"
      ],
      "disclosure_date": "2026-09",
      "status": "disclosed",
      "scope": "hc26"
    },
    "crosswalk.920.0": {
      "value": "Hi1620 / Kunpeng 920 / TaiShan V110",
      "field": "Name / identifier",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "P09"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "920"
    },
    "crosswalk.920.1": {
      "value": "Original 2019 CPU / product / core",
      "field": "Meaning",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "P09"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "920"
    },
    "crosswalk.920.2": {
      "value": "New-model 920 platforms have separate specifications",
      "field": "Important boundary",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "P09"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "920"
    },
    "crosswalk.950.0": {
      "value": "Kunpeng 950 / Linx816",
      "field": "Name / identifier",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P08",
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "950"
    },
    "crosswalk.950.1": {
      "value": "Host CPU family / embedded Ascend CPU core",
      "field": "Meaning",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P08",
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "950"
    },
    "crosswalk.950.2": {
      "value": "Do not equate the two microarchitectures",
      "field": "Important boundary",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P08",
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "950"
    },
    "crosswalk.davinci.0": {
      "value": "DaVinci / Ascend / Atlas",
      "field": "Name / identifier",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P15",
        "P12"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "davinci"
    },
    "crosswalk.davinci.1": {
      "value": "Architecture / processor / hardware system",
      "field": "Meaning",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P15",
        "P12"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "davinci"
    },
    "crosswalk.davinci.2": {
      "value": "One architecture spans multiple chips and boards",
      "field": "Important boundary",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P15",
        "P12"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "davinci"
    },
    "crosswalk.a3.0": {
      "value": "910C / Atlas 900 A3 / CloudMatrix384",
      "field": "Name / identifier",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "a3"
    },
    "crosswalk.a3.1": {
      "value": "NPU / SuperPoD product / cloud-system architecture",
      "field": "Meaning",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "a3"
    },
    "crosswalk.a3.2": {
      "value": "The paper abbreviates the processor to Ascend 910; launch identifies 910C",
      "field": "Important boundary",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "R02",
        "E02"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "a3"
    },
    "crosswalk.pr.0": {
      "value": "950PR / Atlas 350",
      "field": "Name / identifier",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "pr"
    },
    "crosswalk.pr.1": {
      "value": "Prefill/recommendation processor / 28-Cube PCIe card",
      "field": "Meaning",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "pr"
    },
    "crosswalk.pr.2": {
      "value": "128 GB chip maximum vs 112 GB card configuration",
      "field": "Important boundary",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15",
        "P14"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "pr"
    },
    "crosswalk.ub.0": {
      "value": "UB buffer / UnifiedBus",
      "field": "Name / identifier",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "ub"
    },
    "crosswalk.ub.1": {
      "value": "AI-core local memory / system interconnect",
      "field": "Meaning",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "ub"
    },
    "crosswalk.ub.2": {
      "value": "Same acronym, different layers",
      "field": "Important boundary",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "ub"
    },
    "crosswalk.hccs.0": {
      "value": "HCCS / HCCL",
      "field": "Name / identifier",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "hccs"
    },
    "crosswalk.hccs.1": {
      "value": "Hardware interconnect / collective software library",
      "field": "Meaning",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "hccs"
    },
    "crosswalk.hccs.2": {
      "value": "A library name does not specify link bandwidth",
      "field": "Important boundary",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01",
        "P15"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "hccs"
    },
    "crosswalk.sp.0": {
      "value": "SP600 / SP900 / SP560 AI NIC",
      "field": "Name / identifier",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "P06",
        "E13"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp"
    },
    "crosswalk.sp.1": {
      "value": "NIC family / DPU family / AI NIC",
      "field": "Meaning",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "P06",
        "E13"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp"
    },
    "crosswalk.sp.2": {
      "value": "Do not infer the AI NIC from a similarly named SSD",
      "field": "Important boundary",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P04",
        "P06",
        "E13"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "sp"
    },
    "crosswalk.optics.0": {
      "value": "Hi-ONE / NPO",
      "field": "Name / identifier",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "optics"
    },
    "crosswalk.optics.1": {
      "value": "Optical engine / near-packaged optics",
      "field": "Meaning",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "optics"
    },
    "crosswalk.optics.2": {
      "value": "Not a blanket synonym for CPO",
      "field": "Important boundary",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "optics"
    },
    "crosswalk.kv.0": {
      "value": "OceanStor M900 / L3.5",
      "field": "Name / identifier",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "kv"
    },
    "crosswalk.kv.1": {
      "value": "KV storage system / system-tier label",
      "field": "Meaning",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "kv"
    },
    "crosswalk.kv.2": {
      "value": "Not a CPU L3 cache or on-chip SRAM",
      "field": "Important boundary",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E11"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "kv"
    }
  },
  "numeric_facts": {
    "920_ddr": {
      "value": 187.712,
      "unit": "GB/s",
      "scope": "Kunpeng920 64-core socket",
      "source": [
        "P01"
      ],
      "status": "disclosed",
      "basis": "8 channels × 64 data bits × 2933 MT/s / 8",
      "direction": "memory read or write",
      "format": "n/a",
      "date": "2026-09-28"
    },
    "920_bw_core": {
      "value": 2.933,
      "unit": "GB/s/core",
      "scope": "Kunpeng920 64-core socket",
      "source": [
        "P01"
      ],
      "status": "disclosed",
      "basis": "derived 187.712/64",
      "direction": "memory read or write",
      "format": "n/a",
      "date": "2026-09-28"
    },
    "950pr_bf16": {
      "value": 432,
      "unit": "TFLOPS",
      "scope": "950PR max chip Cube only",
      "source": [
        "P15"
      ],
      "status": "disclosed",
      "basis": "theoretical peak",
      "direction": "n/a",
      "format": "dense BF16",
      "date": "2026-09-28"
    },
    "950pr_fp8": {
      "value": 865,
      "unit": "TFLOPS",
      "scope": "950PR max chip Cube only",
      "source": [
        "P15"
      ],
      "status": "disclosed",
      "basis": "theoretical peak",
      "direction": "n/a",
      "format": "dense FP8",
      "date": "2026-09-28"
    },
    "950dt_bf16": {
      "value": 486,
      "unit": "TFLOPS",
      "scope": "950DT max chip Cube only",
      "source": [
        "P15"
      ],
      "status": "disclosed",
      "basis": "theoretical peak",
      "direction": "n/a",
      "format": "dense BF16",
      "date": "2026-09-28"
    },
    "950dt_fp8": {
      "value": 973,
      "unit": "TFLOPS",
      "scope": "950DT max chip Cube only",
      "source": [
        "P15"
      ],
      "status": "disclosed",
      "basis": "theoretical peak",
      "direction": "n/a",
      "format": "dense FP8",
      "date": "2026-09-28"
    },
    "950_link": {
      "value": 56,
      "unit": "GB/s",
      "scope": "950 x4 UB port",
      "source": [
        "P15"
      ],
      "status": "disclosed",
      "basis": "4×112 Gb/s /8; raw signaling rate",
      "direction": "one direction",
      "format": "n/a",
      "date": "2026-09-28"
    },
    "950_io": {
      "value": 1008,
      "unit": "GB/s",
      "scope": "950 all18 UB ports before reuse",
      "source": [
        "P15"
      ],
      "status": "disclosed",
      "basis": "2016 bidirectional /2; raw",
      "direction": "one direction",
      "format": "n/a",
      "date": "2026-09-28"
    },
    "350_link4": {
      "value": 159,
      "unit": "GB/s",
      "scope": "Atlas350 four-card mesh per card",
      "source": [
        "P14"
      ],
      "status": "disclosed",
      "basis": "318 bidirectional /2",
      "direction": "one direction",
      "format": "n/a",
      "date": "2026-09-28"
    },
    "350_link2": {
      "value": 212,
      "unit": "GB/s",
      "scope": "Atlas350 two-card configuration per card",
      "source": [
        "P14"
      ],
      "status": "disclosed",
      "basis": "424 bidirectional /2",
      "direction": "one direction",
      "format": "n/a",
      "date": "2026-09-28"
    },
    "cm384_npu": {
      "value": 384,
      "unit": "NPU packages",
      "scope": "CloudMatrix384",
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      "title": "HiSilicon Kunpeng 920: First 7-nm Chiplet-Based 64-Core Server CPU With Arm Ecosystem, IEEE Micro 2021",
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      "url": "https://arxiv.org/pdf/2604.03298",
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