{ "vendor": "Google", "cutoff": "2026-09-28", "sections": [ { "id": "01", "title": [ "Scope and executive synthesis", "范围与核心判断" ], "blocks": [ { "id": "01.scope", "type": "prose", "text": [ "Coverage: TPU and ICI are deep; Axion, offload and datacenter networking are full at the publicly disclosed level; video acceleration is proportional. Period: 2015-28 September 2026. The latest architecture disclosures reviewed include Cloud Next 2026, the 2026 training-TPU retrospective, and the public Hot Chips 2026 program. Pixel Tensor and edge Coral are excluded. Availability refers to internal deployment or cloud service availability, explicitly distinguished below.", "覆盖范围：深入分析 TPU 与 ICI；按公开披露深度完整覆盖 Axion、基础设施卸载及数据中心网络；按相关性覆盖视频加速。时间范围：2015 年至 2026 年 9 月 28 日。已审阅的最新架构资料包括 Cloud Next 2026、2026 年训练 TPU 回顾论文及 Hot Chips 2026 公开议程。不覆盖 Pixel Tensor 与边缘 Coral。下文分别标明内部部署与云服务正式商用。" ], "sources": [ "C01", "C05", "C09", "P08" ] }, { "id": "01.thesis", "type": "prose", "text": [ "Google’s central architectural asset is continuity of the compiler-controlled tensor machine inside a changing system. The progression is from a latency-constrained inference coprocessor, to a distributed training computer, to workload-specific training and serving systems. Axion and Titanium extend that control to the host and infrastructure path. The important comparison with a GPU vendor is therefore the complete path from graph compilation to job placement, memory movement, collective communication and recovery, rather than matrix throughput alone.", "Google 的核心架构资产，是在持续变化的系统中保持编译器控制的张量计算模型。其演进从受延迟约束的推理协处理器，走向分布式训练计算机，再走向按训练与服务负载优化的系统。Axion 和 Titanium 把这种控制延伸至主机和基础设施路径。因此，与 GPU 厂商比较时，应考察从图编译到作业放置、数据搬移、集合通信和故障恢复的完整路径，而不只是矩阵算力。" ], "sources": [ "C01", "C03", "C05", "P08", "P10" ] } ] }, { "id": "02", "title": [ "Reading the specifications", "规格口径" ], "blocks": [ { "id": "02.basis", "type": "prose", "text": [ "All compute figures are per physical TPU package and dense unless stated otherwise; TFLOPS counts a multiply-add as two operations. Cloud names such as v3-8 count TensorCores, not eight physical chips. GB and GiB retain source units. HBM bandwidth is not bidirectional ICI bandwidth. Full pod footprint, usable allocation and maximum single-job slice can differ. A source’s first deployment date is not automatically public cloud GA. n/d means not established in the reviewed primary documents; n/a means not applicable.", "算力均以物理 TPU 封装为单位，除非另有说明均为稠密值；乘加按两次运算计。v3-8 等云端名称计算的是 TensorCore 数量，不能理解为八颗物理芯片。GB 与 GiB 保留原始资料口径。HBM 带宽与 ICI 双向带宽不同。完整 Pod 的物理规模、可用分配规模和单作业最大切片可能不同。首次内部部署时间不自动等于云端正式商用时间。n/d 表示已审阅一手资料未确定，n/a 表示不适用。" ], "sources": [ "C02", "P07", "P09" ] } ] }, { "id": "03", "title": [ "Axion: bringing the host into the platform", "Axion：把主机纳入平台" ], "blocks": [ { "id": "03.cpu", "type": "prose", "text": [ "The first Axion C4A service became generally available in October 2024 and uses Neoverse V2. N4A, generally available on 27 January 2026, uses the N3 core and targets flexible general-purpose VM shapes. These are distinct workload positions, not proof that every N-series core supersedes every C-series core. Published VM limits describe sold resources; they do not establish physical die core counts, memory channels or socket topology.", "第一代 Axion C4A 服务于 2024 年 10 月正式商用，采用 Neoverse V2。N4A 于 2026 年 1 月 27 日正式商用，采用 N3 核心，侧重灵活的通用虚拟机配置。两者体现不同的负载定位，不能理解为所有 N 系列核心都全面替代 C 系列核心。公开虚拟机上限描述可购买的资源，并不直接确定物理裸片核心数、内存通道数或插槽拓扑。" ], "sources": [ "P10", "P11", "E01" ] }, { "id": "03.host", "type": "prose", "text": [ "Architectural implication: a host can bottleneck AI without executing the main matrix workload. Tokenization, input preparation, dispatch and checkpoint movement consume CPU and I/O resources; infrastructure processing competes with those tasks unless offloaded. Titanium removes portions of networking and storage work from the application CPU. The eighth-generation TPU disclosure explicitly includes Axion hosts. This creates a co-design opportunity, but it does not establish coherent CPU-TPU shared physical memory or uniform access latency.", "架构含义：即使不执行主要矩阵计算，主机仍可能限制 AI 系统。分词、输入准备、任务提交和检查点搬移均消耗 CPU 与 I/O；基础设施处理若不卸载，就会与这些任务竞争资源。Titanium 把部分网络和存储处理移出应用 CPU。第八代 TPU 披露明确采用 Axion 主机。这提供了协同设计机会，但不意味着 CPU 与 TPU 具有一致性共享物理内存或均匀访存延迟。" ], "sources": [ "P08", "P10" ] }, { "id": "cpu", "type": "table", "table": "cpu" } ] }, { "id": "04", "title": [ "TPU v1 and the separate inference branch", "TPU v1 与独立推理分支" ], "blocks": [ { "id": "04.v1", "type": "prose", "text": [ "TPU v1 entered internal service in 2015. Its integer systolic array, software-managed buffers and deterministic execution addressed inference under strict response-time limits. The ISCA 2017 paper is valuable because it connects the machine to production workload measurements, including utilization and memory constraints. A large arithmetic array cannot compensate for insufficient weight reuse; the 34 GB/s off-chip interface made that limitation concrete. Its DDR-based memory and lack of a training pod distinguish it sharply from later HBM systems.", "TPU v1 于 2015 年投入内部服务。整数脉动阵列、软件管理缓冲区和确定性执行，服务于严格响应时间限制下的推理。ISCA 2017 论文的价值在于把机器结构与生产负载测量相连，包括利用率和存储约束。算术阵列再大，也无法补偿不足的权重复用；34 GB/s 片外接口使这个限制十分具体。DDR 存储和缺少训练 Pod，使其明显区别于后续 HBM 系统。" ], "sources": [ "C01" ] }, { "id": "04.v4i", "type": "prose", "text": [ "TPU v4i is a distinct inference design, deployed in 2020 and documented at ISCA 2021. Its 7 nm implementation and enlarged on-chip storage reflect an effort to retain useful working sets while controlling serving power. It should not be folded into the training TPU v4 row. More generally, the i, e and p branches represent different optimization objectives; a later number is insufficient to infer which device is best for a particular latency, capacity or scaling requirement.", "TPU v4i 是独立的推理设计，于 2020 年部署，在 ISCA 2021 披露。7 nm 实现与扩大的片上存储，体现了在控制服务功耗的同时保留有效工作集的设计目标。它不能合并到训练 TPU v4 的规格行中。更一般地，i、e、p 分支代表不同优化目标；仅凭代号较新，无法判断哪款设备更适合特定延迟、容量或扩展要求。" ], "sources": [ "C02" ] } ] }, { "id": "05", "title": [ "TPU v2-v4: from chip to training computer", "TPU v2-v4：从芯片走向训练计算机" ], "blocks": [ { "id": "05.v23", "type": "prose", "text": [ "TPU v2 introduced BF16 training, HBM and a two-dimensional ICI torus. TPU v3 expanded matrix resources and memory capacity and moved to liquid cooling. Hot Chips 2020 explains the architectural organization; the later training retrospective connects it to larger systems and resilience. The important implementation consequence is that more compute in the same generation of manufacturing did not remain a chip-only change: power delivery, cooling, network size and the compiler’s partitioning strategy had to evolve together.", "TPU v2 引入 BF16 训练、HBM 和二维 ICI 环面。TPU v3 扩大矩阵资源及内存容量，并转向液冷。Hot Chips 2020 解释了架构组织，后续训练系统回顾论文进一步连接到更大系统及可靠性。关键实现后果是：在同一制造工艺代际中增加算力，并不只是芯片变化；供电、散热、网络规模和编译器分区策略都必须共同演进。" ], "sources": [ "C04", "C05" ] }, { "id": "05.v4", "type": "prose", "text": [ "TPU v4 combines stronger compute with SparseCore acceleration for embeddings and an optically reconfigurable interconnect. Optical circuit switches change physical connectivity at a coarse timescale; they are not packet switches executing each collective. Reconfiguration helps assemble healthy slices, vary topology and accommodate unavailable components. The 4,096-chip system is therefore also an availability architecture: at this scale, recovering usable capacity matters alongside reducing collective time. The ISCA 2023 paper supplies the explicit product link.", "TPU v4 将更强计算、面向嵌入表的 SparseCore 与可光学重构的互联结合。光路交换机在较粗时间尺度上改变物理连接，并不是为每个集合操作逐包转发的交换机。重构可帮助组成健康切片、调整拓扑，并绕过不可用组件。因此，4,096 芯片系统也是一种可用性架构：在这种规模下，恢复可用容量与减少集合通信时间同样重要。ISCA 2023 论文给出了明确的产品对应关系。" ], "sources": [ "C03" ] } ] }, { "id": "06", "title": [ "v5e, v5p and Trillium: two scaling objectives", "v5e、v5p 与 Trillium：两种扩展目标" ], "blocks": [ { "id": "06.branches", "type": "prose", "text": [ "TPU v5e is a cost-oriented training and inference platform with a smaller physical domain; v5p targets much larger training systems and more HBM per chip. Trillium (v6e) advances the efficiency branch with more compute and memory bandwidth. The e branch is not merely a partially disabled p chip: its domain size, memory budget and deployment economics should be evaluated on their own. For a model that fits in a small slice, paying for a much larger physical scale-up capability may yield little benefit.", "TPU v5e 是侧重成本的训练和推理平台，物理域较小；v5p 面向更大型训练系统，单芯片 HBM 更多。Trillium（v6e）继续推进效率分支，增加计算与存储带宽。e 分支不能简单理解为屏蔽部分资源的 p 芯片：其域规模、内存预算和部署经济性应独立评价。若模型能放入较小切片，为更大物理纵向扩展能力付费，未必带来相应收益。" ], "sources": [ "P04", "P05", "P06" ] }, { "id": "06.balance", "type": "prose", "text": [ "The design question is the bottleneck after partitioning. Dense training can reuse weights enough to benefit from a larger MXU budget, whereas embedding traffic, small batches and decode expose memory and communication. A fair comparison holds model, precision, batch, latency objective and usable chip count constant. Comparing a complete v5p pod with a small Trillium slice answers a procurement-capacity question, not a per-chip architectural efficiency question.", "设计问题在于分区之后的瓶颈。稠密训练可能通过权重复用充分利用更多 MXU，而嵌入表流量、小批量和解码更容易暴露存储及通信限制。公平比较应固定模型、精度、批量、延迟目标和可用芯片数。把完整 v5p Pod 与较小 Trillium 切片比较，回答的是采购容量问题，并非单芯片架构效率问题。" ], "sources": [ "P04", "P05", "P06" ] } ] }, { "id": "07", "title": [ "Ironwood and the eighth-generation split", "Ironwood 与第八代分化" ], "blocks": [ { "id": "07.iron", "type": "prose", "text": [ "Ironwood/TPU7x introduces two compute chiplets with distinct local memory spaces. The package contains two TensorCores, four SparseCores and 192 GiB of HBM according to the cloud specification table. The compiler-visible locality differs from the earlier MegaCore abstraction. A larger package peak does not erase cross-chiplet movement: sharding and kernel placement now have an additional physical boundary to respect. The cloud documentation lists JAX and PyTorch support and explicitly excludes TensorFlow on TPU7x.", "Ironwood／TPU7x 引入两颗计算芯粒，各有本地内存空间。云端规格表给出的封装配置为两个 TensorCore、四个 SparseCore 和 192 GiB HBM。编译器可见的局部性与此前 MegaCore 抽象不同。更高封装算力不能消除跨芯粒搬移；分片与内核放置必须考虑新增的物理边界。云端文档列出 JAX 和 PyTorch 支持，并明确说明 TPU7x 不支持 TensorFlow。" ], "sources": [ "P07", "P13" ] }, { "id": "07.eight", "type": "prose", "text": [ "The April 2026 TPU 8 disclosure makes workload specialization explicit. TPU 8t retains a large torus for training; TPU 8i uses Boardfly for a smaller-diameter serving domain and adds a collective acceleration engine. The published 8i footprint is 1,152 chips, while the topology description separately states up to 1,024 active chips. These numbers must remain separate. Both products are recorded here as announced; the reviewed architectural announcement does not establish general availability.", "2026 年 4 月的 TPU 8 披露明确采用负载专用化。TPU 8t 为训练保留大规模环面；TPU 8i 使用 Boardfly 降低服务域的网络直径，并加入集合通信加速引擎。8i 公布的物理规模是 1,152 芯片，拓扑说明另外指出最多 1,024 个活跃芯片，两者必须分开记录。本报告把两款产品列为已公布；已审阅的架构发布资料不足以确定正式商用。" ], "sources": [ "P08", "E03" ] }, { "id": "07.decision", "type": "prose", "text": [ "Architectural interpretation: the split is evidence that domain size and network diameter have become independent product variables. A training system can tolerate more hops when long collective transfers amortize startup cost. Autoregressive inference repeatedly pays synchronization latency and may prefer fewer hops even with a smaller domain. More SRAM helps only the portion of the working set that actually fits; it does not imply that an arbitrary long-context KV cache resides entirely on chip.", "架构解读：这种分化说明域规模与网络直径已成为独立的产品变量。训练系统的长集合传输可摊薄启动开销，因此可以接受更多跳数。自回归推理反复支付同步延迟，可能宁愿采用规模较小但跳数更少的域。更多 SRAM 只帮助真正能放入其中的工作集，不能推导出任意长上下文 KV 缓存都能驻留片上。" ], "sources": [ "P08" ] } ] }, { "id": "08", "title": [ "Accelerator generation comparison", "加速器代际对照" ], "blocks": [ { "id": "gpu", "type": "table", "table": "gpu" } ] }, { "id": "09", "title": [ "ICI, Jupiter, Virgo and infrastructure offload", "ICI、Jupiter、Virgo 与基础设施卸载" ], "blocks": [ { "id": "09.net", "type": "prose", "text": [ "ICI is the accelerator fabric; Jupiter is the datacenter network. The Jupiter Rising and Jupiter Evolving papers explain the progression from centrally controlled Clos fabrics to optical reconfiguration in the datacenter. These disclosures should not be conflated with the TPU’s local ICI topology. Virgo adds a training-oriented scale-out fabric in the TPU 8 era. A million-chip distributed training claim describes aggregation across systems, not a million-chip coherent memory domain or a single ICI pod.", "ICI 是加速器网络，Jupiter 是数据中心网络。Jupiter Rising 与 Jupiter Evolving 论文解释了从集中控制的 Clos 网络走向数据中心光学重构的过程，不能与 TPU 本地 ICI 拓扑混为一谈。TPU 8 时代的 Virgo 增加了面向训练的横向扩展网络。百万芯片分布式训练的表述指跨系统聚合，不是百万芯片的一致性内存域或单个 ICI Pod。" ], "sources": [ "C06", "C07", "E05", "P08" ] }, { "id": "09.roles", "type": "prose", "text": [ "Titanium is an infrastructure offload system, not a publicly documented merchant DPU SKU with a complete per-chip datasheet. Falcon describes a reliable hardware transport; a transport specification is not itself a Google-branded NIC product. The appropriate report boundary is to map the function and deployment path, retaining n/d for undisclosed silicon implementation. Argos video acceleration belongs alongside this portfolio because it shows the same workload-driven specialization at warehouse scale, but its video engines are not TPU tensor cores.", "Titanium 是基础设施卸载系统，不是具有完整单芯片数据表的公开商用 DPU SKU。Falcon 描述可靠硬件传输机制；传输规范本身不是 Google 品牌网卡产品。报告应映射功能和部署路径，对未披露的芯片实现保留 n/d。Argos 视频加速也应列入产品组合，因为它展示了相同的仓库级负载专用化思路，但视频引擎不等于 TPU 张量核心。" ], "sources": [ "P10", "P14", "C08" ] }, { "id": "net", "type": "table", "table": "net" }, { "id": "links", "type": "table", "table": "links" } ] }, { "id": "10", "title": [ "Software and integrated systems", "软件与集成系统" ], "blocks": [ { "id": "10.sw", "type": "prose", "text": [ "XLA preserves a relatively stable programming contract while hardware changes. JAX expresses distributed computation; Pallas and Mosaic expose lower-level control for kernels whose data movement dominates. SparseCore and collective engines have value only when the software places and schedules work for them. Therefore portability and peak utilization are separate milestones: executing an unchanged model does not mean that its partitioning, fusion and scratchpad schedule exploit a new generation.", "XLA 在硬件变化时保持相对稳定的编程契约。JAX 表达分布式计算；Pallas 和 Mosaic 为数据搬移占主导的内核提供更低层控制。只有软件能够放置并调度相应工作时，SparseCore 与集合引擎才有价值。因此，可移植性与峰值利用率是两个不同里程碑：模型无修改地运行，并不说明其分区、融合和暂存区调度已发挥新一代硬件能力。" ], "sources": [ "C05", "P13" ] }, { "id": "software", "type": "table", "table": "software" }, { "id": "era1", "type": "figure", "figure": "era1" }, { "id": "era2", "type": "figure", "figure": "era2" }, { "id": "era3", "type": "figure", "figure": "era3" }, { "id": "system", "type": "table", "table": "system" } ] }, { "id": "11", "title": [ "Bandwidth balance and architectural trade-offs", "带宽平衡与架构取舍" ], "blocks": [ { "id": "11.ratio", "type": "prose", "text": [ "Derived ratios below use memory bandwidth divided by dense compute, in bytes/FLOP. Capacity divided by compute has units of byte-seconds/FLOP and is deliberately reported separately in the canonical data. v5p uses 95 GiB of usable cloud memory, while the retrospective describes 96 GiB physical capacity. Ironwood bandwidth is 7,380 GB/s in the current cloud table; the retrospective rounds it differently. These are source-basis differences, not additional hardware generations.", "以下推导比值用存储带宽除以稠密算力，单位为 byte/FLOP。容量除以算力的单位是 byte·s/FLOP，在规范数据中单独记录。v5p 使用云端可用容量 95 GiB，而回顾论文给出物理容量 96 GiB。当前云端表中的 Ironwood 带宽为 7,380 GB/s，回顾论文采用不同舍入口径。这些是资料口径差异，不是新的硬件代际。" ], "sources": [ "P05", "P07", "C05" ] }, { "id": "ratios", "type": "table", "table": "ratios" }, { "id": "11.trade", "type": "prose", "text": [ "Architectural interpretation: from v2 to Ironwood, BF16 compute grows about 50 times while HBM bandwidth grows about 10.5 times. The required reuse rises accordingly. Larger arrays shift responsibility toward compiler tiling, fusion and local storage. At system scale, optical reconfiguration trades a more complex control plane for improved slice assembly and fault accommodation. At the host boundary, direct I/O reduces copies but makes end-to-end scheduling and access protection more consequential. The practical evaluation should therefore include sustained throughput during communication, fault recovery time and the cost of recompiling or retuning models, not only isolated GEMM.", "架构解读：从 v2 到 Ironwood，BF16 算力约增长 50 倍，HBM 带宽约增长 10.5 倍，所需数据复用程度相应提高。更大阵列把更多责任交给编译器分块、融合及本地存储。在系统层面，光学重构以更复杂控制平面换取切片组装和故障容纳能力。在主机边界，直接 I/O 减少复制，却提高了端到端调度及访问保护的重要性。因此，实际评估应包含通信并发下的持续吞吐、故障恢复时间，以及重编译或调优模型的成本，而不只是独立 GEMM。" ], "sources": [ "C04", "C05", "P07", "P08" ] }, { "id": "capacity_balance", "type": "table", "table": "capacity_balance" } ] }, { "id": "12", "title": [ "Conference-to-product index", "会议与产品索引" ], "blocks": [ { "id": "conference", "type": "table", "table": "conference" }, { "id": "12.gaps", "type": "prose", "text": [ "ISCA, ASPLOS, Hot Chips and IEEE Micro provide direct product disclosures in the selected corpus. MICRO and HPCA research should be included only when a documented product connection exists; none is asserted here. An ISSCC/JSSC circuit-paper-to-TPU mapping was not established in this pass, so circuit parameters are drawn from the identified product papers rather than attributed to ISSCC. Cloud Next and OCP are useful for launches and systems; MWC, Computex, GTC and other cloud events do not automatically add independent evidence for Google-owned silicon.", "所选资料中的 ISCA、ASPLOS、Hot Chips 与 IEEE Micro 提供直接产品披露。MICRO、HPCA 研究只有在文献明确建立产品联系时才可归入产品；本报告不作未经证实的归属。本次未建立 ISSCC／JSSC 电路论文与 TPU 的明确映射，因此电路参数采用已识别的产品论文，不把它们归因于 ISSCC。Cloud Next 与 OCP 适合补充发布和系统信息；MWC、Computex、GTC 及其他云活动并不自动构成 Google 自研芯片的独立证据。" ], "sources": [ "C01", "C02", "C03", "C08", "C09" ] }, { "id": "isscc", "type": "table", "table": "isscc" }, { "id": "12.isscccontext", "type": "prose", "text": [ "ISSCC contributes both the domain-specialization rationale and a power-delivery implementation perspective. The 2026 forum entry establishes Google’s participation in that engineering discussion, but does not by itself reveal a particular TPU voltage-regulator circuit. These records complement the ISCA product papers and Hot Chips architecture disclosures rather than replacing them with inferred circuit specifications.", "ISSCC 同时提供领域专用化动机及供电实现视角。2026 年论坛条目证明 Google 参与该工程讨论，但其本身并不披露某代 TPU 的具体电压调节电路。这些记录补充 ISCA 产品论文与 Hot Chips 架构披露，不以推测电路规格替代它们。" ], "sources": [ "C10", "C11", "C12" ] } ] }, { "id": "13", "title": [ "Naming crosswalk and remaining disclosure gaps", "命名对照与剩余披露缺口" ], "blocks": [ { "id": "crosswalk", "type": "table", "table": "crosswalk" }, { "id": "13.finish", "type": "prose", "text": [ "The largest unresolved implementation fields are the physical Axion package organization, exact TDP and per-die process information for recent TPUs, and complete link electrical parameters. These gaps limit package-level power and area comparisons but do not prevent analysis of the disclosed memory and network hierarchy. The next useful evidence would be a circuit-level implementation paper, a complete TPU 8 service specification, and measured software behavior across Ironwood’s chiplet boundary.", "尚未确定的主要实现字段，是 Axion 的物理封装组织、近期 TPU 的准确 TDP 与逐裸片工艺，以及完整链路电气参数。这些缺口限制封装级功耗和面积比较，但不妨碍分析已披露的存储与网络层次。下一步最有价值的证据，是电路级实现论文、完整 TPU 8 服务规格，以及 Ironwood 跨芯粒边界的软件实测行为。" ], "sources": [ "P07", "P08", "P10" ] } ] } ], "tables": { "cpu": { "id": "cpu", "title": [ "Host CPU comparison", "主机 CPU 对照" ], "headers": [ [ "Generation / reference SKU", "代际／参考 SKU" ], [ "Codename", "代号" ], [ "GA", "正式商用" ], [ "Status", "状态" ], [ "Core µarch", "核心微架构" ], [ "Cores / threads", "核心／线程" ], [ "Process per die", "各裸片工艺" ], [ "Dies / packaging", "裸片／封装" ], [ "L2 per core", "每核 L2" ], [ "L3 / domain", "L3／共享域" ], [ "Memory: channels; rate; GB/s", "内存：通道；速率；GB/s" ], [ "Sockets / links", "插槽／互联" ], [ "PCIe / CXL", "PCIe／CXL" ], [ "TDP", "TDP" ], [ "Vector / matrix ISA", "向量／矩阵 ISA" ] ], "rows": [ { "id": "c4a", "values": [ [ "Axion / C4A", "Axion / C4A" ], [ "n/d", "n/d" ], [ "2024-10", "2024-10" ], [ "Shipping / available", "已商用／可获取" ], [ "Neoverse V2", "Neoverse V2" ], [ "n/d physical; VM ≤72 vCPU", "物理 n/d；VM ≤72 vCPU" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "DDR5; channels/rate n/d", "DDR5；通道／速率 n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "Arm64; SVE2", "Arm64; SVE2" ] ], "sources": [ "P10", "P11", "E01" ] }, { "id": "n4a", "values": [ [ "Axion / N4A", "Axion / N4A" ], [ "n/d", "n/d" ], [ "2026-01-27", "2026-01-27" ], [ "Shipping / available", "已商用／可获取" ], [ "Neoverse N3", "Neoverse N3" ], [ "n/d physical; VM ≤64 vCPU", "物理 n/d；VM ≤64 vCPU" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "DDR5; VM ≤512 GB; peak n/d", "DDR5；VM ≤512 GB；峰值 n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "Arm64", "Arm64" ] ], "sources": [ "P10" ] } ], "panels": [ [ 0, 1, 2, 3, 4, 5 ], [ 0, 6, 7, 8, 9 ], [ 0, 10, 11, 12, 13, 14 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "gpu": { "id": "gpu", "title": [ "TPU family", "TPU 家族" ], "headers": [ [ "Product", "产品" ], [ "Architecture", "架构" ], [ "GA / milestone", "商用／里程碑" ], [ "Status", "状态" ], [ "Process", "工艺" ], [ "Dies / packaging", "裸片／封装" ], [ "Compute units", "计算单元" ], [ "Dense BF16", "稠密 BF16" ], [ "Dense FP8", "稠密 FP8" ], [ "Dense FP6 / FP4", "稠密 FP6／FP4" ], [ "FP64 vector / matrix", "FP64 向量／矩阵" ], [ "Memory: type; stacks; GB; TB/s", "内存：类型；堆栈；GB；TB/s" ], [ "LLC / SRAM", "末级缓存／SRAM" ], [ "Scale-up: links; GB/s per direction; domain", "纵向扩展：链路；单向 GB/s；域" ], [ "Host link", "主机连接" ], [ "Power / cooling", "功耗／散热" ], [ "Form factor", "形态" ] ], "rows": [ { "id": "v1", "values": [ [ "TPU v1", "TPU v1" ], [ "INT8 systolic", "INT8 systolic" ], [ "2015 Q2", "2015 Q2" ], [ "Historical shipping", "历史已商用" ], [ "28 nm", "28 nm" ], [ "1", "1" ], [ "1 × 256×256", "1 × 256×256" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/d", "n/d" ], [ "DDR3; 8 GB; 0.034 TB/s", "DDR3; 8 GB; 0.034 TB/s" ], [ "28 MB", "28 MB" ], [ "n/a", "n/a" ], [ "PCIe; n/d", "PCIe; n/d" ], [ "75 W chip TDP", "75 W chip TDP" ], [ "Google platform", "Google 平台" ] ], "sources": [ "C01", "C02" ] }, { "id": "v2", "values": [ [ "TPU v2", "TPU v2" ], [ "TensorCore", "TensorCore" ], [ "2017 Q3", "2017 Q3" ], [ "Historical shipping", "历史已商用" ], [ "16 nm", "16 nm" ], [ "1", "1" ], [ "2 TC", "2 TC" ], [ "46 TFLOPS", "46 TFLOPS" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/d", "n/d" ], [ "HBM2; 16 GiB; 0.700 TB/s", "HBM2; 16 GiB; 0.700 TB/s" ], [ "32 MiB", "32 MiB" ], [ "2D torus; 256 chips; direction n/d", "二维环面；256 芯片；方向 n/d" ], [ "PCIe; n/d", "PCIe; n/d" ], [ "280 W chip TDP; air", "280 W chip TDP; air" ], [ "Google platform", "Google 平台" ] ], "sources": [ "C02", "C04" ] }, { "id": "v3", "values": [ [ "TPU v3", "TPU v3" ], [ "TensorCore", "TensorCore" ], [ "2018 Q4", "2018 Q4" ], [ "Historical shipping", "历史已商用" ], [ "16 nm", "16 nm" ], [ "1", "1" ], [ "2 TC", "2 TC" ], [ "123 TFLOPS", "123 TFLOPS" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/d", "n/d" ], [ "HBM2; 4 stacks; 32 GiB; 0.900 TB/s", "HBM2; 4 stacks; 32 GiB; 0.900 TB/s" ], [ "32 MiB", "32 MiB" ], [ "2D torus; 1,024 chips", "二维环面；1,024 芯片" ], [ "PCIe; n/d", "PCIe; n/d" ], [ "450 W chip TDP; liquid", "450 W chip TDP; liquid" ], [ "Google platform", "Google 平台" ] ], "sources": [ "C02", "C04" ] }, { "id": "v4i", "values": [ [ "TPU v4i", "TPU v4i" ], [ "Inference", "Inference" ], [ "2020 Q1", "2020 Q1" ], [ "Historical shipping", "历史已商用" ], [ "7 nm", "7 nm" ], [ "1", "1" ], [ "1 TC; 4 MXU", "1 TC; 4 MXU" ], [ "138 TFLOPS", "138 TFLOPS" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/d", "n/d" ], [ "HBM; 8 GB; 0.614 TB/s", "HBM; 8 GB; 0.614 TB/s" ], [ "144 MB", "144 MB" ], [ "2 × 400 Gb/s; direction n/d", "2 × 400 Gb/s；方向 n/d" ], [ "PCIe; n/d", "PCIe; n/d" ], [ "175 W chip TDP", "175 W chip TDP" ], [ "Google platform", "Google 平台" ] ], "sources": [ "C02" ] }, { "id": "v4", "values": [ [ "TPU v4", "TPU v4" ], [ "TensorCore + SparseCore", "TensorCore + SparseCore" ], [ "2021 deployment", "2021 deployment" ], [ "Historical shipping", "历史已商用" ], [ "7 nm", "7 nm" ], [ "1", "1" ], [ "2 TC; 4 SC", "2 TC; 4 SC" ], [ "275 TFLOPS", "275 TFLOPS" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/d", "n/d" ], [ "HBM2; 4 stacks; 32 GiB; 1.2 TB/s", "HBM2; 4 stacks; 32 GiB; 1.2 TB/s" ], [ "32 MiB", "32 MiB" ], [ "6 × 50 GB/s/direction; 4,096", "6 × 50 GB/s/direction; 4,096" ], [ "PCIe; n/d", "PCIe; n/d" ], [ "liquid; TDP n/d", "liquid; TDP n/d" ], [ "Google platform", "Google 平台" ] ], "sources": [ "C03", "C05" ] }, { "id": "v5e", "values": [ [ "TPU v5e", "TPU v5e" ], [ "Efficiency", "Efficiency" ], [ "2023", "2023" ], [ "Shipping / available", "已商用／可获取" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "1 TC", "1 TC" ], [ "197 TFLOPS", "197 TFLOPS" ], [ "n/d", "n/d" ], [ "n/a", "n/a" ], [ "n/d", "n/d" ], [ "HBM; stacks n/d; 16 GB; 0.819 TB/s", "HBM; stacks n/d; 16 GB; 0.819 TB/s" ], [ "n/d", "n/d" ], [ "256 chips; 400 GB/s bidirectional", "256 chips; 400 GB/s bidirectional" ], [ "PCIe; n/d", "PCIe; n/d" ], [ "n/d", "n/d" ], [ "Google platform", "Google 平台" ] ], "sources": [ "P04" ] }, { "id": "v5p", "values": [ [ "TPU v5p", "TPU v5p" ], [ "Performance", "Performance" ], [ "2023 preview; GA n/d", "2023 preview; GA n/d" ], [ "Shipping / available", "已商用／可获取" ], [ "n/d", "n/d" ], [ "1", "1" ], [ "2 TC; 4 SC", "2 TC; 4 SC" ], [ "459 TFLOPS", "459 TFLOPS" ], [ "459 TFLOPS", "459 TFLOPS" ], [ "n/a", "n/a" ], [ "n/d", "n/d" ], [ "HBM2e; 6 stacks; 95 GiB usable; 2.765 TB/s", "HBM2e; 6 stacks; 95 GiB usable; 2.765 TB/s" ], [ "128 MiB", "128 MiB" ], [ "6 × 100 GB/s/direction; 8,960", "6 × 100 GB/s/direction; 8,960" ], [ "PCIe; n/d", "PCIe; n/d" ], [ "liquid; TDP n/d", "liquid; TDP n/d" ], [ "Google platform", "Google 平台" ] ], "sources": [ "P05", "P07", "C05" ] }, { "id": "v6e", "values": [ [ "TPU v6e", "TPU v6e" ], [ "Trillium", "Trillium" ], [ "2024", "2024" ], [ "Shipping / available", "已商用／可获取" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "1 TC; 2 SC", "1 TC; 2 SC" ], [ "918 TFLOPS", "918 TFLOPS" ], [ "918 TFLOPS", "918 TFLOPS" ], [ "n/a", "n/a" ], [ "n/d", "n/d" ], [ "HBM; stacks n/d; 32 GiB; 1.638 TB/s", "HBM; stacks n/d; 32 GiB; 1.638 TB/s" ], [ "n/d", "n/d" ], [ "256 chips; 800 GB/s bidirectional", "256 chips; 800 GB/s bidirectional" ], [ "PCIe; n/d", "PCIe; n/d" ], [ "n/d", "n/d" ], [ "Google platform", "Google 平台" ] ], "sources": [ "P06", "P07" ] }, { "id": "v7", "values": [ [ "TPU7x", "TPU7x" ], [ "Ironwood", "Ironwood" ], [ "2025", "2025" ], [ "Shipping / available", "已商用／可获取" ], [ "n/d", "n/d" ], [ "2 compute chiplets", "2 颗计算芯粒" ], [ "2 TC; 4 SC", "2 TC; 4 SC" ], [ "2,307 TFLOPS", "2,307 TFLOPS" ], [ "4,614 TFLOPS", "4,614 TFLOPS" ], [ "n/a", "n/a" ], [ "n/d", "n/d" ], [ "HBM3e; 8 stacks; 192 GiB; 7.380 TB/s", "HBM3e; 8 stacks; 192 GiB; 7.380 TB/s" ], [ "128 MiB", "128 MiB" ], [ "6 × 100 GB/s/direction; 9,216", "6 × 100 GB/s/direction; 9,216" ], [ "PCIe; n/d", "PCIe; n/d" ], [ "liquid; TDP n/d", "liquid; TDP n/d" ], [ "Google platform", "Google 平台" ] ], "sources": [ "P07", "C05", "E02" ] }, { "id": "v8t", "values": [ [ "TPU 8t", "TPU 8t" ], [ "Training", "Training" ], [ "2026-04-22", "2026-04-22" ], [ "Announced; GA n/d", "已公布；GA n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "12.6 PFLOPS FP4; dense basis n/d", "12.6 PFLOPS FP4；稠密口径 n/d" ], [ "n/d", "n/d" ], [ "216 GB; 6.528 TB/s", "216 GB; 6.528 TB/s" ], [ "128 MB", "128 MB" ], [ "3D torus; 9,600", "3D torus; 9,600" ], [ "PCIe; n/d", "PCIe; n/d" ], [ "liquid; TDP n/d", "liquid; TDP n/d" ], [ "Google platform", "Google 平台" ] ], "sources": [ "P08", "E03" ] }, { "id": "v8i", "values": [ [ "TPU 8i", "TPU 8i" ], [ "Serving / CAE", "Serving / CAE" ], [ "2026-04-22", "2026-04-22" ], [ "Announced; GA n/d", "已公布；GA n/d" ], [ "n/d", "n/d" ], [ "compute + CAE chiplet", "计算 + CAE 芯粒" ], [ "2 TC; 1 CAE", "2 TC; 1 CAE" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "10.1 PFLOPS FP4; dense basis n/d", "10.1 PFLOPS FP4；稠密口径 n/d" ], [ "n/d", "n/d" ], [ "288 GB; 8.601 TB/s", "288 GB; 8.601 TB/s" ], [ "384 MB", "384 MB" ], [ "Boardfly: 1,152 physical / ≤1,024 active", "Boardfly：1,152 物理／≤1,024 活跃" ], [ "PCIe; n/d", "PCIe; n/d" ], [ "liquid; TDP n/d", "liquid; TDP n/d" ], [ "Google platform", "Google 平台" ] ], "sources": [ "P08", "E03" ] } ], "panels": [ [ 0, 1, 2, 3, 4, 5 ], [ 0, 6, 7, 8, 9, 10 ], [ 0, 11, 12 ], [ 0, 13, 14, 15, 16 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "net": { "id": "net", "title": [ "Networking and offload roles", "网络及卸载角色" ], "headers": [ [ "Product", "产品" ], [ "GA / milestone", "商用／里程碑" ], [ "Status", "状态" ], [ "Class", "类别" ], [ "Ports × speed", "端口×速率" ], [ "SerDes", "SerDes" ], [ "Host interface", "主机接口" ], [ "Programmable engine", "可编程引擎" ], [ "Embedded CPU", "嵌入式 CPU" ], [ "On-card memory", "板载内存" ], [ "Transport / RDMA", "传输／RDMA" ], [ "Congestion control", "拥塞控制" ], [ "Key offloads", "主要卸载" ], [ "Power", "功耗" ] ], "rows": [ { "id": "t", "values": [ [ "Titanium", "Titanium" ], [ "n/d", "n/d" ], [ "Shipping / available", "已商用／可获取" ], [ "Infrastructure offload", "基础设施卸载" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "Networking/storage", "网络／存储" ], [ "n/d", "n/d" ] ], "sources": [ "P10" ] }, { "id": "j", "values": [ [ "Jupiter", "Jupiter" ], [ "n/d", "n/d" ], [ "Shipping / available", "已商用／可获取" ], [ "Datacenter fabric", "数据中心网络" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "Ethernet", "Ethernet" ], [ "n/d", "n/d" ], [ "Fabric control", "网络控制" ], [ "n/d", "n/d" ] ], "sources": [ "C06", "C07" ] }, { "id": "f", "values": [ [ "Falcon", "Falcon" ], [ "n/d", "n/d" ], [ "Shipping / available", "已商用／可获取" ], [ "Transport; not a NIC SKU", "传输；非网卡 SKU" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "RDMA", "RDMA" ], [ "n/d", "n/d" ], [ "Reliable transport", "可靠传输" ], [ "n/d", "n/d" ] ], "sources": [ "P14" ] }, { "id": "v", "values": [ [ "Virgo", "Virgo" ], [ "n/d", "n/d" ], [ "Announced; GA n/d", "已公布；GA n/d" ], [ "AI scale-out fabric", "AI 横向扩展网络" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "Training fabric", "训练网络" ], [ "n/d", "n/d" ] ], "sources": [ "E05" ] } ], "panels": [ [ 0, 1, 2, 3 ], [ 0, 4, 5, 6, 7 ], [ 0, 8, 9, 10, 11 ], [ 0, 12, 13 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "software": { "id": "software", "title": [ "Software evolution", "软件演进" ], "headers": [ [ "Release / layer", "版本／层" ], [ "Date", "日期" ], [ "Hardware", "硬件" ], [ "Capability", "能力" ] ], "rows": [ { "id": "x", "values": [ [ "XLA / TensorFlow", "XLA / TensorFlow" ], [ "2017-2020", "2017-2020" ], [ "v2-v3", "v2-v3" ], [ "Graph compilation and placement", "图编译与放置" ] ], "sources": [ "C04", "C05" ] }, { "id": "j", "values": [ [ "JAX / XLA", "JAX / XLA" ], [ "2021-2026", "2021-2026" ], [ "v4 onward", "v4 onward" ], [ "Distributed array programming", "分布式数组编程" ] ], "sources": [ "C05" ] }, { "id": "p", "values": [ [ "Pallas / Mosaic", "Pallas / Mosaic" ], [ "2025-2026", "2025-2026" ], [ "Ironwood / TPU8", "Ironwood / TPU8" ], [ "Explicit kernel-level locality", "内核级显式局部性" ] ], "sources": [ "P08", "P13" ] }, { "id": "t", "values": [ [ "Native PyTorch", "Native PyTorch" ], [ "2026-04", "2026-04" ], [ "TPU8 stack", "TPU8 stack" ], [ "Preview at disclosure", "披露时为预览" ] ], "sources": [ "P08" ] } ], "panels": [ [ 0, 1, 2, 3 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "ratios": { "id": "ratios", "title": [ "Derived balance metrics", "推导平衡指标" ], "headers": [ [ "Generation", "代际" ], [ "HBM BW / BF16", "HBM 带宽／BF16" ], [ "HBM BW / FP8", "HBM 带宽／FP8" ], [ "One-way ICI / HBM", "单向 ICI／HBM" ], [ "Performance / W", "性能／W" ] ], "rows": [ { "id": "v2", "values": [ [ "v2", "v2" ], [ "0.015217", "0.015217" ], [ "n/a", "n/a" ], [ "n/d", "n/d" ], [ "n/d: comparable power basis", "n/d：缺少可比功耗口径" ] ], "sources": [ "C04" ] }, { "id": "v3", "values": [ [ "v3", "v3" ], [ "0.007317", "0.007317" ], [ "n/a", "n/a" ], [ "n/d", "n/d" ], [ "n/d: comparable power basis", "n/d：缺少可比功耗口径" ] ], "sources": [ "C04" ] }, { "id": "v4", "values": [ [ "v4", "v4" ], [ "0.004364", "0.004364" ], [ "n/a", "n/a" ], [ "0.250", "0.250" ], [ "n/d: comparable power basis", "n/d：缺少可比功耗口径" ] ], "sources": [ "C03" ] }, { "id": "v5p", "values": [ [ "v5p", "v5p" ], [ "0.006024", "0.006024" ], [ "0.006024", "0.006024" ], [ "0.217", "0.217" ], [ "n/d: comparable power basis", "n/d：缺少可比功耗口径" ] ], "sources": [ "P05", "P07" ] }, { "id": "v6e", "values": [ [ "v6e", "v6e" ], [ "0.001784", "0.001784" ], [ "0.001784", "0.001784" ], [ "0.244", "0.244" ], [ "n/d: comparable power basis", "n/d：缺少可比功耗口径" ] ], "sources": [ "P07" ] }, { "id": "v7", "values": [ [ "v7", "v7" ], [ "0.003199", "0.003199" ], [ "0.001599", "0.001599" ], [ "0.081", "0.081" ], [ "n/d: comparable power basis", "n/d：缺少可比功耗口径" ] ], "sources": [ "P07" ] } ], "panels": [ [ 0, 1, 2, 3, 4 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "conference": { "id": "conference", "title": [ "Verified disclosure map", "已核实披露映射" ], "headers": [ [ "Venue", "会议／活动" ], [ "Year", "年份" ], [ "Paper / talk / disclosure", "论文／演讲／披露" ], [ "Presenter / authors", "报告人／作者" ], [ "Product", "产品" ], [ "Evidence type", "证据类型" ], [ "Source", "来源" ] ], "rows": [ { "id": "c1", "values": [ [ "ISCA", "ISCA" ], [ "2017", "2017" ], [ "In-Datacenter Performance Analysis of a Tensor Processing Unit", "In-Datacenter Performance Analysis of a Tensor Processing Unit" ], [ "Jouppi et al.", "Jouppi et al." ], [ "TPU v1", "TPU v1" ], [ "Product architecture and measurements", "产品架构与测量" ], [ "C01", "C01" ] ], "sources": [ "C01" ] }, { "id": "c2", "values": [ [ "ISCA", "ISCA" ], [ "2021", "2021" ], [ "Ten Lessons From Three Generations Shaped Google’s TPUv4i", "Ten Lessons From Three Generations Shaped Google’s TPUv4i" ], [ "Jouppi et al.", "Jouppi et al." ], [ "TPU v4i", "TPU v4i" ], [ "Product implementation and serving", "产品实现与推理服务" ], [ "C02", "C02" ] ], "sources": [ "C02" ] }, { "id": "c3", "values": [ [ "ISCA", "ISCA" ], [ "2023", "2023" ], [ "TPU v4: An Optically Reconfigurable Supercomputer", "TPU v4: An Optically Reconfigurable Supercomputer" ], [ "Jouppi et al.", "Jouppi et al." ], [ "TPU v4", "TPU v4" ], [ "Architecture / system", "架构／系统" ], [ "C03", "C03" ] ], "sources": [ "C03" ] }, { "id": "c4", "values": [ [ "Hot Chips", "Hot Chips" ], [ "2020", "2020" ], [ "Google training chips TPUv2 and TPUv3", "Google training chips TPUv2 and TPUv3" ], [ "Norrie / Patil", "Norrie / Patil" ], [ "v2-v3", "v2-v3" ], [ "Architecture", "架构" ], [ "C04", "C04" ] ], "sources": [ "C04" ] }, { "id": "c5", "values": [ [ "IEEE Micro", "IEEE Micro" ], [ "2026", "2026" ], [ "Google’s Training Supercomputers from TPU v2 to Ironwood", "Google’s Training Supercomputers from TPU v2 to Ironwood" ], [ "Google authors", "Google authors" ], [ "v2-v7", "v2-v7" ], [ "Implementation / system retrospective", "实现／系统回顾" ], [ "C05", "C05" ] ], "sources": [ "C05" ] }, { "id": "c6", "values": [ [ "SIGCOMM", "SIGCOMM" ], [ "2015 / 2022", "2015 / 2022" ], [ "Jupiter Rising / Jupiter Evolving", "Jupiter Rising / Jupiter Evolving" ], [ "Google authors", "Google authors" ], [ "Jupiter", "Jupiter" ], [ "Network systems", "网络系统" ], [ "C06 C07", "C06 C07" ] ], "sources": [ "C06", "C07" ] }, { "id": "c7", "values": [ [ "ASPLOS", "ASPLOS" ], [ "2021", "2021" ], [ "Warehouse-Scale Video Acceleration", "Warehouse-Scale Video Acceleration" ], [ "Ranganathan et al.", "Ranganathan et al." ], [ "Argos", "Argos" ], [ "Product co-design", "产品协同设计" ], [ "C08", "C08" ] ], "sources": [ "C08" ] }, { "id": "c8", "values": [ [ "Cloud Next", "Cloud Next" ], [ "2026", "2026" ], [ "TPU 8t / 8i architecture", "TPU 8t / 8i architecture" ], [ "Gupta / Mugazambi", "Gupta / Mugazambi" ], [ "TPU8", "TPU8" ], [ "Product announcement", "产品发布" ], [ "P08", "P08" ] ], "sources": [ "P08" ] }, { "id": "c9", "values": [ [ "Hot Chips", "Hot Chips" ], [ "2026", "2026" ], [ "The Eighth Generation TPU Family", "The Eighth Generation TPU Family" ], [ "Google", "Google" ], [ "TPU8", "TPU8" ], [ "Program verified; not recording analysis", "已核实议程；非录像分析" ], [ "C09", "C09" ] ], "sources": [ "C09" ] } ], "panels": [ [ 0, 1, 2 ], [ 0, 3, 4, 5, 6 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "crosswalk": { "id": "crosswalk", "title": [ "Names and boundaries", "名称及边界" ], "headers": [ [ "Name", "名称" ], [ "Maps to", "对应" ], [ "Boundary", "边界" ] ], "rows": [ { "id": "a", "values": [ [ "Trillium", "Trillium" ], [ "TPU v6e", "TPU v6e" ], [ "Efficiency branch", "效率分支" ] ], "sources": [ "P06" ] }, { "id": "b", "values": [ [ "Ironwood", "Ironwood" ], [ "TPU7x", "TPU7x" ], [ "Family name vs cloud configuration", "家族名与云端配置" ] ], "sources": [ "P07" ] }, { "id": "c", "values": [ [ "Axion", "Axion" ], [ "C4A / N4A", "C4A / N4A" ], [ "CPU brand vs VM series", "CPU 品牌与虚拟机系列" ] ], "sources": [ "P10" ] }, { "id": "d", "values": [ [ "TPU v4i", "TPU v4i" ], [ "Inference TPU", "Inference TPU" ], [ "Not training TPU v4", "区别于训练 TPU v4" ] ], "sources": [ "C02" ] }, { "id": "e", "values": [ [ "TPU 8t / 8i", "TPU 8t / 8i" ], [ "Training / serving", "Training / serving" ], [ "Separate architecture objectives", "不同架构目标" ] ], "sources": [ "P08" ] } ], "panels": [ [ 0, 1, 2 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "links": { "id": "links", "title": [ "ICI evolution", "ICI 演进" ], "headers": [ [ "Interconnect", "互联" ], [ "Year / generation", "年份／代际" ], [ "Lane rate", "通道速率" ], [ "Lanes / link", "每链路通道" ], [ "GB/s per link per direction", "每链路单向 GB/s" ], [ "Links / device", "每设备链路" ], [ "Topology", "拓扑" ], [ "Domain limit", "域规模" ], [ "Coherence / semantics", "一致性／语义" ] ], "rows": [ { "id": "v2", "values": [ [ "ICI", "ICI" ], [ "v2", "v2" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "2D torus", "2D torus" ], [ "256", "256" ], [ "Explicit collectives", "Explicit collectives" ] ], "sources": [ "C04" ] }, { "id": "v3", "values": [ [ "ICI", "ICI" ], [ "v3", "v3" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "2D torus", "2D torus" ], [ "1024", "1024" ], [ "Explicit collectives", "Explicit collectives" ] ], "sources": [ "C04" ] }, { "id": "v4", "values": [ [ "ICI", "ICI" ], [ "v4", "v4" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "50", "50" ], [ "6", "6" ], [ "3D torus / OCS", "3D torus / OCS" ], [ "4096", "4096" ], [ "Explicit collectives", "Explicit collectives" ] ], "sources": [ "C03", "C05" ] }, { "id": "v7", "values": [ [ "ICI", "ICI" ], [ "Ironwood", "Ironwood" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "100", "100" ], [ "6", "6" ], [ "3D torus", "3D torus" ], [ "9216", "9216" ], [ "Explicit collectives", "Explicit collectives" ] ], "sources": [ "P07", "C05" ] }, { "id": "v8", "values": [ [ "ICI / Boardfly", "ICI / Boardfly" ], [ "TPU8i", "TPU8i" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "Boardfly", "Boardfly" ], [ "1152 physical / ≤1024 active", "1152 physical / ≤1024 active" ], [ "Explicit collectives / CAE", "Explicit collectives / CAE" ] ], "sources": [ "P08" ] } ], "panels": [ [ 0, 1, 2, 3, 4 ], [ 0, 5, 6, 7, 8 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "system": { "id": "system", "title": [ "System domains", "系统域" ], "headers": [ [ "Platform", "平台" ], [ "Year / milestone", "年份／里程碑" ], [ "CPU / accelerator count", "CPU／加速器数量" ], [ "Scale-up domain", "纵向扩展域" ], [ "Scale-out per accelerator", "每加速器横向带宽" ], [ "Rack power", "机架功耗" ], [ "Cooling", "散热" ] ], "rows": [ { "id": "v4", "values": [ [ "TPUv4 pod", "TPUv4 pod" ], [ "2021", "2021" ], [ "4096 TPU chips", "4096 TPU chips" ], [ "4096", "4096" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "Liquid", "Liquid" ] ], "sources": [ "C03" ] }, { "id": "v7", "values": [ [ "Ironwood pod", "Ironwood pod" ], [ "2025", "2025" ], [ "9216 TPU chips", "9216 TPU chips" ], [ "9216", "9216" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "Liquid", "Liquid" ] ], "sources": [ "P07" ] }, { "id": "v8t", "values": [ [ "TPU8t", "TPU8t" ], [ "2026 announcement", "2026 announcement" ], [ "9600 TPU chips", "9600 TPU chips" ], [ "9600", "9600" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "Liquid", "Liquid" ] ], "sources": [ "P08" ] }, { "id": "v8i", "values": [ [ "TPU8i", "TPU8i" ], [ "2026 announcement", "2026 announcement" ], [ "1152 physical / ≤1024 active", "1152 physical / ≤1024 active" ], [ "Boardfly", "Boardfly" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "Liquid", "Liquid" ] ], "sources": [ "P08" ] } ], "panels": [ [ 0, 1, 2, 3 ], [ 0, 4, 5, 6 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "capacity_balance": { "id": "capacity_balance", "title": [ "Capacity and host balance", "容量与主机平衡" ], "headers": [ [ "Metric", "指标" ], [ "Value / calculation", "数值／计算" ], [ "Basis", "口径" ] ], "rows": [ { "id": "v4", "values": [ [ "TPUv4 HBM capacity/BF16", "TPUv4 HBM capacity/BF16" ], [ "32×2^30/(275×10^12) = 1.249×10^-4 B·s/FLOP", "32×2^30/(275×10^12) = 1.249×10^-4 B·s/FLOP" ], [ "Per chip; GiB converted to bytes", "每芯片；GiB 换算为字节" ] ], "sources": [ "C03" ] }, { "id": "v7", "values": [ [ "Ironwood HBM capacity/BF16", "Ironwood HBM capacity/BF16" ], [ "192×2^30/(2307×10^12) = 8.936×10^-5 B·s/FLOP", "192×2^30/(2307×10^12) = 8.936×10^-5 B·s/FLOP" ], [ "Per package; dense BF16", "每封装；稠密 BF16" ] ], "sources": [ "P07" ] }, { "id": "host", "values": [ [ "Axion DDR/core; L3/core", "Axion DDR/core; L3/core" ], [ "n/d", "n/d" ], [ "Physical CPU specifications incomplete", "物理 CPU 规格不完整" ] ], "sources": [ "P10" ] } ], "panels": [ [ 0, 1, 2 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "isscc": { "id": "isscc", "title": [ "ISSCC context and implementation topics", "ISSCC 背景与实现主题" ], "headers": [ [ "Venue", "会议／活动" ], [ "Year", "年份" ], [ "Paper / talk / disclosure", "论文／演讲／披露" ], [ "Presenter / authors", "报告人／作者" ], [ "Product", "产品" ], [ "Evidence type", "证据类型" ], [ "Source", "来源" ] ], "rows": [ { "id": "p", "values": [ [ "ISSCC plenary", "ISSCC plenary" ], [ "2018", "2018" ], [ "50 Years of Computer Architecture: From Mainframe CPUs to Neural-Network TPUs", "50 Years of Computer Architecture: From Mainframe CPUs to Neural-Network TPUs" ], [ "David Patterson", "David Patterson" ], [ "TPU / domain specialization", "TPU / domain specialization" ], [ "Official plenary record", "官方主旨报告记录" ], [ "C10", "C10" ] ], "sources": [ "C10" ] }, { "id": "d", "values": [ [ "ISSCC plenary", "ISSCC plenary" ], [ "2020", "2020" ], [ "The Deep Learning Revolution and Its Implications for Computer Architecture and Chip Design", "The Deep Learning Revolution and Its Implications for Computer Architecture and Chip Design" ], [ "Jeff Dean", "Jeff Dean" ], [ "TPU / chip-design context", "TPU / chip-design context" ], [ "Author companion paper and official record", "作者配套论文及官方记录" ], [ "C11 C10", "C11 C10" ] ], "sources": [ "C11", "C10" ] }, { "id": "g", "values": [ [ "ISSCC Forum 3", "ISSCC Forum 3" ], [ "2026", "2026" ], [ "Power Delivery Trends and Demands in Data-Center AI Processors", "Power Delivery Trends and Demands in Data-Center AI Processors" ], [ "Houle Gan", "Houle Gan" ], [ "Google datacenter processors", "Google datacenter processors" ], [ "Official program; not a per-generation circuit datasheet", "官方议程；非逐代电路数据表" ], [ "C12", "C12" ] ], "sources": [ "C12" ] } ], "panels": [ [ 0, 1, 2 ], [ 0, 3, 4, 5, 6 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" } }, "figures": { "era1": { "id": "era1", "title": [ "2017-2020: the training pod", "2017-2020：训练 Pod" ], "nodes": [ [ "host", [ "CPU host", "CPU 主机" ], 0, 0 ], [ "gpu", [ "TPU v2 / v3 + HBM", "TPU v2／v3 + HBM" ], 0, 1 ], [ "pod", [ "2D ICI torus", "二维 ICI 环面" ], 1, 1 ], [ "sw", [ "TensorFlow / XLA", "TensorFlow／XLA" ], 1, 0 ], [ "net", [ "Datacenter network", "数据中心网络" ], 0, 2 ] ], "edges": [ [ "host", "gpu", [ "PCIe", "PCIe" ] ], [ "gpu", "pod", [ "ICI", "ICI" ] ], [ "sw", "pod", [ "partition", "分区" ] ], [ "gpu", "net", [ "host path", "主机路径" ] ] ], "caption": [ "Logical roles, not a physical wiring diagram.", "逻辑角色图，并非物理布线图。" ] }, "era2": { "id": "era2", "title": [ "2021-2025: reconfigurable scale", "2021-2025：可重构扩展" ], "nodes": [ [ "host", [ "CPU host + offload", "CPU 主机 + 卸载" ], 0, 0 ], [ "gpu", [ "v4 / v5p / Ironwood", "v4／v5p／Ironwood" ], 0, 1 ], [ "pod", [ "ICI + optical circuits", "ICI + 光路交换" ], 1, 1 ], [ "sw", [ "JAX / XLA / kernels", "JAX／XLA／内核" ], 1, 0 ], [ "net", [ "Jupiter / storage", "Jupiter／存储" ], 0, 2 ] ], "edges": [ [ "host", "gpu", [ "PCIe", "PCIe" ] ], [ "gpu", "pod", [ "scale-up", "纵向扩展" ] ], [ "sw", "pod", [ "placement", "放置" ] ], [ "host", "net", [ "DCN", "DCN" ] ] ], "caption": [ "OCS changes connectivity; computation remains in the TPU.", "OCS 改变连接，计算仍在 TPU 中执行。" ] }, "era3": { "id": "era3", "title": [ "2026: separate training and serving systems", "2026：训练与服务系统分化" ], "nodes": [ [ "host", [ "Axion host", "Axion 主机" ], 0, 0 ], [ "gpu", [ "TPU 8t / 8i + HBM", "TPU 8t／8i + HBM" ], 0, 1 ], [ "pod", [ "Torus / Boardfly", "环面／Boardfly" ], 1, 1 ], [ "sw", [ "XLA / Pallas / Pathways", "XLA／Pallas／Pathways" ], 1, 0 ], [ "net", [ "Virgo / Jupiter / storage", "Virgo／Jupiter／存储" ], 0, 2 ] ], "edges": [ [ "host", "gpu", [ "host attach", "主机连接" ] ], [ "gpu", "pod", [ "ICI", "ICI" ] ], [ "sw", "pod", [ "schedule", "调度" ] ], [ "gpu", "net", [ "DCN / direct I/O", "DCN／直接 I/O" ] ] ], "caption": [ "Announced architecture; public GA is not inferred from this diagram.", "已公布架构；本图不推定已正式商用。" ] } }, "claims": { "cpu.c4a.0": { "value": "Axion / C4A", "field": "Generation / reference SKU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P11", "E01" ], "disclosure_date": "2024-10", "status": "shipping", "scope": "c4a" }, "cpu.c4a.1": { "value": "n/d", "field": "Codename", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P11", "E01" ], "disclosure_date": "2024-10", "status": "shipping", "scope": "c4a" }, "cpu.c4a.2": { "value": "2024-10", "field": "GA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P11", "E01" ], "disclosure_date": "2024-10", "status": "shipping", "scope": "c4a" }, "cpu.c4a.3": { "value": "Shipping / available", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P11", "E01" ], "disclosure_date": "2024-10", "status": "shipping", "scope": "c4a" }, "cpu.c4a.4": { "value": "Neoverse V2", "field": "Core µarch", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P11", "E01" ], "disclosure_date": "2024-10", "status": "shipping", "scope": "c4a" }, "cpu.c4a.5": { "value": "n/d physical; VM ≤72 vCPU", "field": "Cores / threads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P11", "E01" ], "disclosure_date": "2024-10", "status": "shipping", "scope": "c4a" }, "cpu.c4a.6": { "value": "n/d", "field": "Process per die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P11", "E01" ], "disclosure_date": "2024-10", "status": "shipping", "scope": "c4a" }, "cpu.c4a.7": { "value": "n/d", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P11", "E01" ], "disclosure_date": "2024-10", "status": "shipping", "scope": "c4a" }, "cpu.c4a.8": { "value": "n/d", "field": "L2 per core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P11", "E01" ], "disclosure_date": "2024-10", "status": "shipping", "scope": "c4a" }, "cpu.c4a.9": { "value": "n/d", "field": "L3 / domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P11", "E01" ], "disclosure_date": "2024-10", "status": "shipping", "scope": "c4a" }, "cpu.c4a.10": { "value": "DDR5; channels/rate n/d", "field": "Memory: channels; rate; GB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P11", "E01" ], "disclosure_date": "2024-10", "status": "shipping", "scope": "c4a" }, "cpu.c4a.11": { "value": "n/d", "field": "Sockets / links", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P11", "E01" ], "disclosure_date": "2024-10", "status": "shipping", "scope": "c4a" }, "cpu.c4a.12": { "value": "n/d", "field": "PCIe / CXL", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P11", "E01" ], "disclosure_date": "2024-10", "status": "shipping", "scope": "c4a" }, "cpu.c4a.13": { "value": "n/d", "field": "TDP", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P11", "E01" ], "disclosure_date": "2024-10", "status": "shipping", "scope": "c4a" }, "cpu.c4a.14": { "value": "Arm64; SVE2", "field": "Vector / matrix ISA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10", "P11", "E01" ], "disclosure_date": "2024-10", "status": "shipping", "scope": "c4a" }, "cpu.n4a.0": { "value": "Axion / N4A", "field": "Generation / reference SKU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-01-27", "status": "shipping", "scope": "n4a" }, "cpu.n4a.1": { "value": "n/d", "field": "Codename", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-01-27", "status": "shipping", "scope": "n4a" }, "cpu.n4a.2": { "value": "2026-01-27", "field": "GA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-01-27", "status": "shipping", "scope": "n4a" }, "cpu.n4a.3": { "value": "Shipping / available", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-01-27", "status": "shipping", "scope": "n4a" }, "cpu.n4a.4": { "value": "Neoverse N3", "field": "Core µarch", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-01-27", "status": "shipping", "scope": "n4a" }, "cpu.n4a.5": { "value": "n/d physical; VM ≤64 vCPU", "field": "Cores / threads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-01-27", "status": "shipping", "scope": "n4a" }, "cpu.n4a.6": { "value": "n/d", "field": "Process per die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-01-27", "status": "shipping", "scope": "n4a" }, "cpu.n4a.7": { "value": "n/d", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-01-27", "status": "shipping", "scope": "n4a" }, "cpu.n4a.8": { "value": "n/d", "field": "L2 per core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-01-27", "status": "shipping", "scope": "n4a" }, "cpu.n4a.9": { "value": "n/d", "field": "L3 / domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-01-27", "status": "shipping", "scope": "n4a" }, "cpu.n4a.10": { "value": "DDR5; VM ≤512 GB; peak n/d", "field": "Memory: channels; rate; GB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-01-27", "status": "shipping", "scope": "n4a" }, "cpu.n4a.11": { "value": "n/d", "field": "Sockets / links", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-01-27", "status": "shipping", "scope": "n4a" }, "cpu.n4a.12": { "value": "n/d", "field": "PCIe / CXL", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-01-27", "status": "shipping", "scope": "n4a" }, "cpu.n4a.13": { "value": "n/d", "field": "TDP", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-01-27", "status": "shipping", "scope": "n4a" }, "cpu.n4a.14": { "value": "Arm64", "field": "Vector / matrix ISA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-01-27", "status": "shipping", "scope": "n4a" }, "gpu.v1.0": { "value": "TPU v1", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "C02" ], "disclosure_date": "2015 Q2", "status": "deployed", "scope": "v1" }, "gpu.v1.1": { "value": "INT8 systolic", "field": "Architecture", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "C02" ], "disclosure_date": "2015 Q2", "status": "deployed", "scope": "v1" }, "gpu.v1.2": { "value": "2015 Q2", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "C02" ], "disclosure_date": "2015 Q2", "status": "deployed", "scope": "v1" }, "gpu.v1.3": { "value": "Historical shipping", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "C02" ], "disclosure_date": "2015 Q2", "status": "deployed", "scope": "v1" }, "gpu.v1.4": { "value": "28 nm", "field": "Process", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "C02" ], "disclosure_date": "2015 Q2", "status": "deployed", "scope": "v1" }, "gpu.v1.5": { "value": "1", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "C02" ], "disclosure_date": "2015 Q2", "status": "deployed", "scope": "v1" }, "gpu.v1.6": { "value": "1 × 256×256", "field": "Compute units", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "C02" ], "disclosure_date": "2015 Q2", "status": "deployed", "scope": "v1" }, "gpu.v1.7": { "value": "n/a", "field": "Dense BF16", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "C02" ], "disclosure_date": "2015 Q2", "status": "deployed", "scope": "v1" }, "gpu.v1.8": { "value": "n/a", "field": "Dense FP8", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "C02" ], "disclosure_date": "2015 Q2", "status": "deployed", "scope": "v1" }, "gpu.v1.9": { "value": "n/a", "field": "Dense FP6 / FP4", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "C02" ], "disclosure_date": "2015 Q2", "status": "deployed", "scope": "v1" }, "gpu.v1.10": { "value": "n/d", "field": "FP64 vector / matrix", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "C02" ], "disclosure_date": "2015 Q2", "status": "deployed", "scope": "v1" }, "gpu.v1.11": { "value": "DDR3; 8 GB; 0.034 TB/s", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "C02" ], "disclosure_date": "2015 Q2", "status": "deployed", "scope": "v1" }, "gpu.v1.12": { "value": "28 MB", "field": "LLC / SRAM", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "C02" ], "disclosure_date": "2015 Q2", "status": "deployed", "scope": "v1" }, "gpu.v1.13": { "value": "n/a", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "C02" ], "disclosure_date": "2015 Q2", "status": "deployed", "scope": "v1" }, "gpu.v1.14": { "value": "PCIe; n/d", "field": "Host link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "C02" ], "disclosure_date": "2015 Q2", "status": "deployed", "scope": "v1" }, "gpu.v1.15": { "value": "75 W chip TDP", "field": "Power / cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "C02" ], "disclosure_date": "2015 Q2", "status": "deployed", "scope": "v1" }, "gpu.v1.16": { "value": "Google platform", "field": "Form factor", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "C02" ], "disclosure_date": "2015 Q2", "status": "deployed", "scope": "v1" }, "gpu.v2.0": { "value": "TPU v2", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2017 Q3", "status": "deployed", "scope": "v2" }, "gpu.v2.1": { "value": "TensorCore", "field": "Architecture", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2017 Q3", "status": "deployed", "scope": "v2" }, "gpu.v2.2": { "value": "2017 Q3", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2017 Q3", "status": "deployed", "scope": "v2" }, "gpu.v2.3": { "value": "Historical shipping", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2017 Q3", "status": "deployed", "scope": "v2" }, "gpu.v2.4": { "value": "16 nm", "field": "Process", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2017 Q3", "status": "deployed", "scope": "v2" }, "gpu.v2.5": { "value": "1", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2017 Q3", "status": "deployed", "scope": "v2" }, "gpu.v2.6": { "value": "2 TC", "field": "Compute units", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2017 Q3", "status": "deployed", "scope": "v2" }, "gpu.v2.7": { "value": "46 TFLOPS", "field": "Dense BF16", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2017 Q3", "status": "deployed", "scope": "v2" }, "gpu.v2.8": { "value": "n/a", "field": "Dense FP8", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2017 Q3", "status": "deployed", "scope": "v2" }, "gpu.v2.9": { "value": "n/a", "field": "Dense FP6 / FP4", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2017 Q3", "status": "deployed", "scope": "v2" }, "gpu.v2.10": { "value": "n/d", "field": "FP64 vector / matrix", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2017 Q3", "status": "deployed", "scope": "v2" }, "gpu.v2.11": { "value": "HBM2; 16 GiB; 0.700 TB/s", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2017 Q3", "status": "deployed", "scope": "v2" }, "gpu.v2.12": { "value": "32 MiB", "field": "LLC / SRAM", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2017 Q3", "status": "deployed", "scope": "v2" }, "gpu.v2.13": { "value": "2D torus; 256 chips; direction n/d", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2017 Q3", "status": "deployed", "scope": "v2" }, "gpu.v2.14": { "value": "PCIe; n/d", "field": "Host link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2017 Q3", "status": "deployed", "scope": "v2" }, "gpu.v2.15": { "value": "280 W chip TDP; air", "field": "Power / cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2017 Q3", "status": "deployed", "scope": "v2" }, "gpu.v2.16": { "value": "Google platform", "field": "Form factor", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2017 Q3", "status": "deployed", "scope": "v2" }, "gpu.v3.0": { "value": "TPU v3", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2018 Q4", "status": "deployed", "scope": "v3" }, "gpu.v3.1": { "value": "TensorCore", "field": "Architecture", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2018 Q4", "status": "deployed", "scope": "v3" }, "gpu.v3.2": { "value": "2018 Q4", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2018 Q4", "status": "deployed", "scope": "v3" }, "gpu.v3.3": { "value": "Historical shipping", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2018 Q4", "status": "deployed", "scope": "v3" }, "gpu.v3.4": { "value": "16 nm", "field": "Process", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2018 Q4", "status": "deployed", "scope": "v3" }, "gpu.v3.5": { "value": "1", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2018 Q4", "status": "deployed", "scope": "v3" }, "gpu.v3.6": { "value": "2 TC", "field": "Compute units", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2018 Q4", "status": "deployed", "scope": "v3" }, "gpu.v3.7": { "value": "123 TFLOPS", "field": "Dense BF16", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2018 Q4", "status": "deployed", "scope": "v3" }, "gpu.v3.8": { "value": "n/a", "field": "Dense FP8", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2018 Q4", "status": "deployed", "scope": "v3" }, "gpu.v3.9": { "value": "n/a", "field": "Dense FP6 / FP4", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2018 Q4", "status": "deployed", "scope": "v3" }, "gpu.v3.10": { "value": "n/d", "field": "FP64 vector / matrix", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2018 Q4", "status": "deployed", "scope": "v3" }, "gpu.v3.11": { "value": "HBM2; 4 stacks; 32 GiB; 0.900 TB/s", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2018 Q4", "status": "deployed", "scope": "v3" }, "gpu.v3.12": { "value": "32 MiB", "field": "LLC / SRAM", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2018 Q4", "status": "deployed", "scope": "v3" }, "gpu.v3.13": { "value": "2D torus; 1,024 chips", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2018 Q4", "status": "deployed", "scope": "v3" }, "gpu.v3.14": { "value": "PCIe; n/d", "field": "Host link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2018 Q4", "status": "deployed", "scope": "v3" }, "gpu.v3.15": { "value": "450 W chip TDP; liquid", "field": "Power / cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2018 Q4", "status": "deployed", "scope": "v3" }, "gpu.v3.16": { "value": "Google platform", "field": "Form factor", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2018 Q4", "status": "deployed", "scope": "v3" }, "gpu.v4i.0": { "value": "TPU v4i", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2020 Q1", "status": "deployed", "scope": "v4i" }, "gpu.v4i.1": { "value": "Inference", "field": "Architecture", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2020 Q1", "status": "deployed", "scope": "v4i" }, "gpu.v4i.2": { "value": "2020 Q1", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2020 Q1", "status": "deployed", "scope": "v4i" }, "gpu.v4i.3": { "value": "Historical shipping", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2020 Q1", "status": "deployed", "scope": "v4i" }, "gpu.v4i.4": { "value": "7 nm", "field": "Process", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2020 Q1", "status": "deployed", "scope": "v4i" }, "gpu.v4i.5": { "value": "1", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2020 Q1", "status": "deployed", "scope": "v4i" }, "gpu.v4i.6": { "value": "1 TC; 4 MXU", "field": "Compute units", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2020 Q1", "status": "deployed", "scope": "v4i" }, "gpu.v4i.7": { "value": "138 TFLOPS", "field": "Dense BF16", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2020 Q1", "status": "deployed", "scope": "v4i" }, "gpu.v4i.8": { "value": "n/a", "field": "Dense FP8", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2020 Q1", "status": "deployed", "scope": "v4i" }, "gpu.v4i.9": { "value": "n/a", "field": "Dense FP6 / FP4", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2020 Q1", "status": "deployed", "scope": "v4i" }, "gpu.v4i.10": { "value": "n/d", "field": "FP64 vector / matrix", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2020 Q1", "status": "deployed", "scope": "v4i" }, "gpu.v4i.11": { "value": "HBM; 8 GB; 0.614 TB/s", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2020 Q1", "status": "deployed", "scope": "v4i" }, "gpu.v4i.12": { "value": "144 MB", "field": "LLC / SRAM", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2020 Q1", "status": "deployed", "scope": "v4i" }, "gpu.v4i.13": { "value": "2 × 400 Gb/s; direction n/d", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2020 Q1", "status": "deployed", "scope": "v4i" }, "gpu.v4i.14": { "value": "PCIe; n/d", "field": "Host link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2020 Q1", "status": "deployed", "scope": "v4i" }, "gpu.v4i.15": { "value": "175 W chip TDP", "field": "Power / cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2020 Q1", "status": "deployed", "scope": "v4i" }, "gpu.v4i.16": { "value": "Google platform", "field": "Form factor", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2020 Q1", "status": "deployed", "scope": "v4i" }, "gpu.v4.0": { "value": "TPU v4", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03", "C05" ], "disclosure_date": "2021 deployment", "status": "deployed", "scope": "v4" }, "gpu.v4.1": { "value": "TensorCore + SparseCore", "field": "Architecture", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03", "C05" ], "disclosure_date": "2021 deployment", "status": "deployed", "scope": "v4" }, "gpu.v4.2": { "value": "2021 deployment", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03", "C05" ], "disclosure_date": "2021 deployment", "status": "deployed", "scope": "v4" }, "gpu.v4.3": { "value": "Historical shipping", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03", "C05" ], "disclosure_date": "2021 deployment", "status": "deployed", "scope": "v4" }, "gpu.v4.4": { "value": "7 nm", "field": "Process", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03", "C05" ], "disclosure_date": "2021 deployment", "status": "deployed", "scope": "v4" }, "gpu.v4.5": { "value": "1", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03", "C05" ], "disclosure_date": "2021 deployment", "status": "deployed", "scope": "v4" }, "gpu.v4.6": { "value": "2 TC; 4 SC", "field": "Compute units", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03", "C05" ], "disclosure_date": "2021 deployment", "status": "deployed", "scope": "v4" }, "gpu.v4.7": { "value": "275 TFLOPS", "field": "Dense BF16", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03", "C05" ], "disclosure_date": "2021 deployment", "status": "deployed", "scope": "v4" }, "gpu.v4.8": { "value": "n/a", "field": "Dense FP8", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03", "C05" ], "disclosure_date": "2021 deployment", "status": "deployed", "scope": "v4" }, "gpu.v4.9": { "value": "n/a", "field": "Dense FP6 / FP4", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03", "C05" ], "disclosure_date": "2021 deployment", "status": "deployed", "scope": "v4" }, "gpu.v4.10": { "value": "n/d", "field": "FP64 vector / matrix", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03", "C05" ], "disclosure_date": "2021 deployment", "status": "deployed", "scope": "v4" }, "gpu.v4.11": { "value": "HBM2; 4 stacks; 32 GiB; 1.2 TB/s", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03", "C05" ], "disclosure_date": "2021 deployment", "status": "deployed", "scope": "v4" }, "gpu.v4.12": { "value": "32 MiB", "field": "LLC / SRAM", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03", "C05" ], "disclosure_date": "2021 deployment", "status": "deployed", "scope": "v4" }, "gpu.v4.13": { "value": "6 × 50 GB/s/direction; 4,096", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03", "C05" ], "disclosure_date": "2021 deployment", "status": "deployed", "scope": "v4" }, "gpu.v4.14": { "value": "PCIe; n/d", "field": "Host link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03", "C05" ], "disclosure_date": "2021 deployment", "status": "deployed", "scope": "v4" }, "gpu.v4.15": { "value": "liquid; TDP n/d", "field": "Power / cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03", "C05" ], "disclosure_date": "2021 deployment", "status": "deployed", "scope": "v4" }, "gpu.v4.16": { "value": "Google platform", "field": "Form factor", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03", "C05" ], "disclosure_date": "2021 deployment", "status": "deployed", "scope": "v4" }, "gpu.v5e.0": { "value": "TPU v5e", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2023", "status": "deployed", "scope": "v5e" }, "gpu.v5e.1": { "value": "Efficiency", "field": "Architecture", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2023", "status": "deployed", "scope": "v5e" }, "gpu.v5e.2": { "value": "2023", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2023", "status": "deployed", "scope": "v5e" }, "gpu.v5e.3": { "value": "Shipping / available", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2023", "status": "deployed", "scope": "v5e" }, "gpu.v5e.4": { "value": "n/d", "field": "Process", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2023", "status": "deployed", "scope": "v5e" }, "gpu.v5e.5": { "value": "n/d", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2023", "status": "deployed", "scope": "v5e" }, "gpu.v5e.6": { "value": "1 TC", "field": "Compute units", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2023", "status": "deployed", "scope": "v5e" }, "gpu.v5e.7": { "value": "197 TFLOPS", "field": "Dense BF16", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2023", "status": "deployed", "scope": "v5e" }, "gpu.v5e.8": { "value": "n/d", "field": "Dense FP8", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2023", "status": "deployed", "scope": "v5e" }, "gpu.v5e.9": { "value": "n/a", "field": "Dense FP6 / FP4", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2023", "status": "deployed", "scope": "v5e" }, "gpu.v5e.10": { "value": "n/d", "field": "FP64 vector / matrix", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2023", "status": "deployed", "scope": "v5e" }, "gpu.v5e.11": { "value": "HBM; stacks n/d; 16 GB; 0.819 TB/s", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2023", "status": "deployed", "scope": "v5e" }, "gpu.v5e.12": { "value": "n/d", "field": "LLC / SRAM", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2023", "status": "deployed", "scope": "v5e" }, "gpu.v5e.13": { "value": "256 chips; 400 GB/s bidirectional", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2023", "status": "deployed", "scope": "v5e" }, "gpu.v5e.14": { "value": "PCIe; n/d", "field": "Host link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2023", "status": "deployed", "scope": "v5e" }, "gpu.v5e.15": { "value": "n/d", "field": "Power / cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2023", "status": "deployed", "scope": "v5e" }, "gpu.v5e.16": { "value": "Google platform", "field": "Form factor", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04" ], "disclosure_date": "2023", "status": "deployed", "scope": "v5e" }, "gpu.v5p.0": { "value": "TPU v5p", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P07", "C05" ], "disclosure_date": "2023 preview; GA n/d", "status": "deployed", "scope": "v5p" }, "gpu.v5p.1": { "value": "Performance", "field": "Architecture", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P07", "C05" ], "disclosure_date": "2023 preview; GA n/d", "status": "deployed", "scope": "v5p" }, "gpu.v5p.2": { "value": "2023 preview; GA n/d", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P07", "C05" ], "disclosure_date": "2023 preview; GA n/d", "status": "deployed", "scope": "v5p" }, "gpu.v5p.3": { "value": "Shipping / available", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P07", "C05" ], "disclosure_date": "2023 preview; GA n/d", "status": "deployed", "scope": "v5p" }, "gpu.v5p.4": { "value": "n/d", "field": "Process", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P07", "C05" ], "disclosure_date": "2023 preview; GA n/d", "status": "deployed", "scope": "v5p" }, "gpu.v5p.5": { "value": "1", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P07", "C05" ], "disclosure_date": "2023 preview; GA n/d", "status": "deployed", "scope": "v5p" }, "gpu.v5p.6": { "value": "2 TC; 4 SC", "field": "Compute units", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P07", "C05" ], "disclosure_date": "2023 preview; GA n/d", "status": "deployed", "scope": "v5p" }, "gpu.v5p.7": { "value": "459 TFLOPS", "field": "Dense BF16", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P07", "C05" ], "disclosure_date": "2023 preview; GA n/d", "status": "deployed", "scope": "v5p" }, "gpu.v5p.8": { "value": "459 TFLOPS", "field": "Dense FP8", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P07", "C05" ], "disclosure_date": "2023 preview; GA n/d", "status": "deployed", "scope": "v5p" }, "gpu.v5p.9": { "value": "n/a", "field": "Dense FP6 / FP4", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P07", "C05" ], "disclosure_date": "2023 preview; GA n/d", "status": "deployed", "scope": "v5p" }, "gpu.v5p.10": { "value": "n/d", "field": "FP64 vector / matrix", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P07", "C05" ], "disclosure_date": "2023 preview; GA n/d", "status": "deployed", "scope": "v5p" }, "gpu.v5p.11": { "value": "HBM2e; 6 stacks; 95 GiB usable; 2.765 TB/s", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P07", "C05" ], "disclosure_date": "2023 preview; GA n/d", "status": "deployed", "scope": "v5p" }, "gpu.v5p.12": { "value": "128 MiB", "field": "LLC / SRAM", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P07", "C05" ], "disclosure_date": "2023 preview; GA n/d", "status": "deployed", "scope": "v5p" }, "gpu.v5p.13": { "value": "6 × 100 GB/s/direction; 8,960", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P07", "C05" ], "disclosure_date": "2023 preview; GA n/d", "status": "deployed", "scope": "v5p" }, "gpu.v5p.14": { "value": "PCIe; n/d", "field": "Host link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P07", "C05" ], "disclosure_date": "2023 preview; GA n/d", "status": "deployed", "scope": "v5p" }, "gpu.v5p.15": { "value": "liquid; TDP n/d", "field": "Power / cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P07", "C05" ], "disclosure_date": "2023 preview; GA n/d", "status": "deployed", "scope": "v5p" }, "gpu.v5p.16": { "value": "Google platform", "field": "Form factor", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P07", "C05" ], "disclosure_date": "2023 preview; GA n/d", "status": "deployed", "scope": "v5p" }, "gpu.v6e.0": { "value": "TPU v6e", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P07" ], "disclosure_date": "2024", "status": "deployed", "scope": "v6e" }, "gpu.v6e.1": { "value": "Trillium", "field": "Architecture", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P07" ], "disclosure_date": "2024", "status": "deployed", "scope": "v6e" }, "gpu.v6e.2": { "value": "2024", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P07" ], "disclosure_date": "2024", "status": "deployed", "scope": "v6e" }, "gpu.v6e.3": { "value": "Shipping / available", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P07" ], "disclosure_date": "2024", "status": "deployed", "scope": "v6e" }, "gpu.v6e.4": { "value": "n/d", "field": "Process", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P07" ], "disclosure_date": "2024", "status": "deployed", "scope": "v6e" }, "gpu.v6e.5": { "value": "n/d", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P07" ], "disclosure_date": "2024", "status": "deployed", "scope": "v6e" }, "gpu.v6e.6": { "value": "1 TC; 2 SC", "field": "Compute units", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P07" ], "disclosure_date": "2024", "status": "deployed", "scope": "v6e" }, "gpu.v6e.7": { "value": "918 TFLOPS", "field": "Dense BF16", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P07" ], "disclosure_date": "2024", "status": "deployed", "scope": "v6e" }, "gpu.v6e.8": { "value": "918 TFLOPS", "field": "Dense FP8", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P07" ], "disclosure_date": "2024", "status": "deployed", "scope": "v6e" }, "gpu.v6e.9": { "value": "n/a", "field": "Dense FP6 / FP4", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P07" ], "disclosure_date": "2024", "status": "deployed", "scope": "v6e" }, "gpu.v6e.10": { "value": "n/d", "field": "FP64 vector / matrix", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P07" ], "disclosure_date": "2024", "status": "deployed", "scope": "v6e" }, "gpu.v6e.11": { "value": "HBM; stacks n/d; 32 GiB; 1.638 TB/s", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P07" ], "disclosure_date": "2024", "status": "deployed", "scope": "v6e" }, "gpu.v6e.12": { "value": "n/d", "field": "LLC / SRAM", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P07" ], "disclosure_date": "2024", "status": "deployed", "scope": "v6e" }, "gpu.v6e.13": { "value": "256 chips; 800 GB/s bidirectional", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P07" ], "disclosure_date": "2024", "status": "deployed", "scope": "v6e" }, "gpu.v6e.14": { "value": "PCIe; n/d", "field": "Host link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P07" ], "disclosure_date": "2024", "status": "deployed", "scope": "v6e" }, "gpu.v6e.15": { "value": "n/d", "field": "Power / cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P07" ], "disclosure_date": "2024", "status": "deployed", "scope": "v6e" }, "gpu.v6e.16": { "value": "Google platform", "field": "Form factor", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P07" ], "disclosure_date": "2024", "status": "deployed", "scope": "v6e" }, "gpu.v7.0": { "value": "TPU7x", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C05", "E02" ], "disclosure_date": "2025", "status": "deployed", "scope": "v7" }, "gpu.v7.1": { "value": "Ironwood", "field": "Architecture", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C05", "E02" ], "disclosure_date": "2025", "status": "deployed", "scope": "v7" }, "gpu.v7.2": { "value": "2025", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C05", "E02" ], "disclosure_date": "2025", "status": "deployed", "scope": "v7" }, "gpu.v7.3": { "value": "Shipping / available", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C05", "E02" ], "disclosure_date": "2025", "status": "deployed", "scope": "v7" }, "gpu.v7.4": { "value": "n/d", "field": "Process", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C05", "E02" ], "disclosure_date": "2025", "status": "deployed", "scope": "v7" }, "gpu.v7.5": { "value": "2 compute chiplets", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C05", "E02" ], "disclosure_date": "2025", "status": "deployed", "scope": "v7" }, "gpu.v7.6": { "value": "2 TC; 4 SC", "field": "Compute units", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C05", "E02" ], "disclosure_date": "2025", "status": "deployed", "scope": "v7" }, "gpu.v7.7": { "value": "2,307 TFLOPS", "field": "Dense BF16", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C05", "E02" ], "disclosure_date": "2025", "status": "deployed", "scope": "v7" }, "gpu.v7.8": { "value": "4,614 TFLOPS", "field": "Dense FP8", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C05", "E02" ], "disclosure_date": "2025", "status": "deployed", "scope": "v7" }, "gpu.v7.9": { "value": "n/a", "field": "Dense FP6 / FP4", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C05", "E02" ], "disclosure_date": "2025", "status": "deployed", "scope": "v7" }, "gpu.v7.10": { "value": "n/d", "field": "FP64 vector / matrix", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C05", "E02" ], "disclosure_date": "2025", "status": "deployed", "scope": "v7" }, "gpu.v7.11": { "value": "HBM3e; 8 stacks; 192 GiB; 7.380 TB/s", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C05", "E02" ], "disclosure_date": "2025", "status": "deployed", "scope": "v7" }, "gpu.v7.12": { "value": "128 MiB", "field": "LLC / SRAM", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C05", "E02" ], "disclosure_date": "2025", "status": "deployed", "scope": "v7" }, "gpu.v7.13": { "value": "6 × 100 GB/s/direction; 9,216", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C05", "E02" ], "disclosure_date": "2025", "status": "deployed", "scope": "v7" }, "gpu.v7.14": { "value": "PCIe; n/d", "field": "Host link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C05", "E02" ], "disclosure_date": "2025", "status": "deployed", "scope": "v7" }, "gpu.v7.15": { "value": "liquid; TDP n/d", "field": "Power / cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C05", "E02" ], "disclosure_date": "2025", "status": "deployed", "scope": "v7" }, "gpu.v7.16": { "value": "Google platform", "field": "Form factor", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C05", "E02" ], "disclosure_date": "2025", "status": "deployed", "scope": "v7" }, "gpu.v8t.0": { "value": "TPU 8t", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8t" }, "gpu.v8t.1": { "value": "Training", "field": "Architecture", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8t" }, "gpu.v8t.2": { "value": "2026-04-22", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8t" }, "gpu.v8t.3": { "value": "Announced; GA n/d", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8t" }, "gpu.v8t.4": { "value": "n/d", "field": "Process", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8t" }, "gpu.v8t.5": { "value": "n/d", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8t" }, "gpu.v8t.6": { "value": "n/d", "field": "Compute units", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8t" }, "gpu.v8t.7": { "value": "n/d", "field": "Dense BF16", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8t" }, "gpu.v8t.8": { "value": "n/d", "field": "Dense FP8", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8t" }, "gpu.v8t.9": { "value": "12.6 PFLOPS FP4; dense basis n/d", "field": "Dense FP6 / FP4", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8t" }, "gpu.v8t.10": { "value": "n/d", "field": "FP64 vector / matrix", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8t" }, "gpu.v8t.11": { "value": "216 GB; 6.528 TB/s", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8t" }, "gpu.v8t.12": { "value": "128 MB", "field": "LLC / SRAM", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8t" }, "gpu.v8t.13": { "value": "3D torus; 9,600", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8t" }, "gpu.v8t.14": { "value": "PCIe; n/d", "field": "Host link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8t" }, "gpu.v8t.15": { "value": "liquid; TDP n/d", "field": "Power / cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8t" }, "gpu.v8t.16": { "value": "Google platform", "field": "Form factor", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8t" }, "gpu.v8i.0": { "value": "TPU 8i", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8i" }, "gpu.v8i.1": { "value": "Serving / CAE", "field": "Architecture", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8i" }, "gpu.v8i.2": { "value": "2026-04-22", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8i" }, "gpu.v8i.3": { "value": "Announced; GA n/d", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8i" }, "gpu.v8i.4": { "value": "n/d", "field": "Process", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8i" }, "gpu.v8i.5": { "value": "compute + CAE chiplet", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8i" }, "gpu.v8i.6": { "value": "2 TC; 1 CAE", "field": "Compute units", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8i" }, "gpu.v8i.7": { "value": "n/d", "field": "Dense BF16", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8i" }, "gpu.v8i.8": { "value": "n/d", "field": "Dense FP8", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8i" }, "gpu.v8i.9": { "value": "10.1 PFLOPS FP4; dense basis n/d", "field": "Dense FP6 / FP4", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8i" }, "gpu.v8i.10": { "value": "n/d", "field": "FP64 vector / matrix", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8i" }, "gpu.v8i.11": { "value": "288 GB; 8.601 TB/s", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8i" }, "gpu.v8i.12": { "value": "384 MB", "field": "LLC / SRAM", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8i" }, "gpu.v8i.13": { "value": "Boardfly: 1,152 physical / ≤1,024 active", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8i" }, "gpu.v8i.14": { "value": "PCIe; n/d", "field": "Host link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8i" }, "gpu.v8i.15": { "value": "liquid; TDP n/d", "field": "Power / cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8i" }, "gpu.v8i.16": { "value": "Google platform", "field": "Form factor", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E03" ], "disclosure_date": "2026-04-22", "status": "announced", "scope": "v8i" }, "net.t.0": { "value": "Titanium", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "t" }, "net.t.1": { "value": "n/d", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "t" }, "net.t.2": { "value": "Shipping / available", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "t" }, "net.t.3": { "value": "Infrastructure offload", "field": "Class", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "t" }, "net.t.4": { "value": "n/d", "field": "Ports × speed", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "t" }, "net.t.5": { "value": "n/d", "field": "SerDes", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "t" }, "net.t.6": { "value": "n/d", "field": "Host interface", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "t" }, "net.t.7": { "value": "n/d", "field": "Programmable engine", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "t" }, "net.t.8": { "value": "n/d", "field": "Embedded CPU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "t" }, "net.t.9": { "value": "n/d", "field": "On-card memory", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "t" }, "net.t.10": { "value": "n/d", "field": "Transport / RDMA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "t" }, "net.t.11": { "value": "n/d", "field": "Congestion control", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "t" }, "net.t.12": { "value": "Networking/storage", "field": "Key offloads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "t" }, "net.t.13": { "value": "n/d", "field": "Power", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "t" }, "net.j.0": { "value": "Jupiter", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C06", "C07" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "j" }, "net.j.1": { "value": "n/d", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C06", "C07" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "j" }, "net.j.2": { "value": "Shipping / available", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C06", "C07" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "j" }, "net.j.3": { "value": "Datacenter fabric", "field": "Class", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C06", "C07" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "j" }, "net.j.4": { "value": "n/d", "field": "Ports × speed", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C06", "C07" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "j" }, "net.j.5": { "value": "n/d", "field": "SerDes", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C06", "C07" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "j" }, "net.j.6": { "value": "n/d", "field": "Host interface", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C06", "C07" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "j" }, "net.j.7": { "value": "n/d", "field": "Programmable engine", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C06", "C07" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "j" }, "net.j.8": { "value": "n/d", "field": "Embedded CPU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C06", "C07" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "j" }, "net.j.9": { "value": "n/d", "field": "On-card memory", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C06", "C07" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "j" }, "net.j.10": { "value": "Ethernet", "field": "Transport / RDMA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C06", "C07" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "j" }, "net.j.11": { "value": "n/d", "field": "Congestion control", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C06", "C07" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "j" }, "net.j.12": { "value": "Fabric control", "field": "Key offloads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C06", "C07" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "j" }, "net.j.13": { "value": "n/d", "field": "Power", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C06", "C07" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "j" }, "net.f.0": { "value": "Falcon", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P14" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "f" }, "net.f.1": { "value": "n/d", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P14" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "f" }, "net.f.2": { "value": "Shipping / available", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P14" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "f" }, "net.f.3": { "value": "Transport; not a NIC SKU", "field": "Class", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P14" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "f" }, "net.f.4": { "value": "n/d", "field": "Ports × speed", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P14" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "f" }, "net.f.5": { "value": "n/d", "field": "SerDes", "basis": "Per reference product; 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theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03", "C05" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "v4" }, "links.v4.8": { "value": "Explicit collectives", "field": "Coherence / semantics", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03", "C05" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "v4" }, "links.v7.0": { "value": "ICI", "field": "Interconnect", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C05" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "v7" }, "links.v7.1": { "value": "Ironwood", "field": "Year / generation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C05" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "v7" }, "links.v7.2": { "value": "n/d", "field": "Lane rate", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C05" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "v7" }, "links.v7.3": { "value": "n/d", "field": "Lanes / link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C05" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "v7" }, "links.v7.4": { "value": "100", "field": "GB/s per link per direction", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C05" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "v7" }, "links.v7.5": { "value": "6", "field": "Links / device", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C05" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "v7" }, "links.v7.6": { "value": "3D torus", "field": "Topology", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C05" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "v7" }, "links.v7.7": { "value": "9216", "field": "Domain limit", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C05" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "v7" }, "links.v7.8": { "value": "Explicit collectives", "field": "Coherence / semantics", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "C05" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "v7" }, "links.v8.0": { "value": "ICI / Boardfly", "field": "Interconnect", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2026-09-28", "status": "announced", "scope": "v8" }, "links.v8.1": { "value": "TPU8i", "field": "Year / generation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2026-09-28", "status": "announced", "scope": "v8" }, "links.v8.2": { "value": "n/d", "field": "Lane rate", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2026-09-28", "status": "announced", "scope": "v8" }, "links.v8.3": { "value": "n/d", "field": "Lanes / link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2026-09-28", "status": "announced", "scope": "v8" }, "links.v8.4": { "value": "n/d", "field": "GB/s per link per direction", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2026-09-28", "status": "announced", "scope": "v8" }, "links.v8.5": { "value": "n/d", "field": "Links / device", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2026-09-28", "status": "announced", "scope": "v8" }, "links.v8.6": { "value": "Boardfly", "field": "Topology", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2026-09-28", "status": "announced", "scope": "v8" }, "links.v8.7": { "value": "1152 physical / ≤1024 active", "field": "Domain limit", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2026-09-28", "status": "announced", "scope": "v8" }, "links.v8.8": { "value": "Explicit collectives / CAE", "field": "Coherence / semantics", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2026-09-28", "status": "announced", "scope": "v8" }, "system.v4.0": { "value": "TPUv4 pod", "field": "Platform", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "v4" }, "system.v4.1": { "value": "2021", "field": "Year / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "v4" }, "system.v4.2": { "value": "4096 TPU chips", "field": "CPU / accelerator count", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "v4" }, "system.v4.3": { "value": "4096", "field": "Scale-up domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "v4" }, "system.v4.4": { "value": "n/d", "field": "Scale-out per accelerator", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "v4" }, "system.v4.5": { "value": "n/d", "field": "Rack power", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "v4" }, "system.v4.6": { "value": "Liquid", "field": "Cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2026-09-28", "status": "deployed", "scope": "v4" }, "system.v7.0": { "value": "Ironwood pod", "field": "Platform", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "v7" }, "system.v7.1": { "value": "2025", "field": "Year / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "v7" }, "system.v7.2": { "value": "9216 TPU chips", "field": "CPU / accelerator count", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "v7" }, "system.v7.3": { "value": "9216", "field": "Scale-up domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "v7" }, "system.v7.4": { "value": "n/d", "field": "Scale-out per accelerator", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "v7" }, "system.v7.5": { "value": "n/d", "field": "Rack power", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "v7" }, "system.v7.6": { "value": "Liquid", "field": "Cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "v7" }, "system.v8t.0": { "value": "TPU8t", "field": "Platform", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2026-09-28", "status": "announced", "scope": "v8t" }, "system.v8t.1": { "value": "2026 announcement", "field": "Year / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2026-09-28", "status": "announced", "scope": "v8t" }, "system.v8t.2": { "value": "9600 TPU chips", "field": "CPU / accelerator count", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2026-09-28", "status": "announced", "scope": "v8t" }, "system.v8t.3": { "value": "9600", "field": "Scale-up domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2026-09-28", "status": "announced", "scope": "v8t" }, "system.v8t.4": { "value": "n/d", "field": "Scale-out per accelerator", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2026-09-28", "status": "announced", "scope": "v8t" }, "system.v8t.5": { "value": "n/d", "field": "Rack power", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2026-09-28", "status": "announced", "scope": "v8t" }, "system.v8t.6": { "value": "Liquid", "field": "Cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2026-09-28", "status": "announced", "scope": "v8t" }, "system.v8i.0": { "value": "TPU8i", "field": "Platform", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2026-09-28", "status": "announced", "scope": "v8i" }, "system.v8i.1": { "value": "2026 announcement", "field": "Year / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2026-09-28", "status": "announced", "scope": "v8i" }, "system.v8i.2": { "value": "1152 physical / ≤1024 active", "field": "CPU / accelerator count", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2026-09-28", "status": "announced", "scope": "v8i" }, "system.v8i.3": { "value": "Boardfly", "field": "Scale-up domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2026-09-28", "status": "announced", "scope": "v8i" }, "system.v8i.4": { "value": "n/d", "field": "Scale-out per accelerator", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2026-09-28", "status": "announced", "scope": "v8i" }, "system.v8i.5": { "value": "n/d", "field": "Rack power", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2026-09-28", "status": "announced", "scope": "v8i" }, "system.v8i.6": { "value": "Liquid", "field": "Cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2026-09-28", "status": "announced", "scope": "v8i" }, "capacity_balance.v4.0": { "value": "TPUv4 HBM capacity/BF16", "field": "Metric", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2026-09-28", "status": "derived", "scope": "v4" }, "capacity_balance.v4.1": { "value": "32×2^30/(275×10^12) = 1.249×10^-4 B·s/FLOP", "field": "Value / calculation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2026-09-28", "status": "derived", "scope": "v4" }, "capacity_balance.v4.2": { "value": "Per chip; GiB converted to bytes", "field": "Basis", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2026-09-28", "status": "derived", "scope": "v4" }, "capacity_balance.v7.0": { "value": "Ironwood HBM capacity/BF16", "field": "Metric", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026-09-28", "status": "derived", "scope": "v7" }, "capacity_balance.v7.1": { "value": "192×2^30/(2307×10^12) = 8.936×10^-5 B·s/FLOP", "field": "Value / calculation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026-09-28", "status": "derived", "scope": "v7" }, "capacity_balance.v7.2": { "value": "Per package; dense BF16", "field": "Basis", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026-09-28", "status": "derived", "scope": "v7" }, "capacity_balance.host.0": { "value": "Axion DDR/core; L3/core", "field": "Metric", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-09-28", "status": "unknown", "scope": "host" }, "capacity_balance.host.1": { "value": "n/d", "field": "Value / calculation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-09-28", "status": "unknown", "scope": "host" }, "capacity_balance.host.2": { "value": "Physical CPU specifications incomplete", "field": "Basis", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P10" ], "disclosure_date": "2026-09-28", "status": "unknown", "scope": "host" }, "isscc.p.0": { "value": "ISSCC plenary", "field": "Venue", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C10" ], "disclosure_date": "2018", "status": "published", "scope": "p" }, "isscc.p.1": { "value": "2018", "field": "Year", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C10" ], "disclosure_date": "2018", "status": "published", "scope": "p" }, "isscc.p.2": { "value": "50 Years of Computer Architecture: From Mainframe CPUs to Neural-Network TPUs", "field": "Paper / talk / disclosure", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C10" ], "disclosure_date": "2018", "status": "published", "scope": "p" }, "isscc.p.3": { "value": "David Patterson", "field": "Presenter / authors", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C10" ], "disclosure_date": "2018", "status": "published", "scope": "p" }, "isscc.p.4": { "value": "TPU / domain specialization", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C10" ], "disclosure_date": "2018", "status": "published", "scope": "p" }, "isscc.p.5": { "value": "Official plenary record", "field": "Evidence type", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C10" ], "disclosure_date": "2018", "status": "published", "scope": "p" }, "isscc.p.6": { "value": "C10", "field": "Source", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C10" ], "disclosure_date": "2018", "status": "published", "scope": "p" }, "isscc.d.0": { "value": "ISSCC plenary", "field": "Venue", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C11", "C10" ], "disclosure_date": "2020", "status": "published", "scope": "d" }, "isscc.d.1": { "value": "2020", "field": "Year", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C11", "C10" ], "disclosure_date": "2020", "status": "published", "scope": "d" }, "isscc.d.2": { "value": "The Deep Learning Revolution and Its Implications for Computer Architecture and Chip Design", "field": "Paper / talk / disclosure", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C11", "C10" ], "disclosure_date": "2020", "status": "published", "scope": "d" }, "isscc.d.3": { "value": "Jeff Dean", "field": "Presenter / authors", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C11", "C10" ], "disclosure_date": "2020", "status": "published", "scope": "d" }, "isscc.d.4": { "value": "TPU / chip-design context", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C11", "C10" ], "disclosure_date": "2020", "status": "published", "scope": "d" }, "isscc.d.5": { "value": "Author companion paper and official record", "field": "Evidence type", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C11", "C10" ], "disclosure_date": "2020", "status": "published", "scope": "d" }, "isscc.d.6": { "value": "C11 C10", "field": "Source", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C11", "C10" ], "disclosure_date": "2020", "status": "published", "scope": "d" }, "isscc.g.0": { "value": "ISSCC Forum 3", "field": "Venue", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C12" ], "disclosure_date": "2026", "status": "program", "scope": "g" }, "isscc.g.1": { "value": "2026", "field": "Year", "basis": "Per reference product; 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