{
  "vendor": "Cerebras",
  "cutoff": "2026-09-28",
  "sections": [
    {
      "id": "01",
      "title": [
        "Scope and architectural synthesis",
        "范围与架构主线"
      ],
      "blocks": [
        {
          "id": "01.scope",
          "type": "prose",
          "text": [
            "This report covers Cerebras from its 2016 founding through 28 September 2026, within the series’ 2015–2026 window. It follows WSE1/2/3/3 Turbo, CS1/2/3/4, MemoryX, SwarmX, wafer I/O, software and the disclosed CS5/CS6 roadmap. It distinguishes wafer silicon from complete systems and deployment services. There is no separate Cerebras server-CPU or merchant DPU line in the documented portfolio.",
            "本报告在系列 2015—2026 年窗口内，覆盖 Cerebras 从 2016 年成立至 2026 年 9 月 28 日的发展，追踪 WSE1／2／3／3 Turbo、CS1／2／3／4、MemoryX、SwarmX、晶圆 I/O、软件及已披露 CS5／CS6 路线图。晶圆芯片、完整系统与部署服务分别处理。已记录产品组合中不存在独立 Cerebras 服务器 CPU 或商用 DPU 产品线。"
          ],
          "sources": [
            "C02",
            "E01",
            "E02",
            "C03"
          ]
        },
        {
          "id": "01.thesis",
          "type": "prose",
          "text": [
            "Cerebras changes the physical boundary of a computer: hundreds of thousands of small cores and their local SRAM communicate on a continuous wafer-scale mesh. This reduces many package crossings, but replaces commodity packaging with demanding yield repair, power delivery, cooling and mapping requirements. Its evolution moves from making wafer-scale computation practical to separating model storage from execution, and then to organizing multiple wafers for fast inference.",
            "Cerebras 改变计算机的物理边界：数十万个小核心及本地 SRAM 通过连续晶圆级网格通信。这减少许多封装跨越，但也用复杂的良率修复、供电、散热及映射要求替代常规封装。其演进从使晶圆级计算可行，转向分离模型存储与执行，再转向组织多晶圆实现快速推理。"
          ],
          "sources": [
            "E05",
            "E06",
            "C01",
            "E03",
            "E02"
          ]
        }
      ]
    },
    {
      "id": "02",
      "title": [
        "WSE1 and CS1: making wafer scale work",
        "WSE1 与 CS1：实现晶圆级计算"
      ],
      "blocks": [
        {
          "id": "02.w1",
          "type": "prose",
          "text": [
            "The 2019 Hot Chips disclosure introduced a 46,225 mm², 16 nm processor with 1.2 trillion transistors, 400,000 cores and 18 GB distributed SRAM. Local memory and a two-dimensional mesh replace the conventional pattern of repeatedly reaching off-chip for operands. The 9 PB/s SRAM figure is the sum of local memory interfaces; the 100 Pb/s fabric figure is an aggregate of mesh links. Neither is a global arbitrary-access bandwidth available to one core.",
            "2019 年 Hot Chips 披露了面积 46,225 mm²、16 nm、1.2 万亿晶体管、40 万核心及 18 GB 分布式 SRAM 的处理器。本地存储与二维网格替代反复到片外取操作数的传统模式。9 PB/s SRAM 带宽是本地存储接口之和；100 Pb/s 网络带宽是网格链路聚合值。两者都不是任意一个核心可享有的全局随机访问带宽。"
          ],
          "sources": [
            "E05"
          ]
        },
        {
          "id": "02.yield",
          "type": "prose",
          "text": [
            "Architectural interpretation: a wafer-scale device cannot require a defect-free wafer. Redundancy and routing repair are part of the architecture, alongside physical continuity across reticle boundaries. This makes yield a system-design problem rather than merely a transistor-density metric. CS1 adds the power and cooling machinery needed to expose the wafer as usable computing infrastructure.",
            "架构解读：晶圆级设备不能要求整片晶圆无缺陷。冗余和路由修复是架构的一部分，与跨光刻边界的物理连续连接共同工作。因此良率成为系统设计问题，而不只是晶体管密度指标。CS1 增加供电与散热装置，把晶圆转化为可用计算基础设施。"
          ],
          "sources": [
            "C01",
            "E05"
          ]
        }
      ]
    },
    {
      "id": "03",
      "title": [
        "WSE2 and CS2: local dataflow and Weight Streaming",
        "WSE2 与 CS2：本地数据流与权重流送"
      ],
      "blocks": [
        {
          "id": "03.w2",
          "type": "prose",
          "text": [
            "WSE2 moves to 7 nm with 850,000 cores and 40 GB SRAM. The 2022 Hot Chips architecture deep dive describes independently programmed cores with 48 KB local memory, a small software-managed accumulator cache, tensor address generation and data-triggered execution. The mesh extends across stitched reticle regions. Source-synchronous parallel links and repair state machines preserve the logical fabric despite manufacturing defects.",
            "WSE2 转向 7 nm，拥有 85 万核心及 40 GB SRAM。2022 年 Hot Chips 架构深析描述独立编程核心、48 KB 本地存储、小型软件管理累加缓存、张量地址生成及数据触发执行。网格跨越连接的光刻区域，源同步并行链路和修复状态机在制造缺陷存在时保持逻辑网络。"
          ],
          "sources": [
            "E06",
            "C01"
          ]
        },
        {
          "id": "03.sparse",
          "type": "prose",
          "text": [
            "Sparsity is supported through dataflow: zero elements can be filtered before sending, so receiving cores do not execute the corresponding work. This is distinct from advertising a fixed two-times structured-sparse peak. Benefits depend on actual sparsity, mapping and communication balance. The local memories also hold code and working data, so aggregate SRAM capacity cannot be assigned entirely to model weights.",
            "稀疏性通过数据流支持：零元素可以在发送前被过滤，接收核心因而不执行对应工作。这不同于公布固定两倍的结构化稀疏峰值。收益取决于实际稀疏度、映射及通信平衡。本地存储同时保存代码与工作数据，因此不能将聚合 SRAM 容量全部分配给模型权重。"
          ],
          "sources": [
            "C01",
            "E06"
          ]
        },
        {
          "id": "03.stream",
          "type": "prose",
          "text": [
            "Weight Streaming separates parameter storage from wafer execution. MemoryX stores and streams weights; SwarmX broadcasts weights and reduces gradients across CS systems. Each wafer executes the mapped work while external storage supports models larger than its SRAM. This is not an enlargement of on-wafer SRAM and does not create cache-coherent shared memory. The operator-facing simplification of distributed training still depends on a compiler and fabric that move the right data at the right time.",
            "权重流送将参数存储与晶圆执行分开。MemoryX 存储并流送权重，SwarmX 在多个 CS 系统间广播权重并归约梯度。各晶圆执行映射任务，外部存储支持超过 SRAM 容量的模型。这不是片上 SRAM 扩容，也不建立缓存一致性共享内存。面向用户的分布式训练简化，仍依赖编译器与网络在正确时间搬移正确数据。"
          ],
          "sources": [
            "E03",
            "P01",
            "C02"
          ]
        }
      ]
    },
    {
      "id": "04",
      "title": [
        "WSE3 and CS3: more compute, similar memory capacity",
        "WSE3 与 CS3：算力增加，存储容量增长较小"
      ],
      "blocks": [
        {
          "id": "04.w3",
          "type": "prose",
          "text": [
            "WSE3 uses 5 nm, four trillion transistors, 900,000 cores and 44 GB SRAM. The advertised 125 PFLOP/s AI compute rate needs a named numerical and sparsity basis before it can enter a dense BF16 comparison. Core count grows about 5.9% over WSE2, while SRAM capacity grows 10%. The generation’s performance improvement therefore cannot be explained simply as twice as many cores. ISA, datapath and implementation changes matter.",
            "WSE3 采用 5 nm、四万亿晶体管、90 万核心和 44 GB SRAM。公布的 125 PFLOP/s AI 算力，需要明确数值及稀疏口径后才能参与稠密 BF16 比较。相较 WSE2，核心数增长约 5.9%，SRAM 容量增长 10%。因此本代性能提升不能简单解释为核心数量翻倍，ISA、数据通路及实现变化同样重要。"
          ],
          "sources": [
            "E01",
            "C02",
            "P01"
          ]
        },
        {
          "id": "04.memory",
          "type": "prose",
          "text": [
            "The 2024 launch describes external memory configurations up to 1.2 PB and clusters up to 2,048 CS3 systems. Those are system/storage scale claims, not SRAM capacity per wafer. Hot Chips 2024 explains training through Weight Streaming and inference through model placement on the wafer fabric. For latency-sensitive decode, keeping weights in SRAM avoids repeated off-chip weight reads, but capacity determines how many wafers and pipeline stages a model needs.",
            "2024 年发布描述最高 1.2 PB 外部存储配置及最高 2,048 台 CS3 的集群。这是系统／存储规模，不是每晶圆 SRAM 容量。Hot Chips 2024 通过权重流送解释训练，并通过晶圆网络中的模型放置解释推理。对延迟敏感的解码，将权重保留在 SRAM 可以避免反复片外读取，但容量决定模型需要多少晶圆和流水级。"
          ],
          "sources": [
            "E01",
            "C02"
          ]
        }
      ]
    },
    {
      "id": "05",
      "title": [
        "CS4 and WSE3 Turbo: a system-generation change",
        "CS4 与 WSE3 Turbo：系统代际变化"
      ],
      "blocks": [
        {
          "id": "05.cs4",
          "type": "prose",
          "text": [
            "CS4, announced in August 2026, is a three-wafer rack-scale system using WSE3 Turbo, not a product called WSE4. Each wafer retains four trillion transistors, 900,000 cores and 44 GB SRAM. Higher operating rates accompany new power delivery, modular cooling and wafer I/O in the Nexus platform. The published system totals are 132 GB SRAM, 129.6 PB/s SRAM bandwidth and 7.2 Tb/s off-wafer I/O. First shipments were targeted for that quarter; the announcement alone does not establish completed general availability.",
            "2026 年 8 月公布的 CS4 是使用 WSE3 Turbo 的三晶圆机架级系统，并不是名为 WSE4 的产品。每晶圆仍有四万亿晶体管、90 万核心和 44 GB SRAM。更高工作速率配合 Nexus 平台的新供电、模块化散热及晶圆 I/O。公布系统总量为 132 GB SRAM、129.6 PB/s SRAM 带宽、7.2 Tb/s 片外 I/O。首批交付目标是当季，发布声明本身不证明已经完成正式商用。"
          ],
          "sources": [
            "E02",
            "P02",
            "C03"
          ]
        },
        {
          "id": "05.physical",
          "type": "prose",
          "text": [
            "The implementation emphasis shifts toward reducing the final power-delivery distance and making compute, power and I/O modules independently serviceable. Moving power conversion close to the wafer reduces resistive loss; it does not remove the need to dissipate the delivered power. The platform’s usefulness must be assessed with facility power, coolant requirements, maintenance isolation and failure recovery, not solely wafer arithmetic.",
            "实现重点转向缩短最终供电距离，并使计算、供电及 I/O 模块可独立维护。把电源转换移近晶圆可以减少电阻损耗，却不会消除对所输送功率的散热需求。平台价值必须结合设施供电、冷却液要求、维护隔离及故障恢复评估，不能只看晶圆算术能力。"
          ],
          "sources": [
            "C03",
            "E02"
          ]
        },
        {
          "id": "05.io",
          "type": "prose",
          "text": [
            "The programmable Wafer I/O Module supports RoCEv2 Ethernet and Direct Wafer Links. The latter connects wafers without an intervening switch, with a vendor-reported latency as low as two microseconds. Per-wafer off-wafer bandwidth is 2.4 Tb/s, or 300 GB/s as a nominal unit conversion; the announcement does not unambiguously specify directional aggregation. This external path remains radically smaller than the sum of local SRAM interfaces, making placement and pipelining essential.",
            "可编程 Wafer I/O Module 支持 RoCEv2 以太网和 Direct Wafer Links。后者无需中间交换机连接晶圆，厂商报告延迟最低两微秒。每晶圆片外带宽为 2.4 Tb/s，按单位换算为标称 300 GB/s；发布未明确方向聚合口径。该外部路径仍远小于本地 SRAM 接口总和，因此放置与流水化至关重要。"
          ],
          "sources": [
            "E02"
          ]
        }
      ]
    },
    {
      "id": "06",
      "title": [
        "Silicon and system specification tables",
        "芯片与系统规格表"
      ],
      "blocks": [
        {
          "id": "gpu",
          "type": "table",
          "table": "gpu"
        },
        {
          "id": "06.versions",
          "type": "prose",
          "text": [
            "The 2024 slides round WSE3 memory bandwidth to 21 PB/s; the 2026 system comparison uses 21.6 PB/s. This report uses the latter for normalized calculations. An older developer page states a 20% core-count increase, which conflicts with the explicitly published 850,000 and 900,000 counts; the counts are retained. Published fabric figures such as 214 or 220 Pb/s are aggregate link metrics and must not be treated as bisection bandwidth.",
            "2024 年幻灯片将 WSE3 内存带宽约写为 21 PB/s，2026 年系统比较采用 21.6 PB/s；本报告归一化计算采用后者。较早开发者页面写核心数增长 20%，与明确公布的 85 万和 90 万数量冲突，因此保留明确数量。214 或 220 Pb/s 等网络指标是链路聚合量，不能当作二分带宽。"
          ],
          "sources": [
            "C02",
            "E02",
            "P01",
            "E06"
          ]
        },
        {
          "id": "cpu",
          "type": "table",
          "table": "cpu"
        },
        {
          "id": "system",
          "type": "table",
          "table": "system"
        }
      ]
    },
    {
      "id": "07",
      "title": [
        "MemoryX, SwarmX and networking boundaries",
        "MemoryX、SwarmX 与网络边界"
      ],
      "blocks": [
        {
          "id": "nic",
          "type": "table",
          "table": "nic"
        },
        {
          "id": "links",
          "type": "table",
          "table": "links"
        },
        {
          "id": "07.hierarchy",
          "type": "prose",
          "text": [
            "Four bandwidth levels must remain distinct: a core’s SRAM port, the sum of SRAM ports across a wafer, the wafer mesh under a particular traffic pattern, and off-wafer I/O. Adding them or comparing their totals directly with GPU rack bisection obscures bottlenecks. A model that communicates mainly between neighbors can exploit the mesh differently from all-to-all expert routing or a global transpose.",
            "四个带宽层级必须区分：单核心 SRAM 端口、整晶圆 SRAM 端口之和、特定流量模式下的晶圆网格，以及片外 I/O。将其相加或直接拿总量比较 GPU 机架二分带宽，会掩盖瓶颈。以邻居通信为主的模型，利用网格的方式不同于全互联专家路由或全局转置。"
          ],
          "sources": [
            "C01",
            "C04",
            "E02"
          ]
        }
      ]
    },
    {
      "id": "08",
      "title": [
        "Programming, deployment and heterogeneous inference",
        "编程、部署与异构推理"
      ],
      "blocks": [
        {
          "id": "08.software",
          "type": "prose",
          "text": [
            "The software has two useful levels: framework/model compilation for AI users and low-level spatial/dataflow programming for kernels and scientific workloads. The compiler must allocate local storage, place work and route communication while respecting defects and resource limits. Weight Streaming hides much distributed-training complexity from the user, but does not make these physical constraints disappear. SC stencil research and wafer-scale FFT work demonstrate alternative mappings, not universal speedups for every scientific application.",
            "软件有两个重要层次：面向 AI 用户的框架／模型编译，以及面向算子和科学计算的低层空间／数据流编程。编译器必须分配本地存储、放置任务并安排通信，同时满足缺陷和资源约束。权重流送对用户隐藏许多分布式训练复杂性，但不会使这些物理限制消失。SC 模板计算研究与晶圆级 FFT 展示其他映射方式，不代表对所有科学应用的通用加速。"
          ],
          "sources": [
            "P01",
            "C01",
            "C04",
            "C07"
          ]
        },
        {
          "id": "08.aws",
          "type": "prose",
          "text": [
            "The March 2026 AWS collaboration describes CS3 deployment and a planned disaggregated inference path: Trainium performs prefill and transfers KV state over EFA to Cerebras for decode. This makes the phase boundary a system interface. The benefit depends on prompt length, output length, batching, transfer time and queueing. The announcement is not used as proof of public general availability for every named model.",
            "2026 年 3 月 AWS 合作描述 CS3 部署及计划中的分离式推理路径：Trainium 执行预填充，通过 EFA 向 Cerebras 传递 KV 状态，由后者执行解码。这把阶段边界变成系统接口。收益取决于输入长度、输出长度、批量、传输时间与排队。发布声明不作为所有具名模型已公共正式商用的证明。"
          ],
          "sources": [
            "E04"
          ]
        },
        {
          "id": "software",
          "type": "table",
          "table": "software"
        },
        {
          "id": "train",
          "type": "figure",
          "figure": "train"
        },
        {
          "id": "infer",
          "type": "figure",
          "figure": "infer"
        }
      ]
    },
    {
      "id": "09",
      "title": [
        "Derived balance and future architectural direction",
        "推导平衡与未来架构方向"
      ],
      "blocks": [
        {
          "id": "ratios",
          "type": "table",
          "table": "ratios"
        },
        {
          "id": "09.roadmap",
          "type": "prose",
          "text": [
            "At Hot Chips 2026, Cerebras described CS5 for 2027 using a next-generation WSE, and CS6 as a future combination of wafer-scale SRAM/compute with stacked DRAM. These are roadmap disclosures. The architectural importance of CS6 is a new memory tier: capacity could grow without proportionally multiplying wafers, but locality, stacking yield, thermal resistance and the SRAM/DRAM interface become central. No undisclosed capacity, process or measured speed is assigned to it.",
            "在 Hot Chips 2026，Cerebras 描述计划于 2027 年推出、使用下一代 WSE 的 CS5，以及未来结合晶圆级 SRAM／计算与堆叠 DRAM 的 CS6。这些均属路线图披露。CS6 的架构意义是引入新存储层：容量可能无需按比例增加晶圆数量就能增长，但局部性、堆叠良率、热阻及 SRAM／DRAM 接口成为核心。不为其填入未披露容量、工艺或实测速率。"
          ],
          "sources": [
            "C03"
          ]
        }
      ]
    },
    {
      "id": "10",
      "title": [
        "Conference index and naming crosswalk",
        "会议索引与命名对照"
      ],
      "blocks": [
        {
          "id": "conference",
          "type": "table",
          "table": "conference"
        },
        {
          "id": "10.limits",
          "type": "prose",
          "text": [
            "Hot Chips provides the main product architecture chain; ISPD and SC illuminate mapping and application behavior. This edition does not establish a direct product implementation paper at ISCA, MICRO, HPCA, ASPLOS or ISSCC. IEEE Micro journal articles derived from Hot Chips must not be mislabelled MICRO conference papers. Detailed comparison still needs matched numerical-format peaks, system power and workload-level throughput under a stated service latency.",
            "Hot Chips 提供主要产品架构链，ISPD 与 SC 解释映射及应用行为。本版未建立 ISCA、MICRO、HPCA、ASPLOS 或 ISSCC 的直接产品实现论文。由 Hot Chips 延伸的 IEEE Micro 期刊文章不能误标为 MICRO 会议论文。详细比较仍需要匹配数值格式的峰值、系统功耗，以及指定服务延迟下的负载吞吐。"
          ],
          "sources": [
            "C01",
            "C02",
            "C05",
            "C07"
          ]
        },
        {
          "id": "cross",
          "type": "table",
          "table": "cross"
        }
      ]
    }
  ],
  "tables": {
    "gpu": {
      "id": "gpu",
      "title": [
        "Wafer specifications, per wafer",
        "晶圆规格：每晶圆口径"
      ],
      "headers": [
        [
          "Product",
          "产品"
        ],
        [
          "Architecture",
          "架构"
        ],
        [
          "GA / milestone",
          "商用／里程碑"
        ],
        [
          "Status",
          "状态"
        ],
        [
          "Process",
          "工艺"
        ],
        [
          "Dies / packaging",
          "裸片／封装"
        ],
        [
          "Compute units",
          "计算单元"
        ],
        [
          "Dense BF16",
          "稠密 BF16"
        ],
        [
          "Dense FP8",
          "稠密 FP8"
        ],
        [
          "Dense FP6 / FP4",
          "稠密 FP6／FP4"
        ],
        [
          "FP64 vector / matrix",
          "FP64 向量／矩阵"
        ],
        [
          "Memory: type; stacks; GB; TB/s",
          "内存：类型；堆栈；GB；TB/s"
        ],
        [
          "LLC / SRAM",
          "末级缓存／SRAM"
        ],
        [
          "Scale-up: links; GB/s per direction; domain",
          "纵向扩展：链路；单向 GB/s；域"
        ],
        [
          "Host link",
          "主机连接"
        ],
        [
          "Power / cooling",
          "功耗／散热"
        ],
        [
          "Form factor",
          "形态"
        ]
      ],
      "rows": [
        {
          "id": "1",
          "values": [
            [
              "WSE1 / CS1",
              "WSE1 / CS1"
            ],
            [
              "Wafer-scale dataflow",
              "Wafer-scale dataflow"
            ],
            [
              "2019",
              "2019"
            ],
            [
              "Historical shipping",
              "历史已商用"
            ],
            [
              "16 nm",
              "16 nm"
            ],
            [
              "1 wafer / system",
              "1 wafer / system"
            ],
            [
              "400000 cores",
              "400000 cores"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "No attached HBM; external MemoryX separate",
              "无附加 HBM；外部 MemoryX 单列"
            ],
            [
              "18 GB SRAM; 9 PB/s aggregate",
              "18 GB SRAM; 9 PB/s aggregate"
            ],
            [
              "2D mesh; per-link n/d; one wafer",
              "2D mesh; per-link n/d; one wafer"
            ],
            [
              "System I/O; not host PCIe card",
              "System I/O; not host PCIe card"
            ],
            [
              "n/d; liquid",
              "n/d; liquid"
            ],
            [
              "Wafer-scale system",
              "晶圆级系统"
            ]
          ],
          "sources": [
            "E05"
          ]
        },
        {
          "id": "2",
          "values": [
            [
              "WSE2 / CS2",
              "WSE2 / CS2"
            ],
            [
              "Wafer-scale dataflow",
              "Wafer-scale dataflow"
            ],
            [
              "2021",
              "2021"
            ],
            [
              "Historical shipping",
              "历史已商用"
            ],
            [
              "7 nm",
              "7 nm"
            ],
            [
              "1 wafer / system",
              "1 wafer / system"
            ],
            [
              "850000 cores",
              "850000 cores"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "No attached HBM; external MemoryX separate",
              "无附加 HBM；外部 MemoryX 单列"
            ],
            [
              "40 GB SRAM; 20 PB/s aggregate",
              "40 GB SRAM; 20 PB/s aggregate"
            ],
            [
              "2D mesh; per-link n/d; one wafer",
              "2D mesh; per-link n/d; one wafer"
            ],
            [
              "System I/O; not host PCIe card",
              "System I/O; not host PCIe card"
            ],
            [
              "n/d; liquid",
              "n/d; liquid"
            ],
            [
              "Wafer-scale system",
              "晶圆级系统"
            ]
          ],
          "sources": [
            "E06",
            "E03"
          ]
        },
        {
          "id": "3",
          "values": [
            [
              "WSE3 / CS3",
              "WSE3 / CS3"
            ],
            [
              "Wafer-scale dataflow",
              "Wafer-scale dataflow"
            ],
            [
              "2024",
              "2024"
            ],
            [
              "Shipping / available",
              "已商用／可获取"
            ],
            [
              "5 nm",
              "5 nm"
            ],
            [
              "1 wafer / system",
              "1 wafer / system"
            ],
            [
              "900000 cores",
              "900000 cores"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "No attached HBM; external MemoryX separate",
              "无附加 HBM；外部 MemoryX 单列"
            ],
            [
              "44 GB SRAM; 21.6 PB/s aggregate",
              "44 GB SRAM; 21.6 PB/s aggregate"
            ],
            [
              "2D mesh; per-link n/d; one wafer",
              "2D mesh; per-link n/d; one wafer"
            ],
            [
              "System I/O; not host PCIe card",
              "System I/O; not host PCIe card"
            ],
            [
              "n/d; liquid",
              "n/d; liquid"
            ],
            [
              "Wafer-scale system",
              "晶圆级系统"
            ]
          ],
          "sources": [
            "E01",
            "C02",
            "E02"
          ]
        },
        {
          "id": "3t",
          "values": [
            [
              "WSE3 Turbo / CS4",
              "WSE3 Turbo / CS4"
            ],
            [
              "Wafer-scale dataflow",
              "Wafer-scale dataflow"
            ],
            [
              "2026 announcement",
              "2026 announcement"
            ],
            [
              "Announced; GA n/d",
              "已公布；GA n/d"
            ],
            [
              "5 nm",
              "5 nm"
            ],
            [
              "3 wafers / CS4; numbers per wafer",
              "3 wafers / CS4; numbers per wafer"
            ],
            [
              "900000 cores",
              "900000 cores"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "No attached HBM; external MemoryX separate",
              "无附加 HBM；外部 MemoryX 单列"
            ],
            [
              "44 GB SRAM; 43.2 PB/s aggregate",
              "44 GB SRAM; 43.2 PB/s aggregate"
            ],
            [
              "2D mesh; per-link n/d; one wafer",
              "2D mesh; per-link n/d; one wafer"
            ],
            [
              "System I/O; not host PCIe card",
              "System I/O; not host PCIe card"
            ],
            [
              "n/d; liquid",
              "n/d; liquid"
            ],
            [
              "Wafer-scale system",
              "晶圆级系统"
            ]
          ],
          "sources": [
            "E02"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3,
          4,
          5
        ],
        [
          0,
          6,
          7,
          8,
          9,
          10
        ],
        [
          0,
          11,
          12
        ],
        [
          0,
          13,
          14,
          15,
          16
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "cpu": {
      "id": "cpu",
      "title": [
        "Host CPU boundary",
        "主机 CPU 边界"
      ],
      "headers": [
        [
          "Generation / reference SKU",
          "代际／参考 SKU"
        ],
        [
          "Codename",
          "代号"
        ],
        [
          "GA",
          "正式商用"
        ],
        [
          "Status",
          "状态"
        ],
        [
          "Core µarch",
          "核心微架构"
        ],
        [
          "Cores / threads",
          "核心／线程"
        ],
        [
          "Process per die",
          "各裸片工艺"
        ],
        [
          "Dies / packaging",
          "裸片／封装"
        ],
        [
          "L2 per core",
          "每核 L2"
        ],
        [
          "L3 / domain",
          "L3／共享域"
        ],
        [
          "Memory: channels; rate; GB/s",
          "内存：通道；速率；GB/s"
        ],
        [
          "Sockets / links",
          "插槽／互联"
        ],
        [
          "PCIe / CXL",
          "PCIe／CXL"
        ],
        [
          "TDP",
          "TDP"
        ],
        [
          "Vector / matrix ISA",
          "向量／矩阵 ISA"
        ]
      ],
      "rows": [
        {
          "id": "none",
          "values": [
            [
              "External preprocessing / management CPUs",
              "外部预处理／管理 CPU"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "Supplier products",
              "供应商产品"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ]
          ],
          "sources": [
            "P01"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3,
          4,
          5
        ],
        [
          0,
          6,
          7,
          8,
          9
        ],
        [
          0,
          10,
          11,
          12,
          13,
          14
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "system": {
      "id": "system",
      "title": [
        "System generations",
        "系统代际"
      ],
      "headers": [
        [
          "Platform",
          "平台"
        ],
        [
          "Year / milestone",
          "年份／里程碑"
        ],
        [
          "CPU / accelerator count",
          "CPU／加速器数量"
        ],
        [
          "Scale-up domain",
          "纵向扩展域"
        ],
        [
          "Scale-out per accelerator",
          "每加速器横向带宽"
        ],
        [
          "Rack power",
          "机架功耗"
        ],
        [
          "Cooling",
          "散热"
        ]
      ],
      "rows": [
        {
          "id": "a",
          "values": [
            [
              "CS1",
              "CS1"
            ],
            [
              "2019",
              "2019"
            ],
            [
              "1 WSE1",
              "1 WSE1"
            ],
            [
              "1 wafer; cluster topology n/d",
              "1 wafer; cluster topology n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Liquid",
              "Liquid"
            ]
          ],
          "sources": [
            "E05"
          ]
        },
        {
          "id": "b",
          "values": [
            [
              "CS2 + MemoryX/SwarmX",
              "CS2 + MemoryX/SwarmX"
            ],
            [
              "2021",
              "2021"
            ],
            [
              "1 WSE2 per CS2",
              "1 WSE2 per CS2"
            ],
            [
              "Weight Streaming cluster",
              "Weight Streaming cluster"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Liquid",
              "Liquid"
            ]
          ],
          "sources": [
            "E03"
          ]
        },
        {
          "id": "c",
          "values": [
            [
              "CS3",
              "CS3"
            ],
            [
              "2024",
              "2024"
            ],
            [
              "1 WSE3; up to 2048 systems",
              "1 WSE3; up to 2048 systems"
            ],
            [
              "SwarmX / workload placement",
              "SwarmX / workload placement"
            ],
            [
              "1.2 Tb/s system I/O; direction n/d",
              "1.2 Tb/s system I/O; direction n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Liquid",
              "Liquid"
            ]
          ],
          "sources": [
            "E01",
            "E02"
          ]
        },
        {
          "id": "d",
          "values": [
            [
              "CS4 / Nexus",
              "CS4 / Nexus"
            ],
            [
              "2026 announcement",
              "2026 announcement"
            ],
            [
              "3 WSE3T",
              "3 WSE3T"
            ],
            [
              "Direct Wafer Links / Ethernet",
              "Direct Wafer Links / Ethernet"
            ],
            [
              "2.4 Tb/s per wafer; direction n/d",
              "2.4 Tb/s per wafer; direction n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Modular liquid cooling",
              "Modular liquid cooling"
            ]
          ],
          "sources": [
            "E02"
          ]
        },
        {
          "id": "e",
          "values": [
            [
              "CS5 / CS6",
              "CS5 / CS6"
            ],
            [
              "2027 target / later",
              "2027 target / later"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ]
          ],
          "sources": [
            "C03"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3
        ],
        [
          0,
          4,
          5,
          6
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "nic": {
      "id": "nic",
      "title": [
        "Communication products and functions",
        "通信产品与功能"
      ],
      "headers": [
        [
          "Product",
          "产品"
        ],
        [
          "GA / milestone",
          "商用／里程碑"
        ],
        [
          "Status",
          "状态"
        ],
        [
          "Class",
          "类别"
        ],
        [
          "Ports × speed",
          "端口×速率"
        ],
        [
          "SerDes",
          "SerDes"
        ],
        [
          "Host interface",
          "主机接口"
        ],
        [
          "Programmable engine",
          "可编程引擎"
        ],
        [
          "Embedded CPU",
          "嵌入式 CPU"
        ],
        [
          "On-card memory",
          "板载内存"
        ],
        [
          "Transport / RDMA",
          "传输／RDMA"
        ],
        [
          "Congestion control",
          "拥塞控制"
        ],
        [
          "Key offloads",
          "主要卸载"
        ],
        [
          "Power",
          "功耗"
        ]
      ],
      "rows": [
        {
          "id": "a",
          "values": [
            [
              "SwarmX",
              "SwarmX"
            ],
            [
              "2021",
              "2021"
            ],
            [
              "Shipping / available",
              "已商用／可获取"
            ],
            [
              "Broadcast/reduce fabric",
              "Broadcast/reduce fabric"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "System Ethernet",
              "System Ethernet"
            ],
            [
              "Collective acceleration",
              "Collective acceleration"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Weight/gradient streaming",
              "Weight/gradient streaming"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Broadcast / reduction",
              "Broadcast / reduction"
            ],
            [
              "n/d",
              "n/d"
            ]
          ],
          "sources": [
            "E03",
            "P01"
          ]
        },
        {
          "id": "b",
          "values": [
            [
              "Wafer I/O Module",
              "Wafer I/O Module"
            ],
            [
              "2026",
              "2026"
            ],
            [
              "Announced; GA n/d",
              "已公布；GA n/d"
            ],
            [
              "Programmable wafer I/O",
              "Programmable wafer I/O"
            ],
            [
              "2.4 Tb/s/wafer aggregate; direction n/d",
              "2.4 Tb/s/wafer aggregate; direction n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Wafer system interface",
              "Wafer system interface"
            ],
            [
              "Programmable I/O",
              "Programmable I/O"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "RoCEv2 / Direct Wafer Links",
              "RoCEv2 / Direct Wafer Links"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Wafer-to-wafer data movement",
              "Wafer-to-wafer data movement"
            ],
            [
              "n/d",
              "n/d"
            ]
          ],
          "sources": [
            "E02"
          ]
        },
        {
          "id": "c",
          "values": [
            [
              "Merchant DPU / host NIC",
              "商用 DPU／主机网卡"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "n/a",
              "n/a"
            ]
          ],
          "sources": [
            "P01"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3
        ],
        [
          0,
          4,
          5,
          6,
          7
        ],
        [
          0,
          8,
          9,
          10,
          11
        ],
        [
          0,
          12,
          13
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "links": {
      "id": "links",
      "title": [
        "Interconnect hierarchy",
        "互联层次"
      ],
      "headers": [
        [
          "Interconnect",
          "互联"
        ],
        [
          "Year / generation",
          "年份／代际"
        ],
        [
          "Lane rate",
          "通道速率"
        ],
        [
          "Lanes / link",
          "每链路通道"
        ],
        [
          "GB/s per link per direction",
          "每链路单向 GB/s"
        ],
        [
          "Links / device",
          "每设备链路"
        ],
        [
          "Topology",
          "拓扑"
        ],
        [
          "Domain limit",
          "域规模"
        ],
        [
          "Coherence / semantics",
          "一致性／语义"
        ]
      ],
      "rows": [
        {
          "id": "a",
          "values": [
            [
              "On-wafer mesh",
              "On-wafer mesh"
            ],
            [
              "WSE1-3T",
              "WSE1-3T"
            ],
            [
              "Generation-specific",
              "Generation-specific"
            ],
            [
              "32-bit interfaces in HC2022",
              "32-bit interfaces in HC2022"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "4 neighbors/core",
              "4 neighbors/core"
            ],
            [
              "2D mesh",
              "2D mesh"
            ],
            [
              "Wafer",
              "Wafer"
            ],
            [
              "Explicit local-memory messages",
              "Explicit local-memory messages"
            ]
          ],
          "sources": [
            "C01"
          ]
        },
        {
          "id": "b",
          "values": [
            [
              "SwarmX",
              "SwarmX"
            ],
            [
              "2021 onward",
              "2021 onward"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Broadcast / reduction tree",
              "Broadcast / reduction tree"
            ],
            [
              "System configuration",
              "System configuration"
            ],
            [
              "Weight streaming; not coherent",
              "Weight streaming; not coherent"
            ]
          ],
          "sources": [
            "E03",
            "P01"
          ]
        },
        {
          "id": "c",
          "values": [
            [
              "Direct Wafer Links",
              "Direct Wafer Links"
            ],
            [
              "2026",
              "2026"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Switchless wafer links",
              "Switchless wafer links"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Explicit communication",
              "Explicit communication"
            ]
          ],
          "sources": [
            "E02"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3,
          4
        ],
        [
          0,
          5,
          6,
          7,
          8
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "software": {
      "id": "software",
      "title": [
        "Software and control layers",
        "软件与控制层"
      ],
      "headers": [
        [
          "Layer",
          "层"
        ],
        [
          "Component",
          "组件"
        ],
        [
          "Function",
          "功能"
        ],
        [
          "Constraint",
          "约束"
        ]
      ],
      "rows": [
        {
          "id": "a",
          "values": [
            [
              "Model",
              "模型"
            ],
            [
              "Framework / model compiler",
              "Framework / model compiler"
            ],
            [
              "Compile training and inference",
              "编译训练与推理"
            ],
            [
              "Operator and numerical support",
              "算子与数值支持"
            ]
          ],
          "sources": [
            "P01",
            "E01"
          ]
        },
        {
          "id": "b",
          "values": [
            [
              "Kernel",
              "内核"
            ],
            [
              "CSL / dataflow mapping",
              "CSL / dataflow mapping"
            ],
            [
              "Spatial compute and communication",
              "空间计算与通信"
            ],
            [
              "Local memory and mesh routing",
              "本地存储与网格路由"
            ]
          ],
          "sources": [
            "C04",
            "C07"
          ]
        },
        {
          "id": "c",
          "values": [
            [
              "Training",
              "训练"
            ],
            [
              "MemoryX / SwarmX control",
              "MemoryX / SwarmX control"
            ],
            [
              "Weights and gradient reduction",
              "权重与梯度归约"
            ],
            [
              "Streaming schedule and bandwidth",
              "流送调度与带宽"
            ]
          ],
          "sources": [
            "P01",
            "E03"
          ]
        },
        {
          "id": "d",
          "values": [
            [
              "Operations",
              "运维"
            ],
            [
              "Management / preprocessing servers",
              "Management / preprocessing servers"
            ],
            [
              "Input and resource scheduling",
              "输入与资源调度"
            ],
            [
              "External hosts and services",
              "外部主机及服务"
            ]
          ],
          "sources": [
            "P01"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2,
          3
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "ratios": {
      "id": "ratios",
      "title": [
        "Normalized metrics",
        "归一化指标"
      ],
      "headers": [
        [
          "Metric",
          "指标"
        ],
        [
          "Calculation",
          "计算"
        ],
        [
          "Meaning",
          "含义"
        ]
      ],
      "rows": [
        {
          "id": "a",
          "values": [
            [
              "WSE2→WSE3 core growth",
              "WSE2→WSE3 core growth"
            ],
            [
              "900000/850000 = 1.059",
              "900000/850000 = 1.059"
            ],
            [
              "5.9%, not 20%",
              "5.9%，非 20%"
            ]
          ],
          "sources": [
            "E06",
            "E01"
          ]
        },
        {
          "id": "b",
          "values": [
            [
              "WSE3→CS4 SRAM",
              "WSE3→CS4 SRAM"
            ],
            [
              "3×44 = 132 GB",
              "3×44 = 132 GB"
            ],
            [
              "System aggregation; not one wafer",
              "系统聚合；非单晶圆"
            ]
          ],
          "sources": [
            "E02"
          ]
        },
        {
          "id": "c",
          "values": [
            [
              "WSE3T SRAM/external I/O",
              "WSE3T SRAM/external I/O"
            ],
            [
              "43.2 PB/s / 0.0003 PB/s = 144000",
              "43.2 PB/s / 0.0003 PB/s = 144000"
            ],
            [
              "Scale contrast; direction and topology differ",
              "规模对照；方向与拓扑不同"
            ]
          ],
          "sources": [
            "E02"
          ]
        },
        {
          "id": "d",
          "values": [
            [
              "CS4 I/O unit conversion",
              "CS4 I/O unit conversion"
            ],
            [
              "7.2 Tb/s /8 = 900 GB/s",
              "7.2 Tb/s /8 = 900 GB/s"
            ],
            [
              "Nominal aggregate; direction n/d",
              "标称聚合；方向 n/d"
            ]
          ],
          "sources": [
            "E02"
          ]
        },
        {
          "id": "e",
          "values": [
            [
              "44 GB / BF16 weight",
              "44 GB / BF16 weight"
            ],
            [
              "44e9/2 = 22 billion parameters",
              "44e9/2 = 22 billion parameters"
            ],
            [
              "Capacity upper bound before code/KV/workspace",
              "扣除代码／KV／工作区前容量上限"
            ]
          ],
          "sources": [
            "E01"
          ]
        },
        {
          "id": "f",
          "values": [
            [
              "Dense HBM/FLOP",
              "Dense HBM/FLOP"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "SRAM architecture; no HBM tier",
              "SRAM 架构；无 HBM 层"
            ]
          ],
          "sources": [
            "C02"
          ]
        },
        {
          "id": "g",
          "values": [
            [
              "SRAM/FLOP; capacity/FLOP; FLOP/W",
              "SRAM/FLOP; capacity/FLOP; FLOP/W"
            ],
            [
              "n/d",
              "n/d"
            ],
            [
              "Matched dense format and power basis absent",
              "缺匹配稠密格式及功耗口径"
            ]
          ],
          "sources": [
            "E01",
            "E02"
          ]
        },
        {
          "id": "h",
          "values": [
            [
              "Host DDR/core; L3/core",
              "Host DDR/core; L3/core"
            ],
            [
              "n/a",
              "n/a"
            ],
            [
              "No proprietary host CPU",
              "无自研主机 CPU"
            ]
          ],
          "sources": [
            "P01"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "conference": {
      "id": "conference",
      "title": [
        "Disclosure map",
        "披露映射"
      ],
      "headers": [
        [
          "Venue",
          "会议／活动"
        ],
        [
          "Year",
          "年份"
        ],
        [
          "Paper / talk / disclosure",
          "论文／演讲／披露"
        ],
        [
          "Presenter / authors",
          "报告人／作者"
        ],
        [
          "Product",
          "产品"
        ],
        [
          "Evidence type",
          "证据类型"
        ],
        [
          "Source",
          "来源"
        ]
      ],
      "rows": [
        {
          "id": "a",
          "values": [
            [
              "Hot Chips",
              "Hot Chips"
            ],
            [
              "2019",
              "2019"
            ],
            [
              "Wafer Scale Engine",
              "Wafer Scale Engine"
            ],
            [
              "Cerebras / research authors",
              "Cerebras／研究作者"
            ],
            [
              "WSE1",
              "WSE1"
            ],
            [
              "Architecture / implementation / workload",
              "架构／实现／负载"
            ],
            [
              "E05",
              "E05"
            ]
          ],
          "sources": [
            "E05"
          ]
        },
        {
          "id": "b",
          "values": [
            [
              "Hot Chips",
              "Hot Chips"
            ],
            [
              "2021",
              "2021"
            ],
            [
              "Extreme-scale AI / Weight Streaming",
              "Extreme-scale AI / Weight Streaming"
            ],
            [
              "Cerebras / research authors",
              "Cerebras／研究作者"
            ],
            [
              "WSE2 / CS2",
              "WSE2 / CS2"
            ],
            [
              "Architecture / implementation / workload",
              "架构／实现／负载"
            ],
            [
              "E06 E03",
              "E06 E03"
            ]
          ],
          "sources": [
            "E06",
            "E03"
          ]
        },
        {
          "id": "c",
          "values": [
            [
              "Hot Chips",
              "Hot Chips"
            ],
            [
              "2022",
              "2022"
            ],
            [
              "Architecture deep dive",
              "Architecture deep dive"
            ],
            [
              "Cerebras / research authors",
              "Cerebras／研究作者"
            ],
            [
              "Core / SRAM / mesh",
              "Core / SRAM / mesh"
            ],
            [
              "Architecture / implementation / workload",
              "架构／实现／负载"
            ],
            [
              "C01",
              "C01"
            ]
          ],
          "sources": [
            "C01"
          ]
        },
        {
          "id": "d",
          "values": [
            [
              "Hot Chips",
              "Hot Chips"
            ],
            [
              "2023",
              "2023"
            ],
            [
              "Inside the Wafer-Scale Cluster",
              "Inside the Wafer-Scale Cluster"
            ],
            [
              "Cerebras / research authors",
              "Cerebras／研究作者"
            ],
            [
              "MemoryX / SwarmX",
              "MemoryX / SwarmX"
            ],
            [
              "Architecture / implementation / workload",
              "架构／实现／负载"
            ],
            [
              "C06",
              "C06"
            ]
          ],
          "sources": [
            "C06"
          ]
        },
        {
          "id": "e",
          "values": [
            [
              "Hot Chips",
              "Hot Chips"
            ],
            [
              "2024",
              "2024"
            ],
            [
              "Wafer-Scale AI",
              "Wafer-Scale AI"
            ],
            [
              "Cerebras / research authors",
              "Cerebras／研究作者"
            ],
            [
              "WSE3 / CS3",
              "WSE3 / CS3"
            ],
            [
              "Architecture / implementation / workload",
              "架构／实现／负载"
            ],
            [
              "C02",
              "C02"
            ]
          ],
          "sources": [
            "C02"
          ]
        },
        {
          "id": "f",
          "values": [
            [
              "Hot Chips",
              "Hot Chips"
            ],
            [
              "2026",
              "2026"
            ],
            [
              "Ultrafast frontier inference",
              "Ultrafast frontier inference"
            ],
            [
              "Cerebras / research authors",
              "Cerebras／研究作者"
            ],
            [
              "CS4; CS5/6 roadmap",
              "CS4; CS5/6 roadmap"
            ],
            [
              "Architecture / implementation / workload",
              "架构／实现／负载"
            ],
            [
              "C03",
              "C03"
            ]
          ],
          "sources": [
            "C03"
          ]
        },
        {
          "id": "g",
          "values": [
            [
              "ISPD",
              "ISPD"
            ],
            [
              "2020",
              "2020"
            ],
            [
              "Wafer-scale placement contest",
              "Wafer-scale placement contest"
            ],
            [
              "Cerebras / research authors",
              "Cerebras／研究作者"
            ],
            [
              "Physical mapping",
              "Physical mapping"
            ],
            [
              "Architecture / implementation / workload",
              "架构／实现／负载"
            ],
            [
              "C05",
              "C05"
            ]
          ],
          "sources": [
            "C05"
          ]
        },
        {
          "id": "h",
          "values": [
            [
              "SC",
              "SC"
            ],
            [
              "2020",
              "2020"
            ],
            [
              "Fast Stencil-Code Computation",
              "Fast Stencil-Code Computation"
            ],
            [
              "Cerebras / research authors",
              "Cerebras／研究作者"
            ],
            [
              "CS1 research workload",
              "CS1 research workload"
            ],
            [
              "Architecture / implementation / workload",
              "架构／实现／负载"
            ],
            [
              "C07",
              "C07"
            ]
          ],
          "sources": [
            "C07"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2
        ],
        [
          0,
          3,
          4,
          5,
          6
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    },
    "cross": {
      "id": "cross",
      "title": [
        "Names and counting levels",
        "名称与计数层级"
      ],
      "headers": [
        [
          "Name",
          "名称"
        ],
        [
          "Meaning",
          "含义"
        ],
        [
          "Boundary",
          "边界"
        ]
      ],
      "rows": [
        {
          "id": "a",
          "values": [
            [
              "WSE",
              "WSE"
            ],
            [
              "Wafer processor",
              "晶圆处理器"
            ],
            [
              "Silicon generation",
              "芯片代际"
            ]
          ],
          "sources": [
            "E01"
          ]
        },
        {
          "id": "b",
          "values": [
            [
              "CS",
              "CS"
            ],
            [
              "Complete compute system",
              "完整计算系统"
            ],
            [
              "CS4 uses three WSE3T",
              "CS4 使用三片 WSE3T"
            ]
          ],
          "sources": [
            "E02"
          ]
        },
        {
          "id": "c",
          "values": [
            [
              "MemoryX",
              "MemoryX"
            ],
            [
              "External model storage/streaming",
              "外部模型存储／流送"
            ],
            [
              "Not on-wafer SRAM",
              "不是片上 SRAM"
            ]
          ],
          "sources": [
            "P01"
          ]
        },
        {
          "id": "d",
          "values": [
            [
              "Swarm / SwarmX",
              "Swarm / SwarmX"
            ],
            [
              "On-wafer fabric / cluster fabric",
              "片上网络／集群网络"
            ],
            [
              "Different physical boundaries",
              "不同物理边界"
            ]
          ],
          "sources": [
            "E05",
            "E03"
          ]
        },
        {
          "id": "e",
          "values": [
            [
              "Nexus",
              "Nexus"
            ],
            [
              "Rack platform",
              "机架平台"
            ],
            [
              "Power, cooling, I/O modularity",
              "供电、散热、I/O 模块化"
            ]
          ],
          "sources": [
            "E02"
          ]
        }
      ],
      "panels": [
        [
          0,
          1,
          2
        ]
      ],
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled"
    }
  },
  "figures": {
    "train": {
      "id": "train",
      "title": [
        "2021-2024 training stack",
        "2021—2024 年训练栈"
      ],
      "nodes": [
        [
          "cpu",
          [
            "Input / management servers",
            "输入／管理服务器"
          ],
          0,
          0
        ],
        [
          "gpu",
          [
            "CS2 / CS3 wafer",
            "CS2 / CS3 wafer"
          ],
          0,
          1
        ],
        [
          "mem",
          [
            "Local SRAM / mesh",
            "本地 SRAM／网格"
          ],
          0,
          2
        ],
        [
          "mx",
          [
            "MemoryX weights",
            "MemoryX 权重"
          ],
          1,
          0
        ],
        [
          "net",
          [
            "SwarmX",
            "SwarmX"
          ],
          1,
          1
        ],
        [
          "sw",
          [
            "Compiler / runtime",
            "编译器／运行时"
          ],
          1,
          2
        ]
      ],
      "edges": [
        [
          "cpu",
          "gpu",
          [
            "input",
            "输入"
          ]
        ],
        [
          "mx",
          "net",
          [
            "weights",
            "权重"
          ]
        ],
        [
          "net",
          "gpu",
          [
            "broadcast / reduce",
            "广播／归约"
          ]
        ],
        [
          "gpu",
          "mem",
          [
            "local work",
            "本地执行"
          ]
        ]
      ],
      "caption": [
        "MemoryX capacity is external to the wafer SRAM.",
        "MemoryX 容量位于晶圆 SRAM 之外。"
      ]
    },
    "infer": {
      "id": "infer",
      "title": [
        "2026 inference integration",
        "2026 年推理集成"
      ],
      "nodes": [
        [
          "cpu",
          [
            "Prefill engine / host",
            "预填充引擎／主机"
          ],
          0,
          0
        ],
        [
          "gpu",
          [
            "WSE3 / WSE3 Turbo",
            "WSE3 / WSE3 Turbo"
          ],
          0,
          1
        ],
        [
          "mem",
          [
            "SRAM-resident weights",
            "SRAM 常驻权重"
          ],
          0,
          2
        ],
        [
          "io",
          [
            "EFA / RoCEv2 / wafer I/O",
            "EFA / RoCEv2 / wafer I/O"
          ],
          1,
          0
        ],
        [
          "net",
          [
            "Other wafers / Direct Links",
            "其他晶圆／直连链路"
          ],
          1,
          1
        ],
        [
          "rack",
          [
            "Nexus power / cooling",
            "Nexus 供电／散热"
          ],
          1,
          2
        ]
      ],
      "edges": [
        [
          "cpu",
          "gpu",
          [
            "KV handoff",
            "KV 交接"
          ]
        ],
        [
          "gpu",
          "mem",
          [
            "decode",
            "解码"
          ]
        ],
        [
          "gpu",
          "net",
          [
            "pipeline",
            "流水线"
          ]
        ],
        [
          "net",
          "rack",
          [
            "system integration",
            "系统集成"
          ]
        ]
      ],
      "caption": [
        "Functional options from separate announcements; not a single confirmed shipping configuration.",
        "来自不同披露的功能选项，不代表单一已确认交付配置。"
      ]
    }
  },
  "claims": {
    "gpu.1.0": {
      "value": "WSE1 / CS1",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "1"
    },
    "gpu.1.1": {
      "value": "Wafer-scale dataflow",
      "field": "Architecture",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "1"
    },
    "gpu.1.2": {
      "value": "2019",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "1"
    },
    "gpu.1.3": {
      "value": "Historical shipping",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "1"
    },
    "gpu.1.4": {
      "value": "16 nm",
      "field": "Process",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "1"
    },
    "gpu.1.5": {
      "value": "1 wafer / system",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "1"
    },
    "gpu.1.6": {
      "value": "400000 cores",
      "field": "Compute units",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "1"
    },
    "gpu.1.7": {
      "value": "n/d",
      "field": "Dense BF16",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "1"
    },
    "gpu.1.8": {
      "value": "n/d",
      "field": "Dense FP8",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "1"
    },
    "gpu.1.9": {
      "value": "n/d",
      "field": "Dense FP6 / FP4",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "1"
    },
    "gpu.1.10": {
      "value": "n/d",
      "field": "FP64 vector / matrix",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "1"
    },
    "gpu.1.11": {
      "value": "No attached HBM; external MemoryX separate",
      "field": "Memory: type; stacks; GB; TB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "1"
    },
    "gpu.1.12": {
      "value": "18 GB SRAM; 9 PB/s aggregate",
      "field": "LLC / SRAM",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "1"
    },
    "gpu.1.13": {
      "value": "2D mesh; per-link n/d; one wafer",
      "field": "Scale-up: links; GB/s per direction; domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "1"
    },
    "gpu.1.14": {
      "value": "System I/O; not host PCIe card",
      "field": "Host link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "1"
    },
    "gpu.1.15": {
      "value": "n/d; liquid",
      "field": "Power / cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "1"
    },
    "gpu.1.16": {
      "value": "Wafer-scale system",
      "field": "Form factor",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "1"
    },
    "gpu.2.0": {
      "value": "WSE2 / CS2",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E06",
        "E03"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "2"
    },
    "gpu.2.1": {
      "value": "Wafer-scale dataflow",
      "field": "Architecture",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E06",
        "E03"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "2"
    },
    "gpu.2.2": {
      "value": "2021",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E06",
        "E03"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "2"
    },
    "gpu.2.3": {
      "value": "Historical shipping",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E06",
        "E03"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "2"
    },
    "gpu.2.4": {
      "value": "7 nm",
      "field": "Process",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E06",
        "E03"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "2"
    },
    "gpu.2.5": {
      "value": "1 wafer / system",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E06",
        "E03"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "2"
    },
    "gpu.2.6": {
      "value": "850000 cores",
      "field": "Compute units",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E06",
        "E03"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "2"
    },
    "gpu.2.7": {
      "value": "n/d",
      "field": "Dense BF16",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E06",
        "E03"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "2"
    },
    "gpu.2.8": {
      "value": "n/d",
      "field": "Dense FP8",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E06",
        "E03"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "2"
    },
    "gpu.2.9": {
      "value": "n/d",
      "field": "Dense FP6 / FP4",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E06",
        "E03"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "2"
    },
    "gpu.2.10": {
      "value": "n/d",
      "field": "FP64 vector / matrix",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E06",
        "E03"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "2"
    },
    "gpu.2.11": {
      "value": "No attached HBM; external MemoryX separate",
      "field": "Memory: type; stacks; GB; TB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E06",
        "E03"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "2"
    },
    "gpu.2.12": {
      "value": "40 GB SRAM; 20 PB/s aggregate",
      "field": "LLC / SRAM",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E06",
        "E03"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "2"
    },
    "gpu.2.13": {
      "value": "2D mesh; per-link n/d; one wafer",
      "field": "Scale-up: links; GB/s per direction; domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E06",
        "E03"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "2"
    },
    "gpu.2.14": {
      "value": "System I/O; not host PCIe card",
      "field": "Host link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E06",
        "E03"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "2"
    },
    "gpu.2.15": {
      "value": "n/d; liquid",
      "field": "Power / cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E06",
        "E03"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "2"
    },
    "gpu.2.16": {
      "value": "Wafer-scale system",
      "field": "Form factor",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E06",
        "E03"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "2"
    },
    "gpu.3.0": {
      "value": "WSE3 / CS3",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "C02",
        "E02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "3"
    },
    "gpu.3.1": {
      "value": "Wafer-scale dataflow",
      "field": "Architecture",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "C02",
        "E02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "3"
    },
    "gpu.3.2": {
      "value": "2024",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "C02",
        "E02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "3"
    },
    "gpu.3.3": {
      "value": "Shipping / available",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "C02",
        "E02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "3"
    },
    "gpu.3.4": {
      "value": "5 nm",
      "field": "Process",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "C02",
        "E02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "3"
    },
    "gpu.3.5": {
      "value": "1 wafer / system",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "C02",
        "E02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "3"
    },
    "gpu.3.6": {
      "value": "900000 cores",
      "field": "Compute units",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "C02",
        "E02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "3"
    },
    "gpu.3.7": {
      "value": "n/d",
      "field": "Dense BF16",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "C02",
        "E02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "3"
    },
    "gpu.3.8": {
      "value": "n/d",
      "field": "Dense FP8",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "C02",
        "E02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "3"
    },
    "gpu.3.9": {
      "value": "n/d",
      "field": "Dense FP6 / FP4",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "C02",
        "E02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "3"
    },
    "gpu.3.10": {
      "value": "n/d",
      "field": "FP64 vector / matrix",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "C02",
        "E02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "3"
    },
    "gpu.3.11": {
      "value": "No attached HBM; external MemoryX separate",
      "field": "Memory: type; stacks; GB; TB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "C02",
        "E02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "3"
    },
    "gpu.3.12": {
      "value": "44 GB SRAM; 21.6 PB/s aggregate",
      "field": "LLC / SRAM",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "C02",
        "E02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "3"
    },
    "gpu.3.13": {
      "value": "2D mesh; per-link n/d; one wafer",
      "field": "Scale-up: links; GB/s per direction; domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "C02",
        "E02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "3"
    },
    "gpu.3.14": {
      "value": "System I/O; not host PCIe card",
      "field": "Host link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "C02",
        "E02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "3"
    },
    "gpu.3.15": {
      "value": "n/d; liquid",
      "field": "Power / cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "C02",
        "E02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "3"
    },
    "gpu.3.16": {
      "value": "Wafer-scale system",
      "field": "Form factor",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "C02",
        "E02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "3"
    },
    "gpu.3t.0": {
      "value": "WSE3 Turbo / CS4",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026 announcement",
      "status": "announced",
      "scope": "3t"
    },
    "gpu.3t.1": {
      "value": "Wafer-scale dataflow",
      "field": "Architecture",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026 announcement",
      "status": "announced",
      "scope": "3t"
    },
    "gpu.3t.2": {
      "value": "2026 announcement",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026 announcement",
      "status": "announced",
      "scope": "3t"
    },
    "gpu.3t.3": {
      "value": "Announced; GA n/d",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026 announcement",
      "status": "announced",
      "scope": "3t"
    },
    "gpu.3t.4": {
      "value": "5 nm",
      "field": "Process",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026 announcement",
      "status": "announced",
      "scope": "3t"
    },
    "gpu.3t.5": {
      "value": "3 wafers / CS4; numbers per wafer",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026 announcement",
      "status": "announced",
      "scope": "3t"
    },
    "gpu.3t.6": {
      "value": "900000 cores",
      "field": "Compute units",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026 announcement",
      "status": "announced",
      "scope": "3t"
    },
    "gpu.3t.7": {
      "value": "n/d",
      "field": "Dense BF16",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026 announcement",
      "status": "announced",
      "scope": "3t"
    },
    "gpu.3t.8": {
      "value": "n/d",
      "field": "Dense FP8",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026 announcement",
      "status": "announced",
      "scope": "3t"
    },
    "gpu.3t.9": {
      "value": "n/d",
      "field": "Dense FP6 / FP4",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026 announcement",
      "status": "announced",
      "scope": "3t"
    },
    "gpu.3t.10": {
      "value": "n/d",
      "field": "FP64 vector / matrix",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026 announcement",
      "status": "announced",
      "scope": "3t"
    },
    "gpu.3t.11": {
      "value": "No attached HBM; external MemoryX separate",
      "field": "Memory: type; stacks; GB; TB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026 announcement",
      "status": "announced",
      "scope": "3t"
    },
    "gpu.3t.12": {
      "value": "44 GB SRAM; 43.2 PB/s aggregate",
      "field": "LLC / SRAM",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026 announcement",
      "status": "announced",
      "scope": "3t"
    },
    "gpu.3t.13": {
      "value": "2D mesh; per-link n/d; one wafer",
      "field": "Scale-up: links; GB/s per direction; domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026 announcement",
      "status": "announced",
      "scope": "3t"
    },
    "gpu.3t.14": {
      "value": "System I/O; not host PCIe card",
      "field": "Host link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026 announcement",
      "status": "announced",
      "scope": "3t"
    },
    "gpu.3t.15": {
      "value": "n/d; liquid",
      "field": "Power / cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026 announcement",
      "status": "announced",
      "scope": "3t"
    },
    "gpu.3t.16": {
      "value": "Wafer-scale system",
      "field": "Form factor",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026 announcement",
      "status": "announced",
      "scope": "3t"
    },
    "cpu.none.0": {
      "value": "External preprocessing / management CPUs",
      "field": "Generation / reference SKU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "none"
    },
    "cpu.none.1": {
      "value": "n/a",
      "field": "Codename",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "none"
    },
    "cpu.none.2": {
      "value": "n/a",
      "field": "GA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "none"
    },
    "cpu.none.3": {
      "value": "Supplier products",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "none"
    },
    "cpu.none.4": {
      "value": "n/a",
      "field": "Core µarch",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "none"
    },
    "cpu.none.5": {
      "value": "n/a",
      "field": "Cores / threads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "none"
    },
    "cpu.none.6": {
      "value": "n/a",
      "field": "Process per die",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "none"
    },
    "cpu.none.7": {
      "value": "n/a",
      "field": "Dies / packaging",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "none"
    },
    "cpu.none.8": {
      "value": "n/a",
      "field": "L2 per core",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "none"
    },
    "cpu.none.9": {
      "value": "n/a",
      "field": "L3 / domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "none"
    },
    "cpu.none.10": {
      "value": "n/a",
      "field": "Memory: channels; rate; GB/s",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "none"
    },
    "cpu.none.11": {
      "value": "n/a",
      "field": "Sockets / links",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "none"
    },
    "cpu.none.12": {
      "value": "n/a",
      "field": "PCIe / CXL",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "none"
    },
    "cpu.none.13": {
      "value": "n/a",
      "field": "TDP",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "none"
    },
    "cpu.none.14": {
      "value": "n/a",
      "field": "Vector / matrix ISA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "external",
      "scope": "none"
    },
    "system.a.0": {
      "value": "CS1",
      "field": "Platform",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "a"
    },
    "system.a.1": {
      "value": "2019",
      "field": "Year / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "a"
    },
    "system.a.2": {
      "value": "1 WSE1",
      "field": "CPU / accelerator count",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "a"
    },
    "system.a.3": {
      "value": "1 wafer; cluster topology n/d",
      "field": "Scale-up domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "a"
    },
    "system.a.4": {
      "value": "n/d",
      "field": "Scale-out per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "a"
    },
    "system.a.5": {
      "value": "n/d",
      "field": "Rack power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "a"
    },
    "system.a.6": {
      "value": "Liquid",
      "field": "Cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "shipping",
      "scope": "a"
    },
    "system.b.0": {
      "value": "CS2 + MemoryX/SwarmX",
      "field": "Platform",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "b"
    },
    "system.b.1": {
      "value": "2021",
      "field": "Year / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "b"
    },
    "system.b.2": {
      "value": "1 WSE2 per CS2",
      "field": "CPU / accelerator count",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "b"
    },
    "system.b.3": {
      "value": "Weight Streaming cluster",
      "field": "Scale-up domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "b"
    },
    "system.b.4": {
      "value": "n/d",
      "field": "Scale-out per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "b"
    },
    "system.b.5": {
      "value": "n/d",
      "field": "Rack power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "b"
    },
    "system.b.6": {
      "value": "Liquid",
      "field": "Cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "b"
    },
    "system.c.0": {
      "value": "CS3",
      "field": "Platform",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "E02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "c"
    },
    "system.c.1": {
      "value": "2024",
      "field": "Year / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "E02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "c"
    },
    "system.c.2": {
      "value": "1 WSE3; up to 2048 systems",
      "field": "CPU / accelerator count",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "E02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "c"
    },
    "system.c.3": {
      "value": "SwarmX / workload placement",
      "field": "Scale-up domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "E02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "c"
    },
    "system.c.4": {
      "value": "1.2 Tb/s system I/O; direction n/d",
      "field": "Scale-out per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "E02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "c"
    },
    "system.c.5": {
      "value": "n/d",
      "field": "Rack power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "E02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "c"
    },
    "system.c.6": {
      "value": "Liquid",
      "field": "Cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "E02"
      ],
      "disclosure_date": "2024",
      "status": "shipping",
      "scope": "c"
    },
    "system.d.0": {
      "value": "CS4 / Nexus",
      "field": "Platform",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "d"
    },
    "system.d.1": {
      "value": "2026 announcement",
      "field": "Year / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "d"
    },
    "system.d.2": {
      "value": "3 WSE3T",
      "field": "CPU / accelerator count",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "d"
    },
    "system.d.3": {
      "value": "Direct Wafer Links / Ethernet",
      "field": "Scale-up domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "d"
    },
    "system.d.4": {
      "value": "2.4 Tb/s per wafer; direction n/d",
      "field": "Scale-out per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "d"
    },
    "system.d.5": {
      "value": "n/d",
      "field": "Rack power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "d"
    },
    "system.d.6": {
      "value": "Modular liquid cooling",
      "field": "Cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "d"
    },
    "system.e.0": {
      "value": "CS5 / CS6",
      "field": "Platform",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "e"
    },
    "system.e.1": {
      "value": "2027 target / later",
      "field": "Year / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "e"
    },
    "system.e.2": {
      "value": "n/d",
      "field": "CPU / accelerator count",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "e"
    },
    "system.e.3": {
      "value": "n/d",
      "field": "Scale-up domain",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "e"
    },
    "system.e.4": {
      "value": "n/d",
      "field": "Scale-out per accelerator",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "e"
    },
    "system.e.5": {
      "value": "n/d",
      "field": "Rack power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "e"
    },
    "system.e.6": {
      "value": "n/d",
      "field": "Cooling",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C03"
      ],
      "disclosure_date": "2026",
      "status": "roadmap",
      "scope": "e"
    },
    "nic.a.0": {
      "value": "SwarmX",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "a"
    },
    "nic.a.1": {
      "value": "2021",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "a"
    },
    "nic.a.2": {
      "value": "Shipping / available",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "a"
    },
    "nic.a.3": {
      "value": "Broadcast/reduce fabric",
      "field": "Class",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "a"
    },
    "nic.a.4": {
      "value": "n/d",
      "field": "Ports × speed",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "a"
    },
    "nic.a.5": {
      "value": "n/d",
      "field": "SerDes",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "a"
    },
    "nic.a.6": {
      "value": "System Ethernet",
      "field": "Host interface",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "a"
    },
    "nic.a.7": {
      "value": "Collective acceleration",
      "field": "Programmable engine",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "a"
    },
    "nic.a.8": {
      "value": "n/d",
      "field": "Embedded CPU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "a"
    },
    "nic.a.9": {
      "value": "n/d",
      "field": "On-card memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "a"
    },
    "nic.a.10": {
      "value": "Weight/gradient streaming",
      "field": "Transport / RDMA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "a"
    },
    "nic.a.11": {
      "value": "n/d",
      "field": "Congestion control",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "a"
    },
    "nic.a.12": {
      "value": "Broadcast / reduction",
      "field": "Key offloads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "a"
    },
    "nic.a.13": {
      "value": "n/d",
      "field": "Power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "a"
    },
    "nic.b.0": {
      "value": "Wafer I/O Module",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "b"
    },
    "nic.b.1": {
      "value": "2026",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "b"
    },
    "nic.b.2": {
      "value": "Announced; GA n/d",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "b"
    },
    "nic.b.3": {
      "value": "Programmable wafer I/O",
      "field": "Class",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "b"
    },
    "nic.b.4": {
      "value": "2.4 Tb/s/wafer aggregate; direction n/d",
      "field": "Ports × speed",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "b"
    },
    "nic.b.5": {
      "value": "n/d",
      "field": "SerDes",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "b"
    },
    "nic.b.6": {
      "value": "Wafer system interface",
      "field": "Host interface",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "b"
    },
    "nic.b.7": {
      "value": "Programmable I/O",
      "field": "Programmable engine",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "b"
    },
    "nic.b.8": {
      "value": "n/d",
      "field": "Embedded CPU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "b"
    },
    "nic.b.9": {
      "value": "n/d",
      "field": "On-card memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "b"
    },
    "nic.b.10": {
      "value": "RoCEv2 / Direct Wafer Links",
      "field": "Transport / RDMA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "b"
    },
    "nic.b.11": {
      "value": "n/d",
      "field": "Congestion control",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "b"
    },
    "nic.b.12": {
      "value": "Wafer-to-wafer data movement",
      "field": "Key offloads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "b"
    },
    "nic.b.13": {
      "value": "n/d",
      "field": "Power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "b"
    },
    "nic.c.0": {
      "value": "Merchant DPU / host NIC",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "not_applicable",
      "scope": "c"
    },
    "nic.c.1": {
      "value": "n/a",
      "field": "GA / milestone",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "not_applicable",
      "scope": "c"
    },
    "nic.c.2": {
      "value": "n/a",
      "field": "Status",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "not_applicable",
      "scope": "c"
    },
    "nic.c.3": {
      "value": "n/a",
      "field": "Class",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "not_applicable",
      "scope": "c"
    },
    "nic.c.4": {
      "value": "n/a",
      "field": "Ports × speed",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "not_applicable",
      "scope": "c"
    },
    "nic.c.5": {
      "value": "n/a",
      "field": "SerDes",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "not_applicable",
      "scope": "c"
    },
    "nic.c.6": {
      "value": "n/a",
      "field": "Host interface",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "not_applicable",
      "scope": "c"
    },
    "nic.c.7": {
      "value": "n/a",
      "field": "Programmable engine",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "not_applicable",
      "scope": "c"
    },
    "nic.c.8": {
      "value": "n/a",
      "field": "Embedded CPU",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "not_applicable",
      "scope": "c"
    },
    "nic.c.9": {
      "value": "n/a",
      "field": "On-card memory",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "not_applicable",
      "scope": "c"
    },
    "nic.c.10": {
      "value": "n/a",
      "field": "Transport / RDMA",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "not_applicable",
      "scope": "c"
    },
    "nic.c.11": {
      "value": "n/a",
      "field": "Congestion control",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "not_applicable",
      "scope": "c"
    },
    "nic.c.12": {
      "value": "n/a",
      "field": "Key offloads",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "not_applicable",
      "scope": "c"
    },
    "nic.c.13": {
      "value": "n/a",
      "field": "Power",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "not_applicable",
      "scope": "c"
    },
    "links.a.0": {
      "value": "On-wafer mesh",
      "field": "Interconnect",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2022",
      "status": "disclosed",
      "scope": "a"
    },
    "links.a.1": {
      "value": "WSE1-3T",
      "field": "Year / generation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2022",
      "status": "disclosed",
      "scope": "a"
    },
    "links.a.2": {
      "value": "Generation-specific",
      "field": "Lane rate",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2022",
      "status": "disclosed",
      "scope": "a"
    },
    "links.a.3": {
      "value": "32-bit interfaces in HC2022",
      "field": "Lanes / link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2022",
      "status": "disclosed",
      "scope": "a"
    },
    "links.a.4": {
      "value": "n/d",
      "field": "GB/s per link per direction",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2022",
      "status": "disclosed",
      "scope": "a"
    },
    "links.a.5": {
      "value": "4 neighbors/core",
      "field": "Links / device",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2022",
      "status": "disclosed",
      "scope": "a"
    },
    "links.a.6": {
      "value": "2D mesh",
      "field": "Topology",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2022",
      "status": "disclosed",
      "scope": "a"
    },
    "links.a.7": {
      "value": "Wafer",
      "field": "Domain limit",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2022",
      "status": "disclosed",
      "scope": "a"
    },
    "links.a.8": {
      "value": "Explicit local-memory messages",
      "field": "Coherence / semantics",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C01"
      ],
      "disclosure_date": "2022",
      "status": "disclosed",
      "scope": "a"
    },
    "links.b.0": {
      "value": "SwarmX",
      "field": "Interconnect",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "b"
    },
    "links.b.1": {
      "value": "2021 onward",
      "field": "Year / generation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "b"
    },
    "links.b.2": {
      "value": "n/d",
      "field": "Lane rate",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "b"
    },
    "links.b.3": {
      "value": "n/d",
      "field": "Lanes / link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "b"
    },
    "links.b.4": {
      "value": "n/d",
      "field": "GB/s per link per direction",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "b"
    },
    "links.b.5": {
      "value": "n/d",
      "field": "Links / device",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "b"
    },
    "links.b.6": {
      "value": "Broadcast / reduction tree",
      "field": "Topology",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "b"
    },
    "links.b.7": {
      "value": "System configuration",
      "field": "Domain limit",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "b"
    },
    "links.b.8": {
      "value": "Weight streaming; not coherent",
      "field": "Coherence / semantics",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E03",
        "P01"
      ],
      "disclosure_date": "2021",
      "status": "shipping",
      "scope": "b"
    },
    "links.c.0": {
      "value": "Direct Wafer Links",
      "field": "Interconnect",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "c"
    },
    "links.c.1": {
      "value": "2026",
      "field": "Year / generation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "c"
    },
    "links.c.2": {
      "value": "n/d",
      "field": "Lane rate",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "c"
    },
    "links.c.3": {
      "value": "n/d",
      "field": "Lanes / link",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "c"
    },
    "links.c.4": {
      "value": "n/d",
      "field": "GB/s per link per direction",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "c"
    },
    "links.c.5": {
      "value": "n/d",
      "field": "Links / device",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "c"
    },
    "links.c.6": {
      "value": "Switchless wafer links",
      "field": "Topology",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "c"
    },
    "links.c.7": {
      "value": "n/d",
      "field": "Domain limit",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "c"
    },
    "links.c.8": {
      "value": "Explicit communication",
      "field": "Coherence / semantics",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026",
      "status": "announced",
      "scope": "c"
    },
    "software.a.0": {
      "value": "Model",
      "field": "Layer",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "E01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "available",
      "scope": "a"
    },
    "software.a.1": {
      "value": "Framework / model compiler",
      "field": "Component",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "E01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "available",
      "scope": "a"
    },
    "software.a.2": {
      "value": "Compile training and inference",
      "field": "Function",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "E01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "available",
      "scope": "a"
    },
    "software.a.3": {
      "value": "Operator and numerical support",
      "field": "Constraint",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "E01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "available",
      "scope": "a"
    },
    "software.b.0": {
      "value": "Kernel",
      "field": "Layer",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04",
        "C07"
      ],
      "disclosure_date": "2026-09-28",
      "status": "available",
      "scope": "b"
    },
    "software.b.1": {
      "value": "CSL / dataflow mapping",
      "field": "Component",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04",
        "C07"
      ],
      "disclosure_date": "2026-09-28",
      "status": "available",
      "scope": "b"
    },
    "software.b.2": {
      "value": "Spatial compute and communication",
      "field": "Function",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04",
        "C07"
      ],
      "disclosure_date": "2026-09-28",
      "status": "available",
      "scope": "b"
    },
    "software.b.3": {
      "value": "Local memory and mesh routing",
      "field": "Constraint",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C04",
        "C07"
      ],
      "disclosure_date": "2026-09-28",
      "status": "available",
      "scope": "b"
    },
    "software.c.0": {
      "value": "Training",
      "field": "Layer",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "E03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "available",
      "scope": "c"
    },
    "software.c.1": {
      "value": "MemoryX / SwarmX control",
      "field": "Component",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "E03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "available",
      "scope": "c"
    },
    "software.c.2": {
      "value": "Weights and gradient reduction",
      "field": "Function",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "E03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "available",
      "scope": "c"
    },
    "software.c.3": {
      "value": "Streaming schedule and bandwidth",
      "field": "Constraint",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01",
        "E03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "available",
      "scope": "c"
    },
    "software.d.0": {
      "value": "Operations",
      "field": "Layer",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "available",
      "scope": "d"
    },
    "software.d.1": {
      "value": "Management / preprocessing servers",
      "field": "Component",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "available",
      "scope": "d"
    },
    "software.d.2": {
      "value": "Input and resource scheduling",
      "field": "Function",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "available",
      "scope": "d"
    },
    "software.d.3": {
      "value": "External hosts and services",
      "field": "Constraint",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "available",
      "scope": "d"
    },
    "ratios.a.0": {
      "value": "WSE2→WSE3 core growth",
      "field": "Metric",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E06",
        "E01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "a"
    },
    "ratios.a.1": {
      "value": "900000/850000 = 1.059",
      "field": "Calculation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E06",
        "E01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "a"
    },
    "ratios.a.2": {
      "value": "5.9%, not 20%",
      "field": "Meaning",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E06",
        "E01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "a"
    },
    "ratios.b.0": {
      "value": "WSE3→CS4 SRAM",
      "field": "Metric",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "b"
    },
    "ratios.b.1": {
      "value": "3×44 = 132 GB",
      "field": "Calculation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "b"
    },
    "ratios.b.2": {
      "value": "System aggregation; not one wafer",
      "field": "Meaning",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "b"
    },
    "ratios.c.0": {
      "value": "WSE3T SRAM/external I/O",
      "field": "Metric",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "c"
    },
    "ratios.c.1": {
      "value": "43.2 PB/s / 0.0003 PB/s = 144000",
      "field": "Calculation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "c"
    },
    "ratios.c.2": {
      "value": "Scale contrast; direction and topology differ",
      "field": "Meaning",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "c"
    },
    "ratios.d.0": {
      "value": "CS4 I/O unit conversion",
      "field": "Metric",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "d"
    },
    "ratios.d.1": {
      "value": "7.2 Tb/s /8 = 900 GB/s",
      "field": "Calculation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "d"
    },
    "ratios.d.2": {
      "value": "Nominal aggregate; direction n/d",
      "field": "Meaning",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "d"
    },
    "ratios.e.0": {
      "value": "44 GB / BF16 weight",
      "field": "Metric",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "e"
    },
    "ratios.e.1": {
      "value": "44e9/2 = 22 billion parameters",
      "field": "Calculation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "e"
    },
    "ratios.e.2": {
      "value": "Capacity upper bound before code/KV/workspace",
      "field": "Meaning",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "derived",
      "scope": "e"
    },
    "ratios.f.0": {
      "value": "Dense HBM/FLOP",
      "field": "Metric",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C02"
      ],
      "disclosure_date": "2026-09-28",
      "status": "not_applicable",
      "scope": "f"
    },
    "ratios.f.1": {
      "value": "n/a",
      "field": "Calculation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C02"
      ],
      "disclosure_date": "2026-09-28",
      "status": "not_applicable",
      "scope": "f"
    },
    "ratios.f.2": {
      "value": "SRAM architecture; no HBM tier",
      "field": "Meaning",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C02"
      ],
      "disclosure_date": "2026-09-28",
      "status": "not_applicable",
      "scope": "f"
    },
    "ratios.g.0": {
      "value": "SRAM/FLOP; capacity/FLOP; FLOP/W",
      "field": "Metric",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "E02"
      ],
      "disclosure_date": "2026-09-28",
      "status": "unknown",
      "scope": "g"
    },
    "ratios.g.1": {
      "value": "n/d",
      "field": "Calculation",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "E02"
      ],
      "disclosure_date": "2026-09-28",
      "status": "unknown",
      "scope": "g"
    },
    "ratios.g.2": {
      "value": "Matched dense format and power basis absent",
      "field": "Meaning",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01",
        "E02"
      ],
      "disclosure_date": "2026-09-28",
      "status": "unknown",
      "scope": "g"
    },
    "ratios.h.0": {
      "value": "Host DDR/core; L3/core",
      "field": "Metric",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "not_applicable",
      "scope": "h"
    },
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      "field": "Calculation",
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      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "not_applicable",
      "scope": "h"
    },
    "ratios.h.2": {
      "value": "No proprietary host CPU",
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      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "not_applicable",
      "scope": "h"
    },
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        "E05"
      ],
      "disclosure_date": "2019",
      "status": "published",
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    },
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      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "published",
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    },
    "conference.a.2": {
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        "E05"
      ],
      "disclosure_date": "2019",
      "status": "published",
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    },
    "conference.a.3": {
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      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "published",
      "scope": "a"
    },
    "conference.a.4": {
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      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "published",
      "scope": "a"
    },
    "conference.a.5": {
      "value": "Architecture / implementation / workload",
      "field": "Evidence type",
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      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "published",
      "scope": "a"
    },
    "conference.a.6": {
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      "field": "Source",
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      "source": [
        "E05"
      ],
      "disclosure_date": "2019",
      "status": "published",
      "scope": "a"
    },
    "conference.b.0": {
      "value": "Hot Chips",
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      "source": [
        "E06",
        "E03"
      ],
      "disclosure_date": "2021",
      "status": "published",
      "scope": "b"
    },
    "conference.b.1": {
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      "field": "Year",
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      "source": [
        "E06",
        "E03"
      ],
      "disclosure_date": "2021",
      "status": "published",
      "scope": "b"
    },
    "conference.b.2": {
      "value": "Extreme-scale AI / Weight Streaming",
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      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E06",
        "E03"
      ],
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      "status": "published",
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    },
    "conference.b.3": {
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        "E06",
        "E03"
      ],
      "disclosure_date": "2021",
      "status": "published",
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    },
    "conference.b.4": {
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      "source": [
        "E06",
        "E03"
      ],
      "disclosure_date": "2021",
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    },
    "conference.b.5": {
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        "E03"
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      "disclosure_date": "2021",
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    },
    "conference.b.6": {
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      "source": [
        "E06",
        "E03"
      ],
      "disclosure_date": "2021",
      "status": "published",
      "scope": "b"
    },
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        "C01"
      ],
      "disclosure_date": "2022",
      "status": "published",
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    },
    "conference.c.1": {
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      "source": [
        "C01"
      ],
      "disclosure_date": "2022",
      "status": "published",
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    },
    "conference.c.2": {
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        "C01"
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    },
    "conference.c.3": {
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        "C01"
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      "status": "published",
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    },
    "conference.c.4": {
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        "C01"
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      "disclosure_date": "2022",
      "status": "published",
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    },
    "conference.c.5": {
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        "C01"
      ],
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      "status": "published",
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    },
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      "source": [
        "C01"
      ],
      "disclosure_date": "2022",
      "status": "published",
      "scope": "c"
    },
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      "source": [
        "C06"
      ],
      "disclosure_date": "2023",
      "status": "published",
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    },
    "conference.d.1": {
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      "source": [
        "C06"
      ],
      "disclosure_date": "2023",
      "status": "published",
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    },
    "conference.d.2": {
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        "C06"
      ],
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      "status": "published",
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    },
    "conference.d.3": {
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        "C06"
      ],
      "disclosure_date": "2023",
      "status": "published",
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    },
    "conference.d.4": {
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        "C06"
      ],
      "disclosure_date": "2023",
      "status": "published",
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    },
    "conference.d.5": {
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      "disclosure_date": "2023",
      "status": "published",
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    },
    "conference.d.6": {
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      "source": [
        "C06"
      ],
      "disclosure_date": "2023",
      "status": "published",
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    },
    "conference.e.0": {
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        "C02"
      ],
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      "status": "published",
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    },
    "conference.e.1": {
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      ],
      "disclosure_date": "2024",
      "status": "published",
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    },
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      "disclosure_date": "2026",
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    },
    "conference.f.1": {
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      ],
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    },
    "conference.f.2": {
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      ],
      "disclosure_date": "2026",
      "status": "published",
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    },
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      ],
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      "disclosure_date": "2026",
      "status": "published",
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    },
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      "source": [
        "C03"
      ],
      "disclosure_date": "2026",
      "status": "published",
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    },
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      "source": [
        "C05"
      ],
      "disclosure_date": "2020",
      "status": "published",
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    },
    "conference.g.1": {
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        "C05"
      ],
      "disclosure_date": "2020",
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    },
    "conference.g.2": {
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        "C05"
      ],
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    },
    "conference.g.3": {
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        "C05"
      ],
      "disclosure_date": "2020",
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    },
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    },
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        "C05"
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      "disclosure_date": "2020",
      "status": "published",
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    },
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      "source": [
        "C05"
      ],
      "disclosure_date": "2020",
      "status": "published",
      "scope": "g"
    },
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        "C07"
      ],
      "disclosure_date": "2020",
      "status": "published",
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    },
    "conference.h.1": {
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      "field": "Year",
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      "source": [
        "C07"
      ],
      "disclosure_date": "2020",
      "status": "published",
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    },
    "conference.h.2": {
      "value": "Fast Stencil-Code Computation",
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        "C07"
      ],
      "disclosure_date": "2020",
      "status": "published",
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    },
    "conference.h.3": {
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      "field": "Presenter / authors",
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      "source": [
        "C07"
      ],
      "disclosure_date": "2020",
      "status": "published",
      "scope": "h"
    },
    "conference.h.4": {
      "value": "CS1 research workload",
      "field": "Product",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C07"
      ],
      "disclosure_date": "2020",
      "status": "published",
      "scope": "h"
    },
    "conference.h.5": {
      "value": "Architecture / implementation / workload",
      "field": "Evidence type",
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      "source": [
        "C07"
      ],
      "disclosure_date": "2020",
      "status": "published",
      "scope": "h"
    },
    "conference.h.6": {
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      "field": "Source",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "C07"
      ],
      "disclosure_date": "2020",
      "status": "published",
      "scope": "h"
    },
    "cross.a.0": {
      "value": "WSE",
      "field": "Name",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "a"
    },
    "cross.a.1": {
      "value": "Wafer processor",
      "field": "Meaning",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "a"
    },
    "cross.a.2": {
      "value": "Silicon generation",
      "field": "Boundary",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "a"
    },
    "cross.b.0": {
      "value": "CS",
      "field": "Name",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "b"
    },
    "cross.b.1": {
      "value": "Complete compute system",
      "field": "Meaning",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "b"
    },
    "cross.b.2": {
      "value": "CS4 uses three WSE3T",
      "field": "Boundary",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "b"
    },
    "cross.c.0": {
      "value": "MemoryX",
      "field": "Name",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "c"
    },
    "cross.c.1": {
      "value": "External model storage/streaming",
      "field": "Meaning",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "c"
    },
    "cross.c.2": {
      "value": "Not on-wafer SRAM",
      "field": "Boundary",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "P01"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "c"
    },
    "cross.d.0": {
      "value": "Swarm / SwarmX",
      "field": "Name",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05",
        "E03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "d"
    },
    "cross.d.1": {
      "value": "On-wafer fabric / cluster fabric",
      "field": "Meaning",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05",
        "E03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "d"
    },
    "cross.d.2": {
      "value": "Different physical boundaries",
      "field": "Boundary",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E05",
        "E03"
      ],
      "disclosure_date": "2026-09-28",
      "status": "disclosed",
      "scope": "d"
    },
    "cross.e.0": {
      "value": "Nexus",
      "field": "Name",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
        "E02"
      ],
      "disclosure_date": "2026-09-28",
      "status": "announced",
      "scope": "e"
    },
    "cross.e.1": {
      "value": "Rack platform",
      "field": "Meaning",
      "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled",
      "source": [
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