{ "vendor": "Cambricon", "cutoff": "2026-09-28", "sections": [ { "id": "01", "title": [ "Scope and architectural synthesis", "范围与架构主线" ], "blocks": [ { "id": "01.scope", "type": "prose", "text": [ "The report covers Cambricon’s publicly documented AI infrastructure from 2015 to 28 September 2026, with DianNao-era research as a pre-company baseline. Deep coverage follows Siyuan/MLU cloud accelerators, memory, MLU-Link and NeuWare. Terminal IP and the MLU220 edge branch explain technology continuity. No proprietary server CPU, merchant DPU or shipping AI NIC is inferred merely from the company’s broader AI ambitions.", "本报告覆盖寒武纪在 2015 年至 2026 年 9 月 28 日公开记录的 AI 基础设施，并以前公司时期的 DianNao 研究为基线。深入梳理思元／MLU 云端加速器、存储、MLU-Link 与 NeuWare；终端 IP 和 MLU220 边缘分支用于解释技术延续。不因公司具有更广泛 AI 战略，就推定存在自研服务器 CPU、商用 DPU 或已交付 AI NIC。" ], "sources": [ "P01", "P02", "E02", "E03" ] }, { "id": "01.thesis", "type": "prose", "text": [ "The strongest continuity is programmable domain specialization: a machine-learning instruction interface, tensor execution, explicit data movement and a software platform spanning cloud and edge. Commercial evolution adds larger SoCs, training support, chiplets and multi-device communication. The public academic record is much richer than the disclosure of recent commercial implementations. Those two evidence streams should inform each other without being treated as an exact RTL lineage.", "最强的技术延续是可编程领域专用化：机器学习指令接口、张量执行、显式数据搬移，以及横跨云边端的软件平台。商业演进逐步加入更大 SoC、训练支持、小芯片及多设备通信。公开学术记录远比近期商业实现披露丰富，两类证据可以相互解释，但不能视为精确 RTL 谱系。" ], "sources": [ "C02", "C03", "P02", "E02" ] } ] }, { "id": "02", "title": [ "Research lineage: what the architecture conferences establish", "研究谱系：架构会议能证明什么" ], "blocks": [ { "id": "02.diannao", "type": "prose", "text": [ "DianNao at ASPLOS 2014 and DaDianNao at MICRO 2014 established early neural-acceleration research. PuDianNao at ASPLOS 2015 broadens the machine-learning workload scope; ShiDianNao at ISCA 2015 moves vision processing toward the sensor. The author’s institutional page explicitly reserves the DianNao names for those academic designs. They are therefore recorded as research predecessors, not early commercial Siyuan SKUs.", "ASPLOS 2014 的 DianNao 与 MICRO 2014 的 DaDianNao 建立早期神经网络加速研究。ASPLOS 2015 的 PuDianNao 扩展机器学习负载范围；ISCA 2015 的 ShiDianNao 把视觉处理推向传感器附近。作者机构主页明确将 DianNao 名称保留给这些学术设计。因此，本报告将其记录为研究前身，而不是早期商业思元 SKU。" ], "sources": [ "C01", "C03" ] }, { "id": "02.isa", "type": "prose", "text": [ "The ISCA 2016 Cambricon ISA paper addresses the gap between fixed-function neural engines and general-purpose instruction streams. A domain-specific ISA can express common neural operations while preserving programmability. That is a useful lens for understanding later MLU software, but the published prototype’s process, area and performance cannot be transplanted into a commercial MLU table without a documented mapping.", "ISCA 2016 的 Cambricon ISA 论文针对固定功能神经网络引擎与通用指令流之间的缺口。领域专用 ISA 可以表达常见神经网络操作，同时保留可编程性。这有助于理解后续 MLU 软件，但若缺少明确对应关系，不能把论文原型的工艺、面积和性能移植到商业 MLU 规格表。" ], "sources": [ "C02" ] }, { "id": "02.sparse", "type": "prose", "text": [ "Cambricon-X at MICRO 2016 and Cambricon-S at MICRO 2018 address sparse and irregular networks. Cambricon-F at ISCA 2019 studies a hierarchical, self-similar programming architecture; Cambricon-Q at ISCA 2021 targets efficient training. The research progression spans sparsity, programmability and training precision. It establishes engineering priorities, not proof that an identically named mechanism ships in every generation.", "MICRO 2016 的 Cambricon-X 与 MICRO 2018 的 Cambricon-S 研究稀疏及不规则网络。ISCA 2019 的 Cambricon-F 研究分层、自相似编程架构；ISCA 2021 的 Cambricon-Q 面向高效训练。研究主线覆盖稀疏性、可编程性和训练精度，建立工程关注点，但不证明同名机制在每代产品中交付。" ], "sources": [ "C03", "C04" ] }, { "id": "02.f", "type": "prose", "text": [ "Cambricon-F recursively decomposes operations through nodes sharing an instruction model and a hierarchical memory organization. The proposal aims to reduce the programming burden across scales. Architectural interpretation: a uniform interface does not eliminate placement, reduction or congestion costs; it changes where they are handled. The paper discusses those challenges explicitly. Its research instances F1/F100 are not MLU100 or MLU270 product names.", "Cambricon-F 通过共享指令模型及分层存储组织的节点，递归分解操作，目标是降低不同规模下的编程负担。架构解读：统一接口并未消除放置、归约或拥塞成本，而是改变处理这些成本的位置。论文明确讨论这些挑战，其中研究实例 F1／F100 不等于 MLU100 或 MLU270 产品名称。" ], "sources": [ "C04" ] }, { "id": "02.llm", "type": "prose", "text": [ "The 2024 Cambricon-LLM research proposes an NPU plus specially designed flash with on-die processing for low-batch edge inference. It is a useful example of capacity/bandwidth co-design, but is not a disclosed production implementation of a Siyuan server accelerator. Flash capacity, DRAM KV storage and compute-side bandwidth are distinct resources.", "2024 年 Cambricon-LLM 研究提出 NPU 配合具有片内处理能力的专用闪存，用于小批量边缘推理。这是容量与带宽协同设计的例子，但不是已披露的思元服务器加速器量产实现。闪存容量、DRAM 中的 KV 存储与计算侧带宽是不同资源。" ], "sources": [ "C05" ] } ] }, { "id": "03", "title": [ "Commercial generations: MLU100, 270 and 290", "商业代际：MLU100、270 与 290" ], "blocks": [ { "id": "03.100", "type": "prose", "text": [ "Siyuan100 introduced the cloud accelerator line in 2018. The 270 generation adds MLUv02, a NoC connecting up to sixteen tensor cores, hardware data compression and video/image functions. Its official page explicitly identifies 128 INT8 TOPS for nonsparse models, alongside 256 INT4 TOPS and 64 INT16 TOPS. Precision changes must not be described as architectural speedups on the same workload.", "思元100 于 2018 年建立云端加速器产品线。270 代增加 MLUv02、连接最多十六个张量核心的片上网络、硬件数据压缩及视频／图像功能。官方页面明确给出非稀疏模型的 INT8 128 TOPS，以及 INT4 256 TOPS 和 INT16 64 TOPS。精度变化不能描述为同一负载的架构加速比。" ], "sources": [ "P01", "E05" ] }, { "id": "03.290", "type": "prose", "text": [ "Siyuan290 is the training-oriented branch, publicly exhibited with MLU290-M5 modules and the XuanSi1000/MLU-X1000 system at WAIC 2021. Its importance is the transition from a predominantly inference product story to multi-accelerator training and system software. This edition does not fill missing board-matched HBM, power or floating-point rates from secondary product lists. A training product’s existence and an exact implementation specification are separate claims.", "思元290 是面向训练的分支，在 WAIC 2021 与 MLU290-M5 模块及玄思1000／MLU-X1000 系统一同公开展示。其重要性在于从以推理为主的产品叙事，转向多加速器训练与系统软件。本版不从二手产品列表补填缺少板卡匹配依据的 HBM、功耗或浮点速率。训练产品存在与精确实现规格是两种不同陈述。" ], "sources": [ "E03", "E02" ] } ] }, { "id": "04", "title": [ "MLU370: chiplets, fusion and board differentiation", "MLU370：小芯片、融合与板卡差异" ], "blocks": [ { "id": "04.370", "type": "prose", "text": [ "Siyuan370 combines two AI compute chiplets in a 7 nm product with 39 billion transistors. MLUarch03 adds tensor-unit improvements, the Supercharger convolution mechanism and hardware support for multi-operator fusion. LPDDR5 and MLU-Link expand the memory and multi-device design space. Chiplet integration is a packaging boundary within a chip; a dual-chip board is a separate boundary and must not be counted as the same thing.", "思元370 采用 7 nm 工艺，将两个 AI 计算小芯片封装为产品，集成 390 亿晶体管。MLUarch03 增加张量单元改进、Supercharger 卷积机制及多算子硬件融合支持。LPDDR5 与 MLU-Link 扩展存储及多设备设计空间。小芯片集成是芯片内部封装边界，双芯板卡则是另一层边界，两者不能混为一谈。" ], "sources": [ "P02" ] }, { "id": "04.boards", "type": "prose", "text": [ "The current official specifications are particularly informative: X4 and X8 both list 96 TFLOP/s BF16 and 256 INT8 TOPS, while X8 doubles memory capacity and bandwidth to 48 GB and 614.4 GB/s. X8 uses two Siyuan370 chips and provides a dedicated MLU-Link interface. Thus two chips on a board do not justify doubling the published board compute rate. The S4/S8 branch trades peak compute for a 75 W, compact deployment envelope.", "当前官方规格很有说明力：X4 与 X8 都列出 BF16 96 TFLOP/s 和 INT8 256 TOPS，而 X8 把内存容量及带宽加倍至 48 GB、614.4 GB/s。X8 使用两颗思元370，并提供专用 MLU-Link 接口。因此板上两颗芯片不意味着可以把公布的板卡算力再乘二。S4／S8 分支则以较低峰值算力换取 75 W 的紧凑部署条件。" ], "sources": [ "P04", "P05", "P06" ] }, { "id": "04.trade", "type": "prose", "text": [ "Architectural interpretation: the X8 configuration targets data capacity, bandwidth, codec resources and multi-card communication as much as arithmetic density. This can favor larger or bandwidth-sensitive workloads even when peak BF16 matches X4. Fusion helps only when intermediate data and execution dependencies fit the supported mechanism. A portable model graph may still require layout, quantization and kernel tuning to exploit the hardware.", "架构解读：X8 配置对数据容量、带宽、编解码资源及多卡通信的关注，不亚于算术密度。即使峰值 BF16 与 X4 相同，它仍可能更适合大型或带宽敏感负载。融合只有在中间数据及执行依赖适合支持机制时才有收益。模型图可移植，也可能仍需调整布局、量化和算子，才能发挥硬件能力。" ], "sources": [ "P02", "P05", "P06", "P07" ] } ] }, { "id": "05", "title": [ "Cloud accelerator and board tables", "云端加速器与板卡规格" ], "blocks": [ { "id": "gpu", "type": "table", "table": "gpu" }, { "id": "cpu", "type": "table", "table": "cpu" } ] }, { "id": "06", "title": [ "MLU-Link, systems and the networking roadmap", "MLU-Link、系统与网络路线图" ], "blocks": [ { "id": "06.link", "type": "prose", "text": [ "The X8 board page resolves a key unit issue: 200 GB/s is aggregate bidirectional MLU-Link bandwidth, corresponding to 100 GB/s per direction when divided symmetrically. It lists four ports, sixteen lanes and 50 Gb/s signaling; the board-wide lane/port wording is retained rather than assuming sixteen lanes per port. The page supports an eight-card server configuration but does not establish transparent memory coherence or a fully connected topology.", "X8 板卡页面澄清一个关键口径：MLU-Link 的 200 GB/s 是聚合双向带宽，对称分配时对应每方向 100 GB/s。页面列出四端口、十六通道及 50 Gb/s 信号速率；本报告保留板级通道／端口表述，不假定每端口十六通道。页面支持八卡服务器配置，但未证明透明内存一致性或全互联拓扑。" ], "sources": [ "P06" ] }, { "id": "06.network", "type": "prose", "text": [ "The 2025 annual report describes future chip platforms for training, language-model inference, multimodal inference and switching for large models. The switching item belongs in the roadmap, not a shipping AI-NIC or DPU table. No port speeds, SerDes generation or switch capacity are assigned without a named technical disclosure. External NICs and host CPUs remain system dependencies in the documented accelerator portfolio.", "2025 年年报描述未来面向训练、语言模型推理、多模态推理及大模型交换的芯片平台。交换芯片项目应放入路线图，而非已交付 AI NIC 或 DPU 表。缺少具名技术披露时，不赋予端口速率、SerDes 代际或交换容量。在已记录的加速器组合中，外部 NIC 与主机 CPU 仍是系统依赖。" ], "sources": [ "E02" ] }, { "id": "nic", "type": "table", "table": "nic" }, { "id": "links", "type": "table", "table": "links" }, { "id": "system", "type": "table", "table": "system" } ] }, { "id": "07", "title": [ "Terminal IP, edge products and software continuity", "终端 IP、边缘产品与软件延续" ], "blocks": [ { "id": "07.edge", "type": "prose", "text": [ "Cambricon1A, 1H and 1M are licensable terminal processor-IP branches, while Siyuan220/MLU220 supplies edge chips and M.2/SOM modules. An IP core inside another company’s SoC is not a Cambricon-owned complete SoC. These products share software and instruction-family continuity with cloud offerings, but their memory systems, power budgets and host integration differ. The annual report continues to describe cloud, edge and IP activities without publishing a complete new-generation server SKU matrix.", "寒武纪1A、1H 和1M 属于可授权终端处理器 IP 分支，思元220／MLU220 则提供边缘芯片与 M.2／SOM 模组。集成于其他公司 SoC 的 IP 核，不等于寒武纪自有完整 SoC。这些产品与云端方案共享软件和指令家族延续，但存储系统、功耗预算及主机集成方式不同。年报继续描述云端、边缘及 IP 业务，但未公布完整新一代服务器 SKU 矩阵。" ], "sources": [ "E03", "E05", "E02" ] }, { "id": "07.sw", "type": "prose", "text": [ "NeuWare brings drivers, runtime, libraries and tools into a shared platform. CNNL implements neural operators, CNCL supplies collective communication and MagicMind provides an MLIR-based inference compilation path. Training supports data, model and hybrid parallelism. Framework support is a starting point: production readiness also requires operator coverage, numerical correctness, communication overlap, profiling and failure recovery at the intended scale.", "NeuWare 将驱动、运行时、算子库及工具整合为共享平台。CNNL 实现神经网络算子，CNCL 提供集合通信，MagicMind 提供基于 MLIR 的推理编译路径。训练支持数据并行、模型并行及混合并行。框架支持只是起点：生产可用性还需要目标规模下的算子覆盖、数值正确性、通信重叠、性能分析与故障恢复。" ], "sources": [ "P07", "P02" ] }, { "id": "software", "type": "table", "table": "software" }, { "id": "early", "type": "figure", "figure": "early" }, { "id": "later", "type": "figure", "figure": "later" } ] }, { "id": "08", "title": [ "Normalized metrics and deployment implications", "归一化指标与部署含义" ], "blocks": [ { "id": "ratios", "type": "table", "table": "ratios" }, { "id": "08.trend", "type": "prose", "text": [ "The board comparison illustrates why peak performance per watt can mislead: X8 has a lower BF16/TDP ratio than X4 but twice the memory bandwidth and capacity plus direct multi-card communication. A bandwidth-bound or capacity-limited model can therefore favor X8. The correct evaluation includes achievable precision, model fit, host-to-device traffic, inter-card collectives and software versions. Dense floating-point comparisons with other vendors remain conditional where the source does not state the sparsity convention.", "板卡比较说明峰值每瓦性能为何可能误导：X8 的 BF16／TDP 比低于 X4，却拥有两倍内存带宽与容量，并具备直接多卡通信。带宽受限或容量受限模型因此可能更适合 X8。正确评估需涵盖可用精度、模型容纳能力、主机至设备流量、卡间集合通信及软件版本。来源未说明稀疏口径时，与其他厂商的稠密浮点比较仍需保留条件。" ], "sources": [ "P05", "P06" ] } ] }, { "id": "09", "title": [ "Conference index and product mapping", "会议索引与产品映射" ], "blocks": [ { "id": "conference", "type": "table", "table": "conference" }, { "id": "09.limits", "type": "prose", "text": [ "The big-four architecture record is strongest at ISCA, MICRO and ASPLOS. This edition does not establish a direct commercial MLU implementation paper at HPCA, ISSCC or Hot Chips. It also does not treat a same-name academic paper as proof of a commercial design. Recent annual reports describe large-model development and deployment but omit a full named implementation matrix. Accordingly, widely circulated newer model numbers are not assigned speculative process, memory or throughput specifications here; this does not imply that MLU370 is the company’s newest deployed silicon.", "四大架构会议记录以 ISCA、MICRO 和 ASPLOS 最丰富。本版未建立商业 MLU 对应的 HPCA、ISSCC 或 Hot Chips 直接实现论文，也不把同名学术论文当作商业设计证明。近期年报描述大模型研发及部署，但未提供完整具名实现矩阵。因此本报告不为广泛流传的较新型号填入推测工艺、存储或算力；这并不意味着 MLU370 是公司最新部署芯片。" ], "sources": [ "C03", "E02" ] }, { "id": "cross", "type": "table", "table": "cross" } ] } ], "tables": { "gpu": { "id": "gpu", "title": [ "Commercial reference specifications", "商业参考规格" ], "headers": [ [ "Product", "产品" ], [ "Architecture", "架构" ], [ "GA / milestone", "商用／里程碑" ], [ "Status", "状态" ], [ "Process", "工艺" ], [ "Dies / packaging", "裸片／封装" ], [ "Compute units", "计算单元" ], [ "Dense BF16", "稠密 BF16" ], [ "Dense FP8", "稠密 FP8" ], [ "Dense FP6 / FP4", "稠密 FP6／FP4" ], [ "FP64 vector / matrix", "FP64 向量／矩阵" ], [ "Memory: type; stacks; GB; TB/s", "内存：类型；堆栈；GB；TB/s" ], [ "LLC / SRAM", "末级缓存／SRAM" ], [ "Scale-up: links; GB/s per direction; domain", "纵向扩展：链路；单向 GB/s；域" ], [ "Host link", "主机连接" ], [ "Power / cooling", "功耗／散热" ], [ "Form factor", "形态" ] ], "rows": [ { "id": "100", "values": [ [ "Siyuan100 / MLU100", "Siyuan100 / MLU100" ], [ "n/d", "n/d" ], [ "2018", "2018" ], [ "Historical shipping", "历史已商用" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "Cloud accelerator", "云端加速器" ] ], "sources": [ "P01", "E03", "E05" ] }, { "id": "270", "values": [ [ "Siyuan270 / MLU270", "Siyuan270 / MLU270" ], [ "MLUv02", "MLUv02" ], [ "2019", "2019" ], [ "Historical shipping", "历史已商用" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "16 tensor cores", "16 tensor cores" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "Cloud accelerator", "云端加速器" ] ], "sources": [ "P01", "E03", "E05" ] }, { "id": "290", "values": [ [ "Siyuan290 / MLU290-M5", "Siyuan290 / MLU290-M5" ], [ "n/d", "n/d" ], [ "2021 public showcase", "2021 public showcase" ], [ "Historical shipping", "历史已商用" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "Cloud accelerator", "云端加速器" ] ], "sources": [ "P01", "E03", "E05" ] }, { "id": "s", "values": [ [ "MLU370-S4/S8", "MLU370-S4/S8" ], [ "MLUarch03", "MLUarch03" ], [ "2021-2022 product era", "2021-2022 product era" ], [ "Shipping / available", "已商用／可获取" ], [ "7 nm", "7 nm" ], [ "SKU configuration", "SKU configuration" ], [ "n/d", "n/d" ], [ "72 TFLOP/s advertised; dense basis n/d", "72 TFLOP/s advertised; dense basis n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "LPDDR5; 24/48 GB; 307.2 GB/s", "LPDDR5; 24/48 GB; 307.2 GB/s" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "PCIe4 ×16", "PCIe4 ×16" ], [ "75 W; passive", "75 W; passive" ], [ "Half-height / half-length", "Half-height / half-length" ] ], "sources": [ "P04", "P02", "E04" ] }, { "id": "x4", "values": [ [ "MLU370-X4", "MLU370-X4" ], [ "MLUarch03", "MLUarch03" ], [ "2021-2022 product era", "2021-2022 product era" ], [ "Shipping / available", "已商用／可获取" ], [ "7 nm", "7 nm" ], [ "Siyuan370 chip", "Siyuan370 chip" ], [ "n/d", "n/d" ], [ "96 TFLOP/s advertised; dense basis n/d", "96 TFLOP/s advertised; dense basis n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "LPDDR5; 24 GB; 307.2 GB/s", "LPDDR5; 24 GB; 307.2 GB/s" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "PCIe4 ×16", "PCIe4 ×16" ], [ "150 W; passive", "150 W; passive" ], [ "Full-height full-length; 1 slot", "Full-height full-length; 1 slot" ] ], "sources": [ "P05", "P02", "E04" ] }, { "id": "x8", "values": [ [ "MLU370-X8", "MLU370-X8" ], [ "MLUarch03", "MLUarch03" ], [ "2021-2022 product era", "2021-2022 product era" ], [ "Shipping / available", "已商用／可获取" ], [ "7 nm", "7 nm" ], [ "2 Siyuan370 chips", "2 Siyuan370 chips" ], [ "n/d", "n/d" ], [ "96 TFLOP/s advertised; dense basis n/d", "96 TFLOP/s advertised; dense basis n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "LPDDR5; 48 GB; 614.4 GB/s", "LPDDR5; 48 GB; 614.4 GB/s" ], [ "n/d", "n/d" ], [ "4 ports; 100 GB/s one-way aggregate; 8 cards supported", "4 ports; 100 GB/s one-way aggregate; 8 cards supported" ], [ "PCIe4 ×16", "PCIe4 ×16" ], [ "250 W; passive", "250 W; passive" ], [ "Full-height full-length; 2 slots", "Full-height full-length; 2 slots" ] ], "sources": [ "P06", "P02", "E04" ] } ], "panels": [ [ 0, 1, 2, 3, 4, 5 ], [ 0, 6, 7, 8, 9, 10 ], [ 0, 11, 12 ], [ 0, 13, 14, 15, 16 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "cpu": { "id": "cpu", "title": [ "Host CPU boundary", "主机 CPU 边界" ], "headers": [ [ "Generation / reference SKU", "代际／参考 SKU" ], [ "Codename", "代号" ], [ "GA", "正式商用" ], [ "Status", "状态" ], [ "Core µarch", "核心微架构" ], [ "Cores / threads", "核心／线程" ], [ "Process per die", "各裸片工艺" ], [ "Dies / packaging", "裸片／封装" ], [ "L2 per core", "每核 L2" ], [ "L3 / domain", "L3／共享域" ], [ "Memory: channels; rate; GB/s", "内存：通道；速率；GB/s" ], [ "Sockets / links", "插槽／互联" ], [ "PCIe / CXL", "PCIe／CXL" ], [ "TDP", "TDP" ], [ "Vector / matrix ISA", "向量／矩阵 ISA" ] ], "rows": [ { "id": "none", "values": [ [ "No proprietary host CPU established", "未建立自研主机 CPU 产品" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ] ], "sources": [ "E02" ] } ], "panels": [ [ 0, 1, 2, 3, 4, 5 ], [ 0, 6, 7, 8, 9 ], [ 0, 10, 11, 12, 13, 14 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "nic": { "id": "nic", "title": [ "Networking product boundary", "网络产品边界" ], "headers": [ [ "Product", "产品" ], [ "GA / milestone", "商用／里程碑" ], [ "Status", "状态" ], [ "Class", "类别" ], [ "Ports × speed", "端口×速率" ], [ "SerDes", "SerDes" ], [ "Host interface", "主机接口" ], [ "Programmable engine", "可编程引擎" ], [ "Embedded CPU", "嵌入式 CPU" ], [ "On-card memory", "板载内存" ], [ "Transport / RDMA", "传输／RDMA" ], [ "Congestion control", "拥塞控制" ], [ "Key offloads", "主要卸载" ], [ "Power", "功耗" ] ], "rows": [ { "id": "a", "values": [ [ "Large-model switch project", "大模型交换芯片项目" ], [ "2025 annual report", "2025 annual report" ], [ "Roadmap", "路线图" ], [ "Switch R&D", "Switch R&D" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ] ], "sources": [ "E02" ] }, { "id": "b", "values": [ [ "Merchant DPU / AI NIC", "商用 DPU／AI NIC" ], [ "n/a", "n/a" ], [ "No product established", "未建立产品" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ] ], "sources": [ "E02" ] } ], "panels": [ [ 0, 1, 2, 3 ], [ 0, 4, 5, 6, 7 ], [ 0, 8, 9, 10, 11 ], [ 0, 12, 13 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "links": { "id": "links", "title": [ "MLU370-X8 links", "MLU370-X8 链路" ], "headers": [ [ "Interconnect", "互联" ], [ "Year / generation", "年份／代际" ], [ "Lane rate", "通道速率" ], [ "Lanes / link", "每链路通道" ], [ "GB/s per link per direction", "每链路单向 GB/s" ], [ "Links / device", "每设备链路" ], [ "Topology", "拓扑" ], [ "Domain limit", "域规模" ], [ "Coherence / semantics", "一致性／语义" ] ], "rows": [ { "id": "a", "values": [ [ "MLU-Link", "MLU-Link" ], [ "MLU370-X8", "MLU370-X8" ], [ "50 Gb/s", "50 Gb/s" ], [ "16 total as listed", "16 total as listed" ], [ "100 aggregate/device", "100 aggregate/device" ], [ "4 ports", "4 ports" ], [ "n/d", "n/d" ], [ "8-card server supported", "8-card server supported" ], [ "Explicit communication; coherence n/d", "Explicit communication; coherence n/d" ] ], "sources": [ "P06" ] }, { "id": "b", "values": [ [ "Host PCIe", "Host PCIe" ], [ "MLU370", "MLU370" ], [ "16 GT/s", "16 GT/s" ], [ "16", "16" ], [ "~31.5 before packet overhead", "~31.5 before packet overhead" ], [ "1", "1" ], [ "Point-to-point", "Point-to-point" ], [ "Host topology", "Host topology" ], [ "PCIe", "PCIe" ] ], "sources": [ "P05", "P06" ] } ], "panels": [ [ 0, 1, 2, 3, 4 ], [ 0, 5, 6, 7, 8 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "system": { "id": "system", "title": [ "System disclosures", "系统披露" ], "headers": [ [ "Platform", "平台" ], [ "Year / milestone", "年份／里程碑" ], [ "CPU / accelerator count", "CPU／加速器数量" ], [ "Scale-up domain", "纵向扩展域" ], [ "Scale-out per accelerator", "每加速器横向带宽" ], [ "Rack power", "机架功耗" ], [ "Cooling", "散热" ] ], "rows": [ { "id": "a", "values": [ [ "XuanSi1000 / MLU-X1000", "XuanSi1000 / MLU-X1000" ], [ "WAIC2021", "WAIC2021" ], [ "MLU290; count n/d", "MLU290; count n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ] ], "sources": [ "E03" ] }, { "id": "b", "values": [ [ "MLU370-X8 server", "MLU370-X8 server" ], [ "Product documentation", "Product documentation" ], [ "Up to 8 cards", "Up to 8 cards" ], [ "Topology n/d", "Topology n/d" ], [ "External NIC; n/d", "External NIC; n/d" ], [ "n/d", "n/d" ], [ "Passive boards; server airflow", "Passive boards; server airflow" ] ], "sources": [ "P06" ] } ], "panels": [ [ 0, 1, 2, 3 ], [ 0, 4, 5, 6 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "software": { "id": "software", "title": [ "Software contracts", "软件契约" ], "headers": [ [ "Layer", "层" ], [ "Product", "产品" ], [ "Function", "功能" ], [ "Scope", "范围" ] ], "rows": [ { "id": "a", "values": [ [ "Platform", "平台" ], [ "NeuWare", "NeuWare" ], [ "Driver / runtime / tools", "驱动／运行时／工具" ], [ "Cloud / edge / terminal", "云／边／端" ] ], "sources": [ "P07" ] }, { "id": "b", "values": [ [ "Operators", "算子" ], [ "CNNL / BANG", "CNNL / BANG" ], [ "Libraries and kernel programming", "算子库与内核编程" ], [ "Device-specific tuning", "设备相关调优" ] ], "sources": [ "P07", "P01" ] }, { "id": "c", "values": [ [ "Communication", "通信" ], [ "CNCL", "CNCL" ], [ "Distributed collectives", "分布式集合通信" ], [ "Topology and configuration dependent", "依赖拓扑与配置" ] ], "sources": [ "P07", "P06" ] }, { "id": "d", "values": [ [ "Inference", "推理" ], [ "MagicMind / MLIR", "MagicMind / MLIR" ], [ "Graph compilation and optimization", "图编译与优化" ], [ "Model and operator coverage dependent", "依赖模型及算子覆盖" ] ], "sources": [ "P02", "P07" ] } ], "panels": [ [ 0, 1, 2, 3 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "ratios": { "id": "ratios", "title": [ "Board-level balance", "板级平衡" ], "headers": [ [ "Metric", "指标" ], [ "Calculation", "计算" ], [ "Basis", "口径" ] ], "rows": [ { "id": "a", "values": [ [ "X4 DRAM/BF16", "X4 DRAM/BF16" ], [ "307.2e9/96e12 = 0.0032 B/FLOP", "307.2e9/96e12 = 0.0032 B/FLOP" ], [ "Advertised peak; sparsity basis unstated", "公布峰值；稀疏口径未明示" ] ], "sources": [ "P05" ] }, { "id": "b", "values": [ [ "X8 DRAM/BF16", "X8 DRAM/BF16" ], [ "614.4e9/96e12 = 0.0064 B/FLOP", "614.4e9/96e12 = 0.0064 B/FLOP" ], [ "Board-wide; not per chiplet", "整板；非每小芯片" ] ], "sources": [ "P06" ] }, { "id": "c", "values": [ [ "X8 capacity/BF16", "X8 capacity/BF16" ], [ "48e9/96e12 = 5e-4 B·s/FLOP", "48e9/96e12 = 5e-4 B·s/FLOP" ], [ "LPDDR, not HBM", "LPDDR，非 HBM" ] ], "sources": [ "P06" ] }, { "id": "d", "values": [ [ "X8 MLU-Link/DRAM", "X8 MLU-Link/DRAM" ], [ "100/614.4 = 0.163", "100/614.4 = 0.163" ], [ "One-way aggregate link rate", "单向聚合链路速率" ] ], "sources": [ "P06" ] }, { "id": "e", "values": [ [ "X4 vs X8 BF16/TDP", "X4 vs X8 BF16/TDP" ], [ "96/150=0.64; 96/250=0.384 TFLOP/s/W", "96/150=0.64; 96/250=0.384 TFLOP/s/W" ], [ "Peak/TDP proxy; workload benefit differs", "峰值／TDP 代理量；负载收益不同" ] ], "sources": [ "P05", "P06" ] }, { "id": "f", "values": [ [ "HBM/FLOP; host DDR/core; L3/core", "HBM/FLOP; host DDR/core; L3/core" ], [ "n/d / n/a", "n/d / n/a" ], [ "No matched published data or own host CPU", "缺匹配公开数据或自有主机 CPU" ] ], "sources": [ "E02" ] } ], "panels": [ [ 0, 1, 2 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "conference": { "id": "conference", "title": [ "Verified disclosure lineage", "已核实披露谱系" ], "headers": [ [ "Venue", "会议／活动" ], [ "Year", "年份" ], [ "Paper / talk / disclosure", "论文／演讲／披露" ], [ "Presenter / authors", "报告人／作者" ], [ "Product", "产品" ], [ "Evidence type", "证据类型" ], [ "Source", "来源" ] ], "rows": [ { "id": "d", "values": [ [ "ASPLOS / MICRO", "ASPLOS / MICRO" ], [ "2014", "2014" ], [ "DianNao / DaDianNao", "DianNao / DaDianNao" ], [ "Paper authors / company", "论文作者／公司" ], [ "Research baseline", "Research baseline" ], [ "Research record", "研究记录" ], [ "C01 C03", "C01 C03" ] ], "sources": [ "C01", "C03" ] }, { "id": "p", "values": [ [ "ASPLOS", "ASPLOS" ], [ "2015", "2015" ], [ "PuDianNao", "PuDianNao" ], [ "Paper authors / company", "论文作者／公司" ], [ "Research", "Research" ], [ "Research record", "研究记录" ], [ "C03", "C03" ] ], "sources": [ "C03" ] }, { "id": "s", "values": [ [ "ISCA", "ISCA" ], [ "2015", "2015" ], [ "ShiDianNao", "ShiDianNao" ], [ "Paper authors / company", "论文作者／公司" ], [ "Research", "Research" ], [ "Research record", "研究记录" ], [ "C03", "C03" ] ], "sources": [ "C03" ] }, { "id": "i", "values": [ [ "ISCA", "ISCA" ], [ "2016", "2016" ], [ "Cambricon ISA", "Cambricon ISA" ], [ "Paper authors / company", "论文作者／公司" ], [ "Research ISA", "Research ISA" ], [ "Research record", "研究记录" ], [ "C02", "C02" ] ], "sources": [ "C02" ] }, { "id": "x", "values": [ [ "MICRO", "MICRO" ], [ "2016", "2016" ], [ "Cambricon-X", "Cambricon-X" ], [ "Paper authors / company", "论文作者／公司" ], [ "Research sparsity", "Research sparsity" ], [ "Research record", "研究记录" ], [ "C03", "C03" ] ], "sources": [ "C03" ] }, { "id": "ss", "values": [ [ "MICRO", "MICRO" ], [ "2018", "2018" ], [ "Cambricon-S", "Cambricon-S" ], [ "Paper authors / company", "论文作者／公司" ], [ "Research sparsity", "Research sparsity" ], [ "Research record", "研究记录" ], [ "C03", "C03" ] ], "sources": [ "C03" ] }, { "id": "f", "values": [ [ "ISCA", "ISCA" ], [ "2019", "2019" ], [ "Cambricon-F", "Cambricon-F" ], [ "Paper authors / company", "论文作者／公司" ], [ "Research programming architecture", "Research programming architecture" ], [ "Research record", "研究记录" ], [ "C04", "C04" ] ], "sources": [ "C04" ] }, { "id": "q", "values": [ [ "ISCA", "ISCA" ], [ "2021", "2021" ], [ "Cambricon-Q", "Cambricon-Q" ], [ "Paper authors / company", "论文作者／公司" ], [ "Research training", "Research training" ], [ "Research record", "研究记录" ], [ "C03", "C03" ] ], "sources": [ "C03" ] }, { "id": "w", "values": [ [ "WAIC", "WAIC" ], [ "2021-2022", "2021-2022" ], [ "Cloud/edge product exhibitions", "Cloud/edge product exhibitions" ], [ "Paper authors / company", "论文作者／公司" ], [ "MLU220/270/290/370", "MLU220/270/290/370" ], [ "Product showcase", "产品展示" ], [ "E03 E04", "E03 E04" ] ], "sources": [ "E03", "E04" ] } ], "panels": [ [ 0, 1, 2 ], [ 0, 3, 4, 5, 6 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "cross": { "id": "cross", "title": [ "Naming boundaries", "命名边界" ], "headers": [ [ "Name", "名称" ], [ "Meaning", "含义" ], [ "Boundary", "边界" ] ], "rows": [ { "id": "a", "values": [ [ "DianNao family", "DianNao family" ], [ "Academic designs", "学术设计" ], [ "Not commercial MLU SKUs", "不是商业 MLU SKU" ] ], "sources": [ "C03" ] }, { "id": "b", "values": [ [ "Siyuan / MLU", "Siyuan / MLU" ], [ "Chip and board families", "芯片及板卡家族" ], [ "Always specify board suffix", "始终注明板卡后缀" ] ], "sources": [ "P02", "P06" ] }, { "id": "c", "values": [ [ "MLU370 chiplet / X8 dual-chip", "MLU370 chiplet / X8 dual-chip" ], [ "Package / board integration", "封装／板级集成" ], [ "Different counting levels", "不同计数层级" ] ], "sources": [ "P02", "P06" ] }, { "id": "d", "values": [ [ "MLU-Link / CNCL", "MLU-Link / CNCL" ], [ "Hardware links / collective library", "硬件链路／集合通信库" ], [ "Bandwidth versus software behavior", "带宽与软件行为不同" ] ], "sources": [ "P06", "P07" ] } ], "panels": [ [ 0, 1, 2 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" } }, "figures": { "early": { "id": "early", "title": [ "2018-2020 stack", "2018-2020 技术栈" ], "nodes": [ [ "cpu", [ "External host CPU", "外部主机 CPU" ], 0, 0 ], [ "gpu", [ "MLU100 / MLU270", "MLU100 / MLU270" ], 0, 1 ], [ "mem", [ "Board memory / on-chip NoC", "Board memory / on-chip NoC" ], 0, 2 ], [ "sw", [ "NeuWare / framework", "NeuWare／框架" ], 1, 0 ], [ "net", [ "External NIC / network", "外部 NIC／网络" ], 1, 1 ], [ "rt", [ "CNCL / runtime", "CNCL／运行时" ], 1, 2 ] ], "edges": [ [ "cpu", "gpu", [ "PCIe", "PCIe" ] ], [ "gpu", "mem", [ "data path", "数据路径" ] ], [ "gpu", "net", [ "system I/O", "系统 I/O" ] ], [ "net", "rt", [ "collectives", "集合通信" ] ] ], "caption": [ "Functional stack; MLU290 and MLU370 are separate branches, not one combined configuration.", "功能技术栈；MLU290 与 MLU370 是不同分支，不是组合配置。" ] }, "later": { "id": "later", "title": [ "2021-2026 disclosures stack", "2021-2026 disclosures 技术栈" ], "nodes": [ [ "cpu", [ "External host CPU", "外部主机 CPU" ], 0, 0 ], [ "gpu", [ "MLU290 / MLU370", "MLU290 / MLU370" ], 0, 1 ], [ "mem", [ "LPDDR5 / MLU-Link", "LPDDR5 / MLU-Link" ], 0, 2 ], [ "sw", [ "NeuWare / framework", "NeuWare／框架" ], 1, 0 ], [ "net", [ "External NIC / network", "外部 NIC／网络" ], 1, 1 ], [ "rt", [ "CNCL / runtime", "CNCL／运行时" ], 1, 2 ] ], "edges": [ [ "cpu", "gpu", [ "PCIe", "PCIe" ] ], [ "gpu", "mem", [ "data path", "数据路径" ] ], [ "gpu", "net", [ "system I/O", "系统 I/O" ] ], [ "net", "rt", [ "collectives", "集合通信" ] ] ], "caption": [ "Functional stack; MLU290 and MLU370 are separate branches, not one combined configuration.", "功能技术栈；MLU290 与 MLU370 是不同分支，不是组合配置。" ] } }, "claims": { "gpu.100.0": { "value": "Siyuan100 / MLU100", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2018", "status": "historical", "scope": "100" }, "gpu.100.1": { "value": "n/d", "field": "Architecture", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2018", "status": "historical", "scope": "100" }, "gpu.100.2": { "value": "2018", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2018", "status": "historical", "scope": "100" }, "gpu.100.3": { "value": "Historical shipping", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2018", "status": "historical", "scope": "100" }, "gpu.100.4": { "value": "n/d", "field": "Process", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2018", "status": "historical", "scope": "100" }, "gpu.100.5": { "value": "n/d", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2018", "status": "historical", "scope": "100" }, "gpu.100.6": { "value": "n/d", "field": "Compute units", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2018", "status": "historical", "scope": "100" }, "gpu.100.7": { "value": "n/d", "field": "Dense BF16", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2018", "status": "historical", "scope": "100" }, "gpu.100.8": { "value": "n/d", "field": "Dense FP8", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2018", "status": "historical", "scope": "100" }, "gpu.100.9": { "value": "n/d", "field": "Dense FP6 / FP4", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2018", "status": "historical", "scope": "100" }, "gpu.100.10": { "value": "n/d", "field": "FP64 vector / matrix", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2018", "status": "historical", "scope": "100" }, "gpu.100.11": { "value": "n/d", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2018", "status": "historical", "scope": "100" }, "gpu.100.12": { "value": "n/d", "field": "LLC / SRAM", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2018", "status": "historical", "scope": "100" }, "gpu.100.13": { "value": "n/d", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2018", "status": "historical", "scope": "100" }, "gpu.100.14": { "value": "n/d", "field": "Host link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2018", "status": "historical", "scope": "100" }, "gpu.100.15": { "value": "n/d", "field": "Power / cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2018", "status": "historical", "scope": "100" }, "gpu.100.16": { "value": "Cloud accelerator", "field": "Form factor", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2018", "status": "historical", "scope": "100" }, "gpu.270.0": { "value": "Siyuan270 / MLU270", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2019", "status": "historical", "scope": "270" }, "gpu.270.1": { "value": "MLUv02", "field": "Architecture", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2019", "status": "historical", "scope": "270" }, "gpu.270.2": { "value": "2019", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2019", "status": "historical", "scope": "270" }, "gpu.270.3": { "value": "Historical shipping", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2019", "status": "historical", "scope": "270" }, "gpu.270.4": { "value": "n/d", "field": "Process", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2019", "status": "historical", "scope": "270" }, "gpu.270.5": { "value": "n/d", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2019", "status": "historical", "scope": "270" }, "gpu.270.6": { "value": "16 tensor cores", "field": "Compute units", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2019", "status": "historical", "scope": "270" }, "gpu.270.7": { "value": "n/d", "field": "Dense BF16", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2019", "status": "historical", "scope": "270" }, "gpu.270.8": { "value": "n/d", "field": "Dense FP8", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2019", "status": "historical", "scope": "270" }, "gpu.270.9": { "value": "n/d", "field": "Dense FP6 / FP4", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2019", "status": "historical", "scope": "270" }, "gpu.270.10": { "value": "n/d", "field": "FP64 vector / matrix", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2019", "status": "historical", "scope": "270" }, "gpu.270.11": { "value": "n/d", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2019", "status": "historical", "scope": "270" }, "gpu.270.12": { "value": "n/d", "field": "LLC / SRAM", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2019", "status": "historical", "scope": "270" }, "gpu.270.13": { "value": "n/d", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2019", "status": "historical", "scope": "270" }, "gpu.270.14": { "value": "n/d", "field": "Host link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2019", "status": "historical", "scope": "270" }, "gpu.270.15": { "value": "n/d", "field": "Power / cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2019", "status": "historical", "scope": "270" }, "gpu.270.16": { "value": "Cloud accelerator", "field": "Form factor", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2019", "status": "historical", "scope": "270" }, "gpu.290.0": { "value": "Siyuan290 / MLU290-M5", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2021 public showcase", "status": "historical", "scope": "290" }, "gpu.290.1": { "value": "n/d", "field": "Architecture", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2021 public showcase", "status": "historical", "scope": "290" }, "gpu.290.2": { "value": "2021 public showcase", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2021 public showcase", "status": "historical", "scope": "290" }, "gpu.290.3": { "value": "Historical shipping", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2021 public showcase", "status": "historical", "scope": "290" }, "gpu.290.4": { "value": "n/d", "field": "Process", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2021 public showcase", "status": "historical", "scope": "290" }, "gpu.290.5": { "value": "n/d", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2021 public showcase", "status": "historical", "scope": "290" }, "gpu.290.6": { "value": "n/d", "field": "Compute units", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2021 public showcase", "status": "historical", "scope": "290" }, "gpu.290.7": { "value": "n/d", "field": "Dense BF16", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2021 public showcase", "status": "historical", "scope": "290" }, "gpu.290.8": { "value": "n/d", "field": "Dense FP8", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2021 public showcase", "status": "historical", "scope": "290" }, "gpu.290.9": { "value": "n/d", "field": "Dense FP6 / FP4", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2021 public showcase", "status": "historical", "scope": "290" }, "gpu.290.10": { "value": "n/d", "field": "FP64 vector / matrix", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2021 public showcase", "status": "historical", "scope": "290" }, "gpu.290.11": { "value": "n/d", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2021 public showcase", "status": "historical", "scope": "290" }, "gpu.290.12": { "value": "n/d", "field": "LLC / SRAM", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2021 public showcase", "status": "historical", "scope": "290" }, "gpu.290.13": { "value": "n/d", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2021 public showcase", "status": "historical", "scope": "290" }, "gpu.290.14": { "value": "n/d", "field": "Host link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2021 public showcase", "status": "historical", "scope": "290" }, "gpu.290.15": { "value": "n/d", "field": "Power / cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2021 public showcase", "status": "historical", "scope": "290" }, "gpu.290.16": { "value": "Cloud accelerator", "field": "Form factor", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E03", "E05" ], "disclosure_date": "2021 public showcase", "status": "historical", "scope": "290" }, "gpu.s.0": { "value": "MLU370-S4/S8", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "s" }, "gpu.s.1": { "value": "MLUarch03", "field": "Architecture", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "s" }, "gpu.s.2": { "value": "2021-2022 product era", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "s" }, "gpu.s.3": { "value": "Shipping / available", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "s" }, "gpu.s.4": { "value": "7 nm", "field": "Process", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "s" }, "gpu.s.5": { "value": "SKU configuration", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "s" }, "gpu.s.6": { "value": "n/d", "field": "Compute units", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "s" }, "gpu.s.7": { "value": "72 TFLOP/s advertised; dense basis n/d", "field": "Dense BF16", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "s" }, "gpu.s.8": { "value": "n/d", "field": "Dense FP8", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "s" }, "gpu.s.9": { "value": "n/d", "field": "Dense FP6 / FP4", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "s" }, "gpu.s.10": { "value": "n/d", "field": "FP64 vector / matrix", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "s" }, "gpu.s.11": { "value": "LPDDR5; 24/48 GB; 307.2 GB/s", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "s" }, "gpu.s.12": { "value": "n/d", "field": "LLC / SRAM", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "s" }, "gpu.s.13": { "value": "n/d", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "s" }, "gpu.s.14": { "value": "PCIe4 ×16", "field": "Host link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "s" }, "gpu.s.15": { "value": "75 W; passive", "field": "Power / cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "s" }, "gpu.s.16": { "value": "Half-height / half-length", "field": "Form factor", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "s" }, "gpu.x4.0": { "value": "MLU370-X4", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x4" }, "gpu.x4.1": { "value": "MLUarch03", "field": "Architecture", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x4" }, "gpu.x4.2": { "value": "2021-2022 product era", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x4" }, "gpu.x4.3": { "value": "Shipping / available", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x4" }, "gpu.x4.4": { "value": "7 nm", "field": "Process", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x4" }, "gpu.x4.5": { "value": "Siyuan370 chip", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x4" }, "gpu.x4.6": { "value": "n/d", "field": "Compute units", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x4" }, "gpu.x4.7": { "value": "96 TFLOP/s advertised; dense basis n/d", "field": "Dense BF16", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x4" }, "gpu.x4.8": { "value": "n/d", "field": "Dense FP8", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x4" }, "gpu.x4.9": { "value": "n/d", "field": "Dense FP6 / FP4", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x4" }, "gpu.x4.10": { "value": "n/d", "field": "FP64 vector / matrix", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x4" }, "gpu.x4.11": { "value": "LPDDR5; 24 GB; 307.2 GB/s", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x4" }, "gpu.x4.12": { "value": "n/d", "field": "LLC / SRAM", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x4" }, "gpu.x4.13": { "value": "n/d", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x4" }, "gpu.x4.14": { "value": "PCIe4 ×16", "field": "Host link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x4" }, "gpu.x4.15": { "value": "150 W; passive", "field": "Power / cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x4" }, "gpu.x4.16": { "value": "Full-height full-length; 1 slot", "field": "Form factor", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x4" }, "gpu.x8.0": { "value": "MLU370-X8", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x8" }, "gpu.x8.1": { "value": "MLUarch03", "field": "Architecture", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x8" }, "gpu.x8.2": { "value": "2021-2022 product era", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x8" }, "gpu.x8.3": { "value": "Shipping / available", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x8" }, "gpu.x8.4": { "value": "7 nm", "field": "Process", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x8" }, "gpu.x8.5": { "value": "2 Siyuan370 chips", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x8" }, "gpu.x8.6": { "value": "n/d", "field": "Compute units", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x8" }, "gpu.x8.7": { "value": "96 TFLOP/s advertised; dense basis n/d", "field": "Dense BF16", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x8" }, "gpu.x8.8": { "value": "n/d", "field": "Dense FP8", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x8" }, "gpu.x8.9": { "value": "n/d", "field": "Dense FP6 / FP4", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x8" }, "gpu.x8.10": { "value": "n/d", "field": "FP64 vector / matrix", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x8" }, "gpu.x8.11": { "value": "LPDDR5; 48 GB; 614.4 GB/s", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x8" }, "gpu.x8.12": { "value": "n/d", "field": "LLC / SRAM", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x8" }, "gpu.x8.13": { "value": "4 ports; 100 GB/s one-way aggregate; 8 cards supported", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x8" }, "gpu.x8.14": { "value": "PCIe4 ×16", "field": "Host link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x8" }, "gpu.x8.15": { "value": "250 W; passive", "field": "Power / cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x8" }, "gpu.x8.16": { "value": "Full-height full-length; 2 slots", "field": "Form factor", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P02", "E04" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "x8" }, "cpu.none.0": { "value": "No proprietary host CPU established", "field": "Generation / reference SKU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "none" }, "cpu.none.1": { "value": "n/a", "field": "Codename", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "none" }, "cpu.none.2": { "value": "n/a", "field": "GA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "none" }, "cpu.none.3": { "value": "n/a", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "none" }, "cpu.none.4": { "value": "n/a", "field": "Core µarch", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "none" }, "cpu.none.5": { "value": "n/a", "field": "Cores / threads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "none" }, "cpu.none.6": { "value": "n/a", "field": "Process per die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "none" }, "cpu.none.7": { "value": "n/a", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "none" }, "cpu.none.8": { "value": "n/a", "field": "L2 per core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "none" }, "cpu.none.9": { "value": "n/a", "field": "L3 / domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "none" }, "cpu.none.10": { "value": "n/a", "field": "Memory: channels; rate; GB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "none" }, "cpu.none.11": { "value": "n/a", "field": "Sockets / links", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "none" }, "cpu.none.12": { "value": "n/a", "field": "PCIe / CXL", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "none" }, "cpu.none.13": { "value": "n/a", "field": "TDP", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "none" }, "cpu.none.14": { "value": "n/a", "field": "Vector / matrix ISA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "none" }, "nic.a.0": { "value": "Large-model switch project", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "roadmap", "scope": "a" }, "nic.a.1": { "value": "2025 annual report", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "roadmap", "scope": "a" }, "nic.a.2": { "value": "Roadmap", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "roadmap", "scope": "a" }, "nic.a.3": { "value": "Switch R&D", "field": "Class", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "roadmap", "scope": "a" }, "nic.a.4": { "value": "n/d", "field": "Ports × speed", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "roadmap", "scope": "a" }, "nic.a.5": { "value": "n/d", "field": "SerDes", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "roadmap", "scope": "a" }, "nic.a.6": { "value": "n/d", "field": "Host interface", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "roadmap", "scope": "a" }, "nic.a.7": { "value": "n/d", "field": "Programmable engine", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "roadmap", "scope": "a" }, "nic.a.8": { "value": "n/d", "field": "Embedded CPU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "roadmap", "scope": "a" }, "nic.a.9": { "value": "n/d", "field": "On-card memory", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "roadmap", "scope": "a" }, "nic.a.10": { "value": "n/d", "field": "Transport / RDMA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "roadmap", "scope": "a" }, "nic.a.11": { "value": "n/d", "field": "Congestion control", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "roadmap", "scope": "a" }, "nic.a.12": { "value": "n/d", "field": "Key offloads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "roadmap", "scope": "a" }, "nic.a.13": { "value": "n/d", "field": "Power", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "roadmap", "scope": "a" }, "nic.b.0": { "value": "Merchant DPU / AI NIC", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "b" }, "nic.b.1": { "value": "n/a", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "b" }, "nic.b.2": { "value": "No product established", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "b" }, "nic.b.3": { "value": "n/a", "field": "Class", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "b" }, "nic.b.4": { "value": "n/a", "field": "Ports × speed", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "b" }, "nic.b.5": { "value": "n/a", "field": "SerDes", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "b" }, "nic.b.6": { "value": "n/a", "field": "Host interface", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "b" }, "nic.b.7": { "value": "n/a", "field": "Programmable engine", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "b" }, "nic.b.8": { "value": "n/a", "field": "Embedded CPU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "b" }, "nic.b.9": { "value": "n/a", "field": "On-card memory", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "b" }, "nic.b.10": { "value": "n/a", "field": "Transport / RDMA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "b" }, "nic.b.11": { "value": "n/a", "field": "Congestion control", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "b" }, "nic.b.12": { "value": "n/a", "field": "Key offloads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "b" }, "nic.b.13": { "value": "n/a", "field": "Power", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "not_applicable", "scope": "b" }, "links.a.0": { "value": "MLU-Link", "field": "Interconnect", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "a" }, "links.a.1": { "value": "MLU370-X8", "field": "Year / generation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "a" }, "links.a.2": { "value": "50 Gb/s", "field": "Lane rate", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "a" }, "links.a.3": { "value": "16 total as listed", "field": "Lanes / link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "a" }, "links.a.4": { "value": "100 aggregate/device", "field": "GB/s per link per direction", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "a" }, "links.a.5": { "value": "4 ports", "field": "Links / device", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "a" }, "links.a.6": { "value": "n/d", "field": "Topology", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "a" }, "links.a.7": { "value": "8-card server supported", "field": "Domain limit", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "a" }, "links.a.8": { "value": "Explicit communication; coherence n/d", "field": "Coherence / semantics", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "a" }, "links.b.0": { "value": "Host PCIe", "field": "Interconnect", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "b" }, "links.b.1": { "value": "MLU370", "field": "Year / generation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "b" }, "links.b.2": { "value": "16 GT/s", "field": "Lane rate", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "b" }, "links.b.3": { "value": "16", "field": "Lanes / link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "b" }, "links.b.4": { "value": "~31.5 before packet overhead", "field": "GB/s per link per direction", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "b" }, "links.b.5": { "value": "1", "field": "Links / device", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "b" }, "links.b.6": { "value": "Point-to-point", "field": "Topology", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "b" }, "links.b.7": { "value": "Host topology", "field": "Domain limit", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "b" }, "links.b.8": { "value": "PCIe", "field": "Coherence / semantics", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "b" }, "system.a.0": { "value": "XuanSi1000 / MLU-X1000", "field": "Platform", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2021", "status": "showcased", "scope": "a" }, "system.a.1": { "value": "WAIC2021", "field": "Year / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2021", "status": "showcased", "scope": "a" }, "system.a.2": { "value": "MLU290; count n/d", "field": "CPU / accelerator count", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2021", "status": "showcased", "scope": "a" }, "system.a.3": { "value": "n/d", "field": "Scale-up domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2021", "status": "showcased", "scope": "a" }, "system.a.4": { "value": "n/d", "field": "Scale-out per accelerator", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2021", "status": "showcased", "scope": "a" }, "system.a.5": { "value": "n/d", "field": "Rack power", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2021", "status": "showcased", "scope": "a" }, "system.a.6": { "value": "n/d", "field": "Cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2021", "status": "showcased", "scope": "a" }, "system.b.0": { "value": "MLU370-X8 server", "field": "Platform", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "b" }, "system.b.1": { "value": "Product documentation", "field": "Year / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "b" }, "system.b.2": { "value": "Up to 8 cards", "field": "CPU / accelerator count", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "b" }, "system.b.3": { "value": "Topology n/d", "field": "Scale-up domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "b" }, "system.b.4": { "value": "External NIC; n/d", "field": "Scale-out per accelerator", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "b" }, "system.b.5": { "value": "n/d", "field": "Rack power", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "b" }, "system.b.6": { "value": "Passive boards; server airflow", "field": "Cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "b" }, "software.a.0": { "value": "Platform", "field": "Layer", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "a" }, "software.a.1": { "value": "NeuWare", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "a" }, "software.a.2": { "value": "Driver / runtime / tools", "field": "Function", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "a" }, "software.a.3": { "value": "Cloud / edge / terminal", "field": "Scope", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "a" }, "software.b.0": { "value": "Operators", "field": "Layer", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "P01" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "b" }, "software.b.1": { "value": "CNNL / BANG", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "P01" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "b" }, "software.b.2": { "value": "Libraries and kernel programming", "field": "Function", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "P01" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "b" }, "software.b.3": { "value": "Device-specific tuning", "field": "Scope", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "P01" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "b" }, "software.c.0": { "value": "Communication", "field": "Layer", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "c" }, "software.c.1": { "value": "CNCL", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "c" }, "software.c.2": { "value": "Distributed collectives", "field": "Function", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "c" }, "software.c.3": { "value": "Topology and configuration dependent", "field": "Scope", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "P06" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "c" }, "software.d.0": { "value": "Inference", "field": "Layer", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P02", "P07" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "d" }, "software.d.1": { "value": "MagicMind / MLIR", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P02", "P07" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "d" }, "software.d.2": { "value": "Graph compilation and optimization", "field": "Function", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P02", "P07" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "d" }, "software.d.3": { "value": "Model and operator coverage dependent", "field": "Scope", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P02", "P07" ], "disclosure_date": "2026-09-28", "status": "available", "scope": "d" }, "ratios.a.0": { "value": "X4 DRAM/BF16", "field": "Metric", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05" ], "disclosure_date": "2026-09-28", "status": "derived", "scope": "a" }, "ratios.a.1": { "value": "307.2e9/96e12 = 0.0032 B/FLOP", "field": "Calculation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05" ], "disclosure_date": "2026-09-28", "status": "derived", "scope": "a" }, "ratios.a.2": { "value": "Advertised peak; sparsity basis unstated", "field": "Basis", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05" ], "disclosure_date": "2026-09-28", "status": "derived", "scope": "a" }, "ratios.b.0": { "value": "X8 DRAM/BF16", "field": "Metric", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06" ], "disclosure_date": "2026-09-28", "status": "derived", "scope": "b" }, "ratios.b.1": { "value": "614.4e9/96e12 = 0.0064 B/FLOP", "field": "Calculation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06" ], "disclosure_date": "2026-09-28", "status": "derived", "scope": "b" }, "ratios.b.2": { "value": "Board-wide; not per chiplet", "field": "Basis", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06" ], "disclosure_date": "2026-09-28", "status": "derived", "scope": "b" }, "ratios.c.0": { "value": "X8 capacity/BF16", "field": "Metric", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06" ], "disclosure_date": "2026-09-28", "status": "derived", "scope": "c" }, "ratios.c.1": { "value": "48e9/96e12 = 5e-4 B·s/FLOP", "field": "Calculation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06" ], "disclosure_date": "2026-09-28", "status": "derived", "scope": "c" }, "ratios.c.2": { "value": "LPDDR, not HBM", "field": "Basis", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06" ], "disclosure_date": "2026-09-28", "status": "derived", "scope": "c" }, "ratios.d.0": { "value": "X8 MLU-Link/DRAM", "field": "Metric", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06" ], "disclosure_date": "2026-09-28", "status": "derived", "scope": "d" }, "ratios.d.1": { "value": "100/614.4 = 0.163", "field": "Calculation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06" ], "disclosure_date": "2026-09-28", "status": "derived", "scope": "d" }, "ratios.d.2": { "value": "One-way aggregate link rate", "field": "Basis", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06" ], "disclosure_date": "2026-09-28", "status": "derived", "scope": "d" }, "ratios.e.0": { "value": "X4 vs X8 BF16/TDP", "field": "Metric", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P06" ], "disclosure_date": "2026-09-28", "status": "derived", "scope": "e" }, "ratios.e.1": { "value": "96/150=0.64; 96/250=0.384 TFLOP/s/W", "field": "Calculation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P06" ], "disclosure_date": "2026-09-28", "status": "derived", "scope": "e" }, "ratios.e.2": { "value": "Peak/TDP proxy; workload benefit differs", "field": "Basis", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P05", "P06" ], "disclosure_date": "2026-09-28", "status": "derived", "scope": "e" }, "ratios.f.0": { "value": "HBM/FLOP; host DDR/core; L3/core", "field": "Metric", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "unknown", "scope": "f" }, "ratios.f.1": { "value": "n/d / n/a", "field": "Calculation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "unknown", "scope": "f" }, "ratios.f.2": { "value": "No matched published data or own host CPU", "field": "Basis", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E02" ], "disclosure_date": "2026-09-28", "status": "unknown", "scope": "f" }, "conference.d.0": { "value": "ASPLOS / MICRO", "field": "Venue", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "C03" ], "disclosure_date": "2014", "status": "published", "scope": "d" }, "conference.d.1": { "value": "2014", "field": "Year", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "C03" ], "disclosure_date": "2014", "status": "published", "scope": "d" }, "conference.d.2": { "value": "DianNao / DaDianNao", "field": "Paper / talk / disclosure", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "C03" ], "disclosure_date": "2014", "status": "published", "scope": "d" }, "conference.d.3": { "value": "Paper authors / company", "field": "Presenter / authors", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "C03" ], "disclosure_date": "2014", "status": "published", "scope": "d" }, "conference.d.4": { "value": "Research baseline", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "C03" ], "disclosure_date": "2014", "status": "published", "scope": "d" }, "conference.d.5": { "value": "Research record", "field": "Evidence type", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "C03" ], "disclosure_date": "2014", "status": "published", "scope": "d" }, "conference.d.6": { "value": "C01 C03", "field": "Source", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01", "C03" ], "disclosure_date": "2014", "status": "published", "scope": "d" }, "conference.p.0": { "value": "ASPLOS", "field": "Venue", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2015", "status": "published", "scope": "p" }, "conference.p.1": { "value": "2015", "field": "Year", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2015", "status": "published", "scope": "p" }, "conference.p.2": { "value": "PuDianNao", "field": "Paper / talk / disclosure", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2015", "status": "published", "scope": "p" }, "conference.p.3": { "value": "Paper authors / company", "field": "Presenter / authors", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2015", "status": "published", "scope": "p" }, "conference.p.4": { "value": "Research", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2015", "status": "published", "scope": "p" }, "conference.p.5": { "value": "Research record", "field": "Evidence type", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2015", "status": "published", "scope": "p" }, "conference.p.6": { "value": "C03", "field": "Source", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2015", "status": "published", "scope": "p" }, "conference.s.0": { "value": "ISCA", "field": "Venue", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2015", "status": "published", "scope": "s" }, "conference.s.1": { "value": "2015", "field": "Year", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2015", "status": "published", "scope": "s" }, "conference.s.2": { "value": "ShiDianNao", "field": "Paper / talk / disclosure", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2015", "status": "published", "scope": "s" }, "conference.s.3": { "value": "Paper authors / company", "field": "Presenter / authors", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2015", "status": "published", "scope": "s" }, "conference.s.4": { "value": "Research", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2015", "status": "published", "scope": "s" }, "conference.s.5": { "value": "Research record", "field": "Evidence type", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2015", "status": "published", "scope": "s" }, "conference.s.6": { "value": "C03", "field": "Source", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2015", "status": "published", "scope": "s" }, "conference.i.0": { "value": "ISCA", "field": "Venue", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2016", "status": "published", "scope": "i" }, "conference.i.1": { "value": "2016", "field": "Year", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2016", "status": "published", "scope": "i" }, "conference.i.2": { "value": "Cambricon ISA", "field": "Paper / talk / disclosure", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2016", "status": "published", "scope": "i" }, "conference.i.3": { "value": "Paper authors / company", "field": "Presenter / authors", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2016", "status": "published", "scope": "i" }, "conference.i.4": { "value": "Research ISA", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2016", "status": "published", "scope": "i" }, "conference.i.5": { "value": "Research record", "field": "Evidence type", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2016", "status": "published", "scope": "i" }, "conference.i.6": { "value": "C02", "field": "Source", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02" ], "disclosure_date": "2016", "status": "published", "scope": "i" }, "conference.x.0": { "value": "MICRO", "field": "Venue", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2016", "status": "published", "scope": "x" }, "conference.x.1": { "value": "2016", "field": "Year", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2016", "status": "published", "scope": "x" }, "conference.x.2": { "value": "Cambricon-X", "field": "Paper / talk / disclosure", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2016", "status": "published", "scope": "x" }, "conference.x.3": { "value": "Paper authors / company", "field": "Presenter / authors", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03" ], "disclosure_date": "2016", "status": "published", "scope": "x" }, "conference.x.4": { "value": "Research sparsity", "field": "Product", "basis": "Per reference product; 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