{ "vendor": "Arm", "cutoff": "2026-09-28", "sections": [ { "id": "01", "title": [ "Scope and executive synthesis", "研究范围与执行摘要" ], "blocks": [ { "id": "01.scope", "type": "prose", "text": [ "Families and weights: deep on Neoverse, CSS and AGI CPU; full on mesh/system IP; proportional on licensee silicon, GPU/NPU IP and software.\nStart: 2015, with Cortex-A server designs as the baseline.\nCutoff: 28 September 2026; includes Hot Chips 2026 and the September CSS N4 announcement.\nFocus: core evolution, coherent memory systems, integration boundaries and the CPU role in AI infrastructure.\nExclusions: exhaustive licensee SKUs and mobile generations; no Arm-branded datacenter training GPU or merchant AI NIC is established in the reviewed portfolio.", "产品权重：深入研究 Neoverse、CSS 和 AGI CPU；完整覆盖网格与系统 IP；适度覆盖被授权方芯片、GPU／NPU IP 和软件。\n起点：2015 年，以 Cortex-A 服务器设计为基线。\n截止：2026 年 9 月 28 日，覆盖 Hot Chips 2026 和 9 月 CSS N4 发布。\n重点：核心演进、一致性内存系统、集成边界，以及 CPU 在 AI 基础设施中的作用。\n不含：所有被授权方 SKU 和移动产品代际的穷尽清单；已审阅产品版图未确立 Arm 品牌的数据中心训练 GPU 或商用 AI NIC。" ], "sources": [ "E01", "E04", "E05", "E06" ] }, { "id": "01.thesis", "type": "prose", "text": [ "Arm’s infrastructure evolution has three overlapping layers. Neoverse separates server-oriented core development from a mobile-led product story. Compute Subsystems move validation of the CPU, mesh, memory interfaces and platform software upstream into Arm. AGI CPU adds Arm-designed merchant silicon in 2026. The last transition changes the competitive boundary: Arm can now supply both the building blocks for a custom server and a finished CPU for organizations without a custom-silicon program.", "Arm 的基础设施演进包含三个相互重叠的层次。Neoverse 将面向服务器的核心开发从以移动产品为中心的叙事中独立出来；计算子系统（Compute Subsystems，CSS）把 CPU、网格、内存接口和平台软件的验证工作上移到 Arm；2026 年 AGI CPU 又加入 Arm 自研商用芯片。最后这一步改变了竞争边界：Arm 既能为定制服务器提供构建模块，也能向没有自研芯片项目的机构提供完整 CPU。" ], "sources": [ "E03", "E05", "E15" ] }, { "id": "01.finding", "type": "prose", "text": [ "The important progression is not simply more cores. N1 establishes a scalable cloud core; V1 adds substantial vector capacity; N2 emphasizes density and Armv9; V2 widens the scalar machine and improves memory access; V3 and CSS bring confidential computing and more complete integration. CSS N4 then expands configuration and I/O headroom. The realized outcome still depends on the licensee’s memory channels, cache, physical design and software. A Neoverse name is therefore insufficient to predict socket performance.", "关键进步并非简单增加核心。N1 建立可扩展的云核心；V1 显著提高向量能力；N2 强调密度和 Armv9；V2 扩宽标量执行并改善访存；V3 与 CSS 引入机密计算和更完整的集成；CSS N4 进一步扩展配置与 I/O 空间。但最终结果仍取决于被授权方选择的内存通道、缓存、物理设计和软件。因此，仅凭 Neoverse 名称无法预测插槽性能。" ], "sources": [ "P01", "P02", "C02", "E04", "P06" ] } ] }, { "id": "02", "title": [ "Units, ownership and availability", "数值、设计归属与可用性" ], "blocks": [ { "id": "02.basis", "type": "prose", "text": [ "IP availability is not silicon general availability. A core does not have a universal foundry node, package power, socket count or DDR bandwidth. Those properties belong to an implementation. Tables retain the standard cross-vendor columns and use n/a for a field that does not apply, and n/d when reviewed sources do not disclose it. Cloud vCPU limits are not automatically physical core counts. Historical shipping does not imply current orderability.", "IP 可获取不等于芯片正式商用。核心 IP 没有统一的代工节点、封装功耗、插槽数或 DDR 带宽；这些属性属于具体实现。表格保留跨厂商统一字段，不适用记为 n/a，已审阅资料未披露记为 n/d。云实例的 vCPU 上限不能自动当作芯片物理核心数。历史已商用也不代表当前仍可订购。" ], "sources": [ "P08", "E08" ] }, { "id": "02.normalization", "type": "prose", "text": [ "Memory bandwidth is decimal payload GB/s: channels × transfers per second × eight bytes for a conventional 64-bit DDR channel. Per-core bandwidth is a derived equal-share ratio, not a reservation. Link figures are per direction unless explicitly labelled otherwise. ISA vector length, number of execution pipelines and aggregate bytes processed per cycle are different quantities. A two-pipeline 256-bit SVE core must not be compared with a four-pipeline 128-bit core by vector length alone. Confidential-computing capability likewise requires system and software enablement, not just an ISA label.", "内存带宽采用十进制有效载荷 GB/s：对常规 64 位 DDR 通道，通道数乘每秒传输次数，再乘八字节。每核带宽是均分推导值，不是预留保证。链路数值除非特别标注，否则按单方向计算。ISA 向量长度、执行流水线数量和每周期总处理字节数是不同指标；不能仅按向量长度比较双流水线 256 位 SVE 核心与四流水线 128 位核心。机密计算能力同样需要系统与软件启用，不能只看 ISA 名称。" ], "sources": [ "P02", "C02", "P04", "P07" ] } ] }, { "id": "03", "title": [ "Neoverse and CSS generation atlas", "Neoverse 与 CSS 代际总览" ], "blocks": [ { "id": "cpu-ip", "type": "table", "table": "cpu-ip" }, { "id": "css", "type": "table", "table": "css" } ] }, { "id": "04", "title": [ "2015-2018: separating ISA, core and server", "2015—2018：区分 ISA、核心与服务器" ], "blocks": [ { "id": "04.baseline", "type": "prose", "text": [ "Before Neoverse, an Arm server could use licensed Cortex cores or a custom Arm-compatible microarchitecture. These are different business and engineering paths. Cortex-A57/A72-era designs provided a baseline, while Qualcomm Falkor, Cavium/Marvell ThunderX and Fujitsu’s later A64FX demonstrate that an Arm ISA license does not imply a Neoverse core. That distinction remains essential for AmpereOne and NVIDIA Vera as well: their presence in the Arm ecosystem cannot be used as evidence about the internals of an Arm-designed core.", "Neoverse 出现之前，Arm 服务器既可以采用授权的 Cortex 核心，也可以采用自定义的 Arm 兼容微架构。这是两条不同的商业与工程路径。Cortex-A57／A72 时代的设计构成基线，而 Qualcomm Falkor、Cavium／Marvell ThunderX 以及后来的 Fujitsu A64FX 则说明，获得 Arm ISA 授权不等于采用 Neoverse 核心。对于 AmpereOne 和 NVIDIA Vera，这一区分依然重要：它们属于 Arm 生态，不能据此推断 Arm 自研核心的内部结构。" ], "sources": [ "E08", "C03", "P08" ] }, { "id": "04.serverrequirements", "type": "prose", "text": [ "A server platform requires much more than an instruction decoder. Coherent I/O, interrupt virtualization, page-table maintenance, RAS, firmware boot conventions and a stable operating-system environment all affect deployment cost. Neoverse’s 2018 branding and 2019 products made this infrastructure focus explicit. The lasting architectural advantage is the ability to assemble an application-specific balance of cores, caches, memory and accelerators, provided that integration and software costs remain manageable.", "服务器平台远不止指令译码器。一致性 I/O、中断虚拟化、页表维护、RAS、固件启动约定和稳定的操作系统环境都会影响部署成本。2018 年 Neoverse 品牌和 2019 年产品明确了这种基础设施定位。其长期架构优势在于按应用配置核心、缓存、内存与加速器比例，但前提是集成和软件成本可控。" ], "sources": [ "E01", "P01" ] } ] }, { "id": "05", "title": [ "N1 and E1: cloud cores and throughput cores", "N1 与 E1：云核心和吞吐型核心" ], "blocks": [ { "id": "05.n1core", "type": "prose", "text": [ "N1 combines four-instruction decode with dispatch of up to eight internal micro-operations, a 128-entry commit queue, 64 KB instruction and data caches, and private L2. Its decoupled branch predictor runs ahead of instruction fetch; a 6K-entry main BTB helps large server code footprints. These widths describe different pipeline stages, not interchangeable measures of IPC. Direct attachment to CMN-600 lets designers grow the coherent system without imposing a fixed mobile cluster boundary. Server features include RAS, virtualization extensions and coherent instruction-cache behavior.", "N1 具有四指令译码、最多八个内部微操作分派、128 项提交队列、64 KB 指令和数据缓存，以及私有 L2。解耦分支预测器可以先于指令获取运行，6K 项主 BTB 服务于服务器的大代码工作集。上述宽度属于不同流水级，不能互换为 IPC 指标。直接连接 CMN-600 让设计者扩展一致性系统，而不必受固定移动核心簇边界限制。服务器功能包括 RAS、虚拟化扩展和指令缓存一致性。" ], "sources": [ "P01" ] }, { "id": "05.n1implementation", "type": "prose", "text": [ "Hot Chips 2019 explains the architecture; ISSCC 2020 paper 8.3 supplies a concrete 3 GHz, 7 nm implementation anchor. The ISSCC summary emphasizes a short, operation-dependent pipeline and a low-latency memory hierarchy. Its PPA comparisons belong to that implementation and baseline, not every N1 licensee. E1 instead targets data-plane throughput with two hardware threads per core. It should not be treated as a low-clocked N1 or used to infer SMT in N-series and V-series products.", "Hot Chips 2019 解释架构，ISSCC 2020 论文 8.3 则提供 3 GHz、7 nm 的具体实现依据。ISSCC 摘要强调随操作变化的短流水线和低延迟内存层次。其中的性能、功耗、面积比较属于该实现及其基线，不能套用到所有 N1 被授权方产品。E1 则通过每核两个硬件线程提高数据平面吞吐；它不是降低频率的 N1，也不能用来推断 N 系列和 V 系列具有 SMT。" ], "sources": [ "C01", "E01", "P08" ] }, { "id": "05.n1deployment", "type": "prose", "text": [ "AWS Graviton2 and Ampere Altra turned N1 into commercial cloud and merchant-server products. Their usefulness comes from a complete platform and a large population of independent software threads, rather than from one universal Arm socket. Altra Max extends the density approach. Increasing cores while holding memory-channel count constant reduces the average external bandwidth budget per core; cache locality and workload consolidation determine whether that trade is productive.", "AWS Graviton2 和 Ampere Altra 将 N1 带入商业云和商用服务器，Altra Max 进一步提高密度。这些产品的价值来自完整平台和大量独立软件线程，而不是一个通用的“Arm 插槽”。当内存通道数保持不变时，增加核心会降低平均每核片外带宽预算；缓存局部性和工作负载整合效果决定这种取舍是否有利。" ], "sources": [ "E08", "P08" ] } ] }, { "id": "06", "title": [ "V1 and N2: vector performance versus density", "V1 与 N2：向量性能与密度分线" ], "blocks": [ { "id": "06.v1", "type": "prose", "text": [ "V1 creates a performance-oriented branch rather than replacing N1 in every role. Its two 256-bit SVE pipelines, BF16 support and INT8 matrix instructions increase CPU-side scientific and ML capability. Decoupled prediction, an instruction-side operation cache and a wider machine aim to keep the execution units busy. Vector-length-agnostic programming protects software from assuming one implementation width. AWS Graviton3 is the important cloud realization, but its chiplets and DDR5 channels are AWS design choices, not intrinsic V1 properties.", "V1 建立面向性能的分支，而不是在所有场景替代 N1。双 256 位 SVE 流水线、BF16 支持和 INT8 矩阵指令提高 CPU 侧科学计算与机器学习能力。解耦预测、指令侧操作缓存和更宽的执行机器共同提高执行单元利用率。向量长度无关编程避免软件绑定某一种实现宽度。AWS Graviton3 是重要云端实现，但芯粒结构与 DDR5 通道属于 AWS 的设计选择，并非 V1 固有属性。" ], "sources": [ "P02", "E02", "E08" ] }, { "id": "06.n2", "type": "prose", "text": [ "N2 takes Armv9 and 128-bit SVE2 into a more density-oriented core. The Hot Chips 2021 disclosure places the core together with CMN-700 and the wider system roadmap. The appropriate comparison with V1 is performance per area, per watt and per memory channel on the intended workload, not SVE width alone. Microsoft Cobalt 100 and networking implementations demonstrate how one core family can support different system balances. The CSS N2 offering in 2023 further reduces the amount of subsystem integration that a licensee must perform.", "N2 将 Armv9 和 128 位 SVE2 引入更强调密度的核心。Hot Chips 2021 将它与 CMN-700 及系统路线图一起披露。与 V1 比较时，应针对目标工作负载分析单位面积、单位功耗和每内存通道的性能，而不是只比较 SVE 位宽。Microsoft Cobalt 100 与网络领域的实现表明，同一核心家族可支持不同系统配比。2023 年 CSS N2 又减少了被授权方自行完成的子系统集成工作。" ], "sources": [ "P03", "C04", "E03", "E08" ] } ] }, { "id": "07", "title": [ "V2: width, memory concurrency and coherent hosts", "V2：执行宽度、访存并发与一致性主机" ], "blocks": [ { "id": "07.v2core", "type": "prose", "text": [ "V2’s Hot Chips 2023 disclosure is unusually useful for reconstructing the whole core. It shows six-instruction decode, eight-wide dispatch and retirement, a 320-plus out-of-order window, six ALUs, two branch pipelines, and two load/store pipes plus one additional load pipe. Four 128-bit vector datapaths replace the V1 organization. The optional 2 MB private L2 retains a quoted ten-cycle load-to-use latency. Prefetch changes include indirect and page-table-walk handling, with lower priority for speculative prefetch traffic than demand requests. The design broadens useful concurrency while controlling memory interference.", "V2 的 Hot Chips 2023 披露尤其有助于还原完整核心：六指令译码、八宽分派与退休、超过 320 项的乱序窗口、六个 ALU、两条分支流水线，以及两条读写流水线加一条额外读取流水线。四条 128 位向量数据通路取代 V1 的组织方式。可选 2 MB 私有 L2 保持标称十周期的 load-to-use 延迟。预取改进涉及间接访问和页表遍历，并让推测预取流量低于需求请求的优先级。设计目标是在控制访存干扰的同时扩展有效并发。" ], "sources": [ "C02" ] }, { "id": "07.v2systems", "type": "prose", "text": [ "V2 appears in AWS Graviton4, Google Axion and NVIDIA Grace. These systems illustrate three different optimizations: general cloud throughput, a vertically integrated cloud platform, and a coherent accelerator host. Grace’s LPDDR5X and NVLink-C2C belong to NVIDIA’s CPU and superchip integration. They do not make NVLink an Arm interconnect. Conversely, a cloud processor’s DDR channels do not describe Grace. The common core provides software and implementation reuse; the system fabric and memory hierarchy determine the node-level behavior.", "V2 出现在 AWS Graviton4、Google Axion 和 NVIDIA Grace 中，分别体现通用云吞吐、垂直集成云平台和一致性加速器主机三种优化方向。Grace 的 LPDDR5X 与 NVLink-C2C 属于 NVIDIA 的 CPU 和超级芯片集成，不能因此将 NVLink 归为 Arm 互联。反过来，云处理器的 DDR 通道配置也不能描述 Grace。共享核心带来软件与实现复用，系统互联和内存层次决定节点行为。" ], "sources": [ "E08", "P15", "E16", "E17" ] } ] }, { "id": "08", "title": [ "V3, N3 and CSS: moving the integration boundary", "V3、N3 与 CSS：改变集成边界" ], "blocks": [ { "id": "08.cssmeaning", "type": "prose", "text": [ "The 2024 generation makes a preintegrated subsystem a central product rather than a reference illustration. CSS V3 combines V3 cores, coherent fabric and platform IP, while CSS N3 serves a broader range of cloud, networking and edge configurations. V3 introduces Arm Confidential Computing Architecture support within the Neoverse family. CCA’s Realm isolation model is separate from Morello’s capability-based memory safety. Neither feature should be inferred merely because a chip implements some Armv9 instructions.", "2024 年这一代将预集成子系统变为核心产品，而不仅是参考示意。CSS V3 组合 V3 核心、一致性互联与平台 IP；CSS N3 面向更广泛的云、网络和边缘配置。V3 在 Neoverse 家族中引入 Arm 机密计算架构（CCA）支持。CCA 的 Realm 隔离模型与 Morello 的基于能力的内存安全不同。不能因为芯片实现了部分 Armv9 指令，就推断它具有其中任何一项功能。" ], "sources": [ "E04", "P04", "P09", "R01" ] }, { "id": "08.cssconsequences", "type": "prose", "text": [ "CSS trades some integration freedom for a verified baseline and a shorter path to silicon. The licensee still owns choices in packaging, memory population, clocks, firmware policy and commercial qualification. Microsoft Cobalt 200 uses CSS V3, yet its complete SoC has 132 active cores, 3 MB L2 per core and 192 MB system cache. Cobalt 200 entered customer preview in 2026. This is why a subsystem’s core ceiling must not be mistaken for a package ceiling. AWS Graviton5 provides another V3-based cloud generation, reaching 192 cores per chip and becoming available through M9g/M9gd in June 2026.", "CSS 用一部分集成自由度换取预验证基线和更短的芯片开发路径。封装、内存配置、频率、固件策略和商业验证仍由被授权方决定。Microsoft Cobalt 200 使用 CSS V3，但完整 SoC 具有 132 个启用核心、每核 3 MB L2 和 192 MB 系统缓存。Cobalt 200 于 2026 年进入客户预览。因此，子系统核心上限不能误当作封装上限。AWS Graviton5 则提供另一种基于 V3 的云端实现，每颗芯片达到 192 核，并于 2026 年 6 月通过 M9g／M9gd 商用。" ], "sources": [ "E07", "E18", "E19", "E20", "P08" ] } ] }, { "id": "09", "title": [ "AGI CPU: Arm becomes a silicon supplier", "AGI CPU：Arm 成为芯片供应商" ], "blocks": [ { "id": "09.agiidentity", "type": "prose", "text": [ "Announced in March 2026, AGI CPU turns the Neoverse platform into an Arm-designed server product. By the May shareholder update, commercial systems were available to order from named OEMs. Hot Chips 2026 adds the architecture context; the current product brief supplies SKU-level boundaries. The 136-core SP113012 has 2 MB L2 per core and 128 MB shared system cache, twelve DDR5-8800 channels, 96 PCIe 6 lanes and CXL 3.0 Type 3 support. Its maximum clock is 3.5 GHz; the 3.7 GHz headline belongs to the 64-core variant. All three listed variants have a 300 W base TDP setting.", "AGI CPU 于 2026 年 3 月发布，将 Neoverse 平台转化为 Arm 自研服务器产品。5 月股东更新已说明，指定 OEM 的商业系统可以订购。Hot Chips 2026 补充架构背景，当前产品简介则确定 SKU 边界。136 核 SP113012 配备每核 2 MB L2、128 MB 共享系统缓存、十二通道 DDR5-8800、96 条 PCIe 6 通道及 CXL 3.0 Type 3 支持。其最高频率为 3.5 GHz，3.7 GHz 宣传值属于 64 核变体；所列三个变体的基础 TDP 均设为 300 W。" ], "sources": [ "P07", "E05", "E15", "C03" ] }, { "id": "09.agibalance", "type": "prose", "text": [ "The design emphasizes feeding many independent CPU tasks and attaching external accelerators. A theoretical 844.8 GB/s channel sum yields 6.21 GB/s per core at 136 cores and 13.2 GB/s at 64 cores. Those derived ratios explain the memory-per-core variant without implying sustained application bandwidth. The CPU remains a host and an inference-capable general processor. It is not an HBM tensor accelerator, and the 300 W CPU rating cannot be multiplied into a complete rack power estimate without memory, storage, NICs, fans and power-conversion losses.", "该设计强调为大量独立 CPU 任务供给数据，并连接外部加速器。理论通道带宽合计为 844.8 GB/s，136 核时平均每核 6.21 GB/s，64 核时为 13.2 GB/s。这些推导比例解释了高每核内存配置的定位，但不代表应用持续带宽。该 CPU 仍是主机和具有推理能力的通用处理器，不是 HBM 张量加速器。也不能仅将 300 W CPU 功耗相乘得到完整机架功耗，还必须计入内存、存储、NIC、风扇与电源转换损耗。" ], "sources": [ "P07", "E13" ] }, { "id": "cpu-silicon", "type": "table", "table": "cpu-silicon" } ] }, { "id": "10", "title": [ "CSS N4 and the current roadmap", "CSS N4 与当前路线图" ], "blocks": [ { "id": "10.n4", "type": "prose", "text": [ "September 2026 CSS N4 is a new IP/subsystem generation, not the core inside the first AGI CPU. Arm lists up to 128 N4 cores per die, private L2 configurable to 2 MB, a 3 nm implementation target, DDR5 or LPDDR6, and PCIe 7/CXL 4.0 I/O. These are subsystem capabilities; a licensee need not instantiate every maximum together. The architectural direction is a wider deployment envelope, including CPU hosts and infrastructure processors whose memory and I/O requirements differ.", "2026 年 9 月的 CSS N4 是新的 IP／子系统代际，并非首代 AGI CPU 内部的核心。Arm 列出每裸片最高 128 个 N4 核心、可配置到 2 MB 的私有 L2、3 nm 实现目标、DDR5 或 LPDDR6，以及 PCIe 7／CXL 4.0 I/O。这些属于子系统能力，被授权方不必同时实现所有最大配置。架构方向是扩大部署范围，覆盖内存和 I/O 需求各异的 CPU 主机及基础设施处理器。" ], "sources": [ "P06", "P10", "E06" ] }, { "id": "10.n4gaps", "type": "prose", "text": [ "A public IP announcement does not establish final commercial silicon clocks, socket TDP, DDR qualification or deployment dates. The reviewed evidence does not provide a complete N4 core queue-and-port disclosure comparable with the V2 Hot Chips talk. The report therefore preserves the new generation and its verified interfaces without filling those fields from client-core analogies. Mobile CSS and automotive V3AE derivatives show reuse, but their safety, graphics and power domains remain distinct from the cloud subsystem.", "公开的 IP 发布不能确定最终商业芯片频率、插槽 TDP、DDR 验证范围或部署时间。已审阅证据尚未提供像 V2 Hot Chips 演讲那样完整的 N4 队列和执行端口披露。因此，本报告保留新代际和已确认接口，不从客户端核心类比补齐这些字段。移动 CSS 和汽车 V3AE 衍生产品体现技术复用，但它们的安全、图形与功耗域仍不同于云子系统。" ], "sources": [ "P06", "E06", "E10" ] } ] }, { "id": "11", "title": [ "CMN, CHI and the infrastructure offload boundary", "CMN、CHI 与基础设施卸载边界" ], "blocks": [ { "id": "11.mesh", "type": "prose", "text": [ "CMN-600, CMN-700 and CMN S3 make coherence a configurable system resource. Request nodes inject CPU and I/O transactions; home nodes coordinate address ownership, directories and system cache; memory-facing nodes connect to controllers. CHI specifies transaction and coherence behavior, while the mesh implements routing and buffering. Consequently, a CHI data-channel width is not a SerDes lane rate and a mesh peak is not DRAM bandwidth. Chiplet crossings add a physical-link and latency problem beyond on-die coherence.", "CMN-600、CMN-700 与 CMN S3 将一致性变成可配置的系统资源。请求节点注入 CPU 和 I/O 事务，归属节点协调地址所有权、目录与系统缓存，面向内存的节点连接控制器。CHI 规定事务和一致性行为，网格实现路由与缓冲。因此，CHI 数据通道宽度不是 SerDes 通道速率，网格峰值也不是 DRAM 带宽。跨芯粒连接在片上一致性之外，又增加了物理链路与延迟问题。" ], "sources": [ "P01", "C02", "P09", "P14" ] }, { "id": "11.dpu", "type": "prose", "text": [ "Arm cores inside DPUs and IPUs provide a programmable control or service processor. Packet pipelines, RDMA engines, crypto, local memory and ports are supplied by the chip designer. Arm’s participation in a DPU therefore does not make that device an Arm-branded NIC. CSS N3 and the Alphawave collaboration show how a compute chiplet can be combined with a networking or acceleration die. The useful unit of comparison is the whole device: host interface, offload engines, transport semantics and software isolation.", "DPU 和 IPU 内部的 Arm 核心承担可编程控制或服务处理。报文流水线、RDMA 引擎、密码模块、本地内存和端口由芯片设计者提供。因此，使用 Arm 核心的 DPU 并不是 Arm 品牌 NIC。CSS N3 与 Alphawave 合作展示了计算芯粒如何与网络或加速裸片组合。有效比较单位是完整设备：主机接口、卸载引擎、传输语义和软件隔离。" ], "sources": [ "E09", "P08" ] }, { "id": "interconnect", "type": "table", "table": "interconnect" }, { "id": "network", "type": "table", "table": "network" } ] }, { "id": "12", "title": [ "GPU and NPU IP: complementary edge compute", "GPU 与 NPU IP：互补的边缘计算" ], "blocks": [ { "id": "12.gpu", "type": "prose", "text": [ "Mali evolves through Midgard, Bifrost, Valhall and later graphics generations; Immortalis adds a premium graphics branch. These designs target integrated graphics and shared-memory SoCs. Their presence does not establish a merchant HBM GPU for distributed training. The 2026 Mali G2-Ultra NX adds dedicated neural acceleration within the mobile graphics platform, alongside the C2 CPU cluster and SME2. This is important convergence at the edge, while its bandwidth, power and software environment remain different from a datacenter accelerator card.", "Mali 经历 Midgard、Bifrost、Valhall 及后续图形代际，Immortalis 增加高端图形分支。这些设计面向集成图形和共享内存 SoC，并不构成用于分布式训练的商用 HBM GPU。2026 年 Mali G2-Ultra NX 在移动图形平台内增加专用神经加速，与 C2 CPU 簇和 SME2 配合。这是边缘侧的重要融合，但带宽、功耗与软件环境仍不同于数据中心加速卡。" ], "sources": [ "E10", "E12" ] }, { "id": "12.ethos", "type": "prose", "text": [ "Ethos-N77/N78 address application-processor and edge inference integration; Ethos-U55/U65/U85 address constrained embedded systems. U65 extends the U55 approach into Cortex-A, Cortex-R and Neoverse systems. U85 expands to 128-2048 MAC units and supports transformer-oriented operators. At 1 GHz, 2048 MACs correspond to 4.096 TOPS when one multiply-add counts as two integer operations; this is a configuration calculation, not BF16 throughput. Compiler partitioning, SRAM tiling and unsupported-operator fallback determine practical model coverage.", "Ethos-N77／N78 面向应用处理器和边缘推理集成，Ethos-U55／U65／U85 则服务资源受限的嵌入式系统。U65 将 U55 路线扩展到 Cortex-A、Cortex-R 和 Neoverse 系统；U85 扩展至 128—2048 个 MAC 单元，并支持面向 Transformer 的算子。在 1 GHz 下，2048 个 MAC 按每次乘加两次整数运算计算，对应 4.096 TOPS；这是配置推导，不是 BF16 吞吐。编译器划分、SRAM 分块和不支持算子的回退决定实际模型覆盖。" ], "sources": [ "P11", "P12", "E11", "E12" ] }, { "id": "accelerators", "type": "table", "table": "accelerators" } ] }, { "id": "13", "title": [ "Software, security and research evidence", "软件、安全与研究证据" ], "blocks": [ { "id": "13.software", "type": "prose", "text": [ "Arm’s software advantage comes from a common AArch64 ecosystem combined with implementation-specific optimization. GCC/LLVM targets, Linux scheduling and NUMA placement, optimized math kernels, Compute Library and profiling tools must match the actual core and memory system. SVE-length-agnostic code still needs sensible blocking and cache reuse. CSS reference software supplies firmware and platform models; it does not automatically qualify a production server. In AI hosting, orchestration latency, tokenizer performance and communication progress can matter even when all large matrix operations run elsewhere.", "Arm 的软件优势来自共同的 AArch64 生态和针对实现的优化。GCC／LLVM 目标、Linux 调度与 NUMA 放置、优化数学内核、Compute Library 和性能分析工具必须匹配实际核心及内存系统。向量长度无关的 SVE 代码仍需要合理分块与缓存复用。CSS 参考软件提供固件和平台模型，并不自动完成生产服务器验证。即使大型矩阵运算全部在外部执行，AI 主机的编排延迟、分词性能和通信推进仍可能重要。" ], "sources": [ "P13", "P14", "P08" ] }, { "id": "13.research", "type": "prose", "text": [ "The academic record adds mechanisms and evaluation methods rather than a complete product roadmap. Arm-associated MISB at ISCA 2019 and temporal prefetching at MICRO 2019 study the storage and traffic cost of prediction metadata. Triangel at ISCA 2024 studies timeliness and accuracy; HPCA 2025 bandwidth-partitioning work evaluates resource interference; ASPLOS 2025 hierarchical prefetching addresses large instruction footprints. These help explain what designers are optimizing. They do not prove that a named production core implements the proposed mechanism. Morello is different: its documented N1-derived evaluation platform is an explicit research-to-hardware link, but remains a capability-security prototype rather than a standard Neoverse feature.", "学术记录补充机制和评估方法，而不是完整产品路线图。Arm 参与的 ISCA 2019 MISB 和 MICRO 2019 时间预取研究关注预测元数据的存储与流量成本；ISCA 2024 Triangel 研究及时性和准确率；HPCA 2025 带宽划分研究评估资源干扰；ASPLOS 2025 分层预取针对较大的指令工作集。这些工作有助于理解设计者优化的问题，但不能证明某量产核心采用了所提机制。Morello 则不同：文档明确说明其评估平台源自 N1，构成研究与硬件的直接联系；但它仍是能力安全原型，不是标准 Neoverse 功能。" ], "sources": [ "R01", "R02", "R03", "R04", "R05", "R06", "R07" ] }, { "id": "software", "type": "table", "table": "software" } ] }, { "id": "14", "title": [ "Systems and quantitative balance", "系统与定量配比" ], "blocks": [ { "id": "systems", "type": "table", "table": "systems" }, { "id": "ratios", "type": "table", "table": "ratios" }, { "id": "14.notratios", "type": "prose", "text": [ "HBM bytes per dense BF16/FP8 FLOP and accelerator scale-up/HBM ratios are n/a for the Arm-branded CPU/IP portfolio. Assigning a partner GPU’s HBM to Arm would corrupt a cross-vendor comparison. Likewise, no universal tokens/W number follows from core count or an IP efficiency projection. An end-to-end measurement needs the actual model, precision, latency target, memory configuration and system power boundary.", "对于 Arm 品牌 CPU／IP 产品版图，HBM 字节数与稠密 BF16／FP8 FLOP 的比值，以及加速器纵向带宽与 HBM 的比值，均为 n/a。把合作伙伴 GPU 的 HBM 归到 Arm 会破坏跨厂商比较。同样，核心数或 IP 能效预测不能推出通用 tokens/W；端到端测量必须明确模型、精度、延迟目标、内存配置和系统功耗边界。" ], "sources": [ "P07", "P11" ] } ] }, { "id": "15", "title": [ "Conference-to-product index", "会议与产品对应索引" ], "blocks": [ { "id": "conference", "type": "table", "table": "conference" }, { "id": "15.venues", "type": "prose", "text": [ "DAC, MWC, Computex, OCP, GTC, SC/ISC, VLSI and ISSCC/JSSC are complementary channels: design methodology, telecom deployments, ecosystem launches, racks, coherent GPU hosts, HPC systems and implementation technology. They are included when a specific disclosure is tied to a covered generation. The index is a verified selection, not a claim that Arm presented every product at every venue. The N1 ISSCC entry uses the conference’s published technical summary; it does not imply access to the complete paper.", "DAC、MWC、Computex、OCP、GTC、SC／ISC、VLSI 和 ISSCC／JSSC 是互补渠道，分别涉及设计方法、电信部署、生态发布、机架、一致性 GPU 主机、HPC 系统及实现技术。只有具体披露与所覆盖代际建立联系时，才作为产品证据列入。索引是核验后的精选，不表示 Arm 在每个会议展示了每款产品。N1 的 ISSCC 条目使用会议公开技术摘要，并不表示已获取论文全文。" ], "sources": [ "C01", "E09", "E13", "P15" ] } ] }, { "id": "16", "title": [ "Codename and ownership crosswalk", "代号与设计归属对照" ], "blocks": [ { "id": "crosswalk", "type": "table", "table": "crosswalk" } ] }, { "id": "17", "title": [ "Integrated stack across four eras", "四个时代的整体产品栈" ], "blocks": [ { "id": "17.stackintro", "type": "prose", "text": [ "These figures show ownership and composition, not an assertion of a common physical fabric across all licensees. Connections indicate integration relationships. Exact bandwidth remains implementation-specific.", "以下图示表达归属与组成关系，并不意味着所有被授权方使用共同物理互联。连接线表示集成关系，精确带宽仍取决于具体实现。" ], "sources": [ "P01", "E03", "P07", "E06" ] }, { "id": "early", "type": "figure", "figure": "early" }, { "id": "n1era", "type": "figure", "figure": "n1era" }, { "id": "cssera", "type": "figure", "figure": "cssera" }, { "id": "current", "type": "figure", "figure": "current" }, { "id": "hierarchy", "type": "table", "table": "hierarchy" } ] }, { "id": "18", "title": [ "Engineering conclusions", "工程结论" ], "blocks": [ { "id": "18.conclusions", "type": "prose", "text": [ "Arm’s decade is best understood as the gradual productization of a configurable system. Core efficiency matters, but the larger gains come from pairing the right core with the right memory, coherence and deployment model. CSS reduces integration cost without removing implementation responsibility. Merchant AGI silicon widens access to the platform while introducing a second relationship with existing licensees. For AI infrastructure, the enduring CPU requirements are predictable service latency, memory capacity and bandwidth, accelerator I/O, isolation and mature software. Neither an Arm ISA label nor a maximum core count settles those questions.", "Arm 的十年最适合被理解为可配置系统逐步产品化的过程。核心能效很重要，但更大的收益来自核心与内存、一致性和部署模型的匹配。CSS 降低集成成本，却没有消除实现责任。商用 AGI 芯片扩大平台的可用范围，也让 Arm 与既有被授权方形成第二种关系。对 AI 基础设施而言，CPU 的长期要求是可预测服务延迟、内存容量与带宽、加速器 I/O、隔离和成熟软件。Arm ISA 标签或最大核心数都不能单独回答这些问题。" ], "sources": [ "P07", "E03", "E06", "P13" ] } ] } ], "tables": { "cpu-ip": { "id": "cpu-ip", "title": [ "CPU IP comparison: implementation fields remain separate", "CPU IP 对比：实现属性单独区分" ], "headers": [ [ "Generation / reference SKU", "代际／参考 SKU" ], [ "Codename", "代号" ], [ "GA", "正式商用" ], [ "Status", "状态" ], [ "Core µarch", "核心微架构" ], [ "Cores / threads", "核心／线程" ], [ "Process per die", "各裸片工艺" ], [ "Dies / packaging", "裸片／封装" ], [ "L2 per core", "每核 L2" ], [ "L3 / domain", "L3／共享域" ], [ "Memory: channels; rate; GB/s", "内存：通道；速率；GB/s" ], [ "Sockets / links", "插槽／互联" ], [ "PCIe / CXL", "PCIe／CXL" ], [ "TDP", "TDP" ], [ "Vector / matrix ISA", "向量／矩阵 ISA" ] ], "rows": [ { "id": "n1", "values": [ [ "Neoverse N1 / Ares", "Neoverse N1 / Ares" ], [ "Ares", "Ares" ], [ "2019 IP disclosure", "2019 IP 披露" ], [ "Licensable IP", "可授权 IP" ], [ "N1", "N1" ], [ "Configurable; E1 SMT2; N4 threads n/d; others single-threaded", "可配置；E1 SMT2；N4 线程数 n/d；其余单线程" ], [ "Licensee-defined; N4 targets 3 nm", "由被授权方决定；N4 面向 3 nm" ], [ "IP, not a packaged SKU", "IP，非封装 SKU" ], [ "512 KB / 1 MB", "512 KB / 1 MB" ], [ "System configuration", "依系统配置" ], [ "Implementation-defined", "依具体实现" ], [ "n/a", "n/a" ], [ "System integration", "依系统集成" ], [ "n/a", "n/a" ], [ "Armv8.2-A; NEON 128-bit", "Armv8.2-A; NEON 128-bit" ] ], "sources": [ "P01", "E01" ] }, { "id": "e1", "values": [ [ "Neoverse E1", "Neoverse E1" ], [ "n/d", "n/d" ], [ "2019 IP disclosure", "2019 IP 披露" ], [ "Licensable IP", "可授权 IP" ], [ "E1", "E1" ], [ "Configurable; E1 SMT2; N4 threads n/d; others single-threaded", "可配置；E1 SMT2；N4 线程数 n/d；其余单线程" ], [ "Licensee-defined; N4 targets 3 nm", "由被授权方决定；N4 面向 3 nm" ], [ "IP, not a packaged SKU", "IP，非封装 SKU" ], [ "n/d", "n/d" ], [ "System configuration", "依系统配置" ], [ "Implementation-defined", "依具体实现" ], [ "n/a", "n/a" ], [ "System integration", "依系统集成" ], [ "n/a", "n/a" ], [ "Armv8.2-A; NEON; SMT2", "Armv8.2-A; NEON; SMT2" ] ], "sources": [ "P08", "E01" ] }, { "id": "v1", "values": [ [ "Neoverse V1 / Zeus", "Neoverse V1 / Zeus" ], [ "Zeus", "Zeus" ], [ "2020-2021 IP disclosure", "2020-2021 IP 披露" ], [ "Licensable IP", "可授权 IP" ], [ "V1", "V1" ], [ "Configurable; E1 SMT2; N4 threads n/d; others single-threaded", "可配置；E1 SMT2；N4 线程数 n/d；其余单线程" ], [ "Licensee-defined; N4 targets 3 nm", "由被授权方决定；N4 面向 3 nm" ], [ "IP, not a packaged SKU", "IP，非封装 SKU" ], [ "512 KB / 1 MB", "512 KB / 1 MB" ], [ "System configuration", "依系统配置" ], [ "Implementation-defined", "依具体实现" ], [ "n/a", "n/a" ], [ "System integration", "依系统集成" ], [ "n/a", "n/a" ], [ "SVE: 2 x 256-bit; BF16; INT8", "SVE: 2 x 256-bit; BF16; INT8" ] ], "sources": [ "P02", "E02" ] }, { "id": "n2", "values": [ [ "Neoverse N2 / Perseus", "Neoverse N2 / Perseus" ], [ "Perseus", "Perseus" ], [ "2020-2021 IP disclosure", "2020-2021 IP 披露" ], [ "Licensable IP", "可授权 IP" ], [ "N2", "N2" ], [ "Configurable; E1 SMT2; N4 threads n/d; others single-threaded", "可配置；E1 SMT2；N4 线程数 n/d；其余单线程" ], [ "Licensee-defined; N4 targets 3 nm", "由被授权方决定；N4 面向 3 nm" ], [ "IP, not a packaged SKU", "IP，非封装 SKU" ], [ "512 KB / 1 MB", "512 KB / 1 MB" ], [ "System configuration", "依系统配置" ], [ "Implementation-defined", "依具体实现" ], [ "n/a", "n/a" ], [ "System integration", "依系统集成" ], [ "n/a", "n/a" ], [ "Armv9; SVE2 128-bit; BF16", "Armv9; SVE2 128-bit; BF16" ] ], "sources": [ "P03", "P08", "E02" ] }, { "id": "v2", "values": [ [ "Neoverse V2 / Demeter", "Neoverse V2 / Demeter" ], [ "Demeter", "Demeter" ], [ "2022-2023 IP disclosure", "2022-2023 IP 披露" ], [ "Licensable IP", "可授权 IP" ], [ "V2", "V2" ], [ "Configurable; E1 SMT2; N4 threads n/d; others single-threaded", "可配置；E1 SMT2；N4 线程数 n/d；其余单线程" ], [ "Licensee-defined; N4 targets 3 nm", "由被授权方决定；N4 面向 3 nm" ], [ "IP, not a packaged SKU", "IP，非封装 SKU" ], [ "1 / 2 MB", "1 / 2 MB" ], [ "System configuration", "依系统配置" ], [ "Implementation-defined", "依具体实现" ], [ "n/a", "n/a" ], [ "System integration", "依系统集成" ], [ "n/a", "n/a" ], [ "Armv9; SVE2 128-bit; 4 vector pipes", "Armv9; SVE2 128-bit; 4 vector pipes" ] ], "sources": [ "C02", "P08" ] }, { "id": "v3", "values": [ [ "Neoverse V3", "Neoverse V3" ], [ "n/d", "n/d" ], [ "2024 IP disclosure", "2024 IP 披露" ], [ "Licensable IP", "可授权 IP" ], [ "V3", "V3" ], [ "Configurable; E1 SMT2; N4 threads n/d; others single-threaded", "可配置；E1 SMT2；N4 线程数 n/d；其余单线程" ], [ "Licensee-defined; N4 targets 3 nm", "由被授权方决定；N4 面向 3 nm" ], [ "IP, not a packaged SKU", "IP，非封装 SKU" ], [ "2 / 3 MB", "2 / 3 MB" ], [ "System configuration", "依系统配置" ], [ "Implementation-defined", "依具体实现" ], [ "n/a", "n/a" ], [ "System integration", "依系统集成" ], [ "n/a", "n/a" ], [ "Armv9.2-A; SVE2; CCA", "Armv9.2-A; SVE2; CCA" ] ], "sources": [ "P04", "P08", "E04" ] }, { "id": "n3", "values": [ [ "Neoverse N3", "Neoverse N3" ], [ "n/d", "n/d" ], [ "2024 IP disclosure", "2024 IP 披露" ], [ "Licensable IP", "可授权 IP" ], [ "N3", "N3" ], [ "Configurable; E1 SMT2; N4 threads n/d; others single-threaded", "可配置；E1 SMT2；N4 线程数 n/d；其余单线程" ], [ "Licensee-defined; N4 targets 3 nm", "由被授权方决定；N4 面向 3 nm" ], [ "IP, not a packaged SKU", "IP，非封装 SKU" ], [ "128 KB - 2 MB", "128 KB - 2 MB" ], [ "System configuration", "依系统配置" ], [ "Implementation-defined", "依具体实现" ], [ "n/a", "n/a" ], [ "System integration", "依系统集成" ], [ "n/a", "n/a" ], [ "Armv9.2-A; SVE2", "Armv9.2-A; SVE2" ] ], "sources": [ "P08", "E04" ] }, { "id": "n4", "values": [ [ "CSS N4", "CSS N4" ], [ "n/d", "n/d" ], [ "2026-09 IP disclosure", "2026-09 IP 披露" ], [ "Licensable IP", "可授权 IP" ], [ "N4", "N4" ], [ "Configurable; E1 SMT2; N4 threads n/d; others single-threaded", "可配置；E1 SMT2；N4 线程数 n/d；其余单线程" ], [ "Licensee-defined; N4 targets 3 nm", "由被授权方决定；N4 面向 3 nm" ], [ "IP, not a packaged SKU", "IP，非封装 SKU" ], [ "up to 2 MB", "up to 2 MB" ], [ "System configuration", "依系统配置" ], [ "Implementation-defined", "依具体实现" ], [ "n/a", "n/a" ], [ "System integration", "依系统集成" ], [ "n/a", "n/a" ], [ "Armv9; details n/d", "Armv9; details n/d" ] ], "sources": [ "P06", "P10", "E06" ] } ], "panels": [ [ 0, 2, 3, 4, 5 ], [ 0, 6, 7, 8, 9 ], [ 0, 10, 11, 12, 13, 14 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "css": { "id": "css", "title": [ "Subsystem integration envelope", "子系统集成范围" ], "headers": [ [ "Subsystem", "子系统" ], [ "Disclosure", "披露" ], [ "Core envelope", "核心范围" ], [ "Memory / I/O", "内存／I/O" ], [ "Integration meaning", "集成含义" ] ], "rows": [ { "id": "cssn2", "values": [ [ "CSS N2", "CSS N2" ], [ "2023", "2023" ], [ "Up to 64 N2", "最高 64 个 N2" ], [ "DDR5/LPDDR5; PCIe 5 / CXL", "DDR5/LPDDR5; PCIe 5 / CXL" ], [ "Prevalidated CPU and system design", "预验证 CPU 与系统设计" ] ], "sources": [ "E03" ] }, { "id": "cssv3", "values": [ [ "CSS V3", "CSS V3" ], [ "2024", "2024" ], [ "Up to 64 V3 per subsystem", "每子系统最高 64 个 V3" ], [ "up to 12 memory channels; 64 PCIe 5/CXL lanes", "up to 12 memory channels; 64 PCIe 5/CXL lanes" ], [ "Chiplet-ready; CCA support", "支持芯粒集成与 CCA" ] ], "sources": [ "P09", "E04" ] }, { "id": "cssn3", "values": [ [ "CSS N3", "CSS N3" ], [ "2024", "2024" ], [ "Configurable N3 subsystem", "可配置 N3 子系统" ], [ "CMN S3; CHI C2C", "CMN S3; CHI C2C" ], [ "Cloud, networking, DPU and edge customization", "云、网络、DPU 与边缘定制" ] ], "sources": [ "E04", "E09", "P08" ] }, { "id": "cssn4", "values": [ [ "CSS N4", "CSS N4" ], [ "2026-09", "2026-09" ], [ "Up to 128 N4 per die", "每裸片最高 128 个 N4" ], [ "DDR5 / LPDDR6; PCIe 7 / CXL 4.0", "DDR5 / LPDDR6; PCIe 7 / CXL 4.0" ], [ "3 nm target; configurable compute foundation", "面向 3 nm；可配置计算基础" ] ], "sources": [ "P06", "P10", "E06" ] } ], "panels": [ [ 0, 1, 2, 3, 4 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "cpu-silicon": { "id": "cpu-silicon", "title": [ "Arm merchant CPU reference SKUs", "Arm 商用 CPU 参考型号" ], "headers": [ [ "Generation / reference SKU", "代际／参考 SKU" ], [ "Codename", "代号" ], [ "GA", "正式商用" ], [ "Status", "状态" ], [ "Core µarch", "核心微架构" ], [ "Cores / threads", "核心／线程" ], [ "Process per die", "各裸片工艺" ], [ "Dies / packaging", "裸片／封装" ], [ "L2 per core", "每核 L2" ], [ "L3 / domain", "L3／共享域" ], [ "Memory: channels; rate; GB/s", "内存：通道；速率；GB/s" ], [ "Sockets / links", "插槽／互联" ], [ "PCIe / CXL", "PCIe／CXL" ], [ "TDP", "TDP" ], [ "Vector / matrix ISA", "向量／矩阵 ISA" ] ], "rows": [ { "id": "agi136", "values": [ [ "AGI CPU 136C", "AGI CPU 136C" ], [ "SP113012", "SP113012" ], [ "2026", "2026" ], [ "Shipping / available", "已商用／可获取" ], [ "Neoverse V3", "Neoverse V3" ], [ "136 / 136", "136 / 136" ], [ "3 nm", "3 nm" ], [ "Arm-designed server SoC", "Arm 自研服务器 SoC" ], [ "2 MB", "2 MB" ], [ "128 MB SLC", "128 MB SLC" ], [ "DDR5; 12; 8800 MT/s; 844.8 GB/s", "DDR5; 12; 8800 MT/s; 844.8 GB/s" ], [ "2S; link rate n/d", "双路；链路速率 n/d" ], [ "96 PCIe 6; CXL 3.0 Type 3", "96 PCIe 6; CXL 3.0 Type 3" ], [ "300 W", "300 W" ], [ "2 x 128-bit SVE2; BF16; INT8 MMLA", "2×128 位 SVE2；BF16；INT8 MMLA" ] ], "sources": [ "P07", "E14", "E15" ] }, { "id": "agi128", "values": [ [ "AGI CPU 128C", "AGI CPU 128C" ], [ "SP113012S", "SP113012S" ], [ "2026", "2026" ], [ "Shipping / available", "已商用／可获取" ], [ "Neoverse V3", "Neoverse V3" ], [ "128 / 128", "128 / 128" ], [ "3 nm", "3 nm" ], [ "Arm-designed server SoC", "Arm 自研服务器 SoC" ], [ "2 MB", "2 MB" ], [ "128 MB SLC", "128 MB SLC" ], [ "DDR5; 12; 8800 MT/s; 844.8 GB/s", "DDR5; 12; 8800 MT/s; 844.8 GB/s" ], [ "2S; link rate n/d", "双路；链路速率 n/d" ], [ "96 PCIe 6; CXL 3.0 Type 3", "96 PCIe 6; CXL 3.0 Type 3" ], [ "300 W", "300 W" ], [ "2 x 128-bit SVE2; BF16; INT8 MMLA", "2×128 位 SVE2；BF16；INT8 MMLA" ] ], "sources": [ "P07", "E14", "E15" ] }, { "id": "agi64", "values": [ [ "AGI CPU 64C", "AGI CPU 64C" ], [ "SP113012A", "SP113012A" ], [ "2026", "2026" ], [ "Shipping / available", "已商用／可获取" ], [ "Neoverse V3", "Neoverse V3" ], [ "64 / 64", "64 / 64" ], [ "3 nm", "3 nm" ], [ "Arm-designed server SoC", "Arm 自研服务器 SoC" ], [ "2 MB", "2 MB" ], [ "128 MB SLC", "128 MB SLC" ], [ "DDR5; 12; 8800 MT/s; 844.8 GB/s", "DDR5; 12; 8800 MT/s; 844.8 GB/s" ], [ "2S; link rate n/d", "双路；链路速率 n/d" ], [ "96 PCIe 6; CXL 3.0 Type 3", "96 PCIe 6; CXL 3.0 Type 3" ], [ "300 W", "300 W" ], [ "2 x 128-bit SVE2; BF16; INT8 MMLA", "2×128 位 SVE2；BF16；INT8 MMLA" ] ], "sources": [ "P07", "E14", "E15" ] } ], "panels": [ [ 0, 1, 2, 3, 4, 5 ], [ 0, 6, 7, 8, 9 ], [ 0, 10, 11, 12, 13, 14 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "interconnect": { "id": "interconnect", "title": [ "Interconnect ownership and semantics", "互联归属与语义" ], "headers": [ [ "Interconnect", "互联" ], [ "Year / generation", "年份／代际" ], [ "Lane rate", "通道速率" ], [ "Lanes / link", "每链路通道" ], [ "GB/s per link per direction", "每链路单向 GB/s" ], [ "Links / device", "每设备链路" ], [ "Topology", "拓扑" ], [ "Domain limit", "域规模" ], [ "Coherence / semantics", "一致性／语义" ] ], "rows": [ { "id": "cmn600", "values": [ [ "CMN-600 / CHI", "CMN-600 / CHI" ], [ "N1", "N1" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "Coherent on-die mesh", "片上一致性网格" ], [ "Implementation-defined", "依实现" ], [ "Cache coherence; system cache", "缓存一致性；系统缓存" ] ], "sources": [ "P01" ] }, { "id": "cmn700", "values": [ [ "CMN-700", "CMN-700" ], [ "N2 / V2", "N2 / V2" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "Coherent mesh; multi-chip integration", "一致性网格；多芯片集成" ], [ "n/d", "n/d" ], [ "CHI", "CHI" ] ], "sources": [ "C02", "C04" ] }, { "id": "cmns3", "values": [ [ "CMN S3 / CHI C2C", "CMN S3 / CHI C2C" ], [ "V3 / N3", "V3 / N3" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "Mesh and chiplet links", "网格与芯粒连接" ], [ "n/d", "n/d" ], [ "Coherent subsystem integration", "一致性子系统集成" ] ], "sources": [ "P09", "P14", "E09" ] }, { "id": "pcie6", "values": [ [ "AGI CPU PCIe 6 / CXL 3", "AGI CPU PCIe 6 / CXL 3" ], [ "2026", "2026" ], [ "64 GT/s", "64 GT/s" ], [ "up to x16", "up to x16" ], [ "~128 raw x16", "~128 raw x16" ], [ "96 lanes total", "96 lanes total" ], [ "Host I/O fabric", "主机 I/O 互联" ], [ "n/d", "n/d" ], [ "PCIe I/O; CXL Type 3 memory", "PCIe I/O；CXL Type 3 内存" ] ], "sources": [ "P07" ] } ], "panels": [ [ 0, 1, 2, 3, 4 ], [ 0, 5, 6, 7, 8 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "network": { "id": "network", "title": [ "Network product boundary", "网络产品边界" ], "headers": [ [ "Product", "产品" ], [ "GA / milestone", "商用／里程碑" ], [ "Status", "状态" ], [ "Class", "类别" ], [ "Ports × speed", "端口×速率" ], [ "SerDes", "SerDes" ], [ "Host interface", "主机接口" ], [ "Programmable engine", "可编程引擎" ], [ "Embedded CPU", "嵌入式 CPU" ], [ "On-card memory", "板载内存" ], [ "Transport / RDMA", "传输／RDMA" ], [ "Congestion control", "拥塞控制" ], [ "Key offloads", "主要卸载" ], [ "Power", "功耗" ] ], "rows": [ { "id": "none", "values": [ [ "No Arm-branded AI NIC established", "未确立 Arm 品牌 AI NIC" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "IP supplier / CPU supplier", "IP／CPU 供应商" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "n/a", "n/a" ], [ "Neoverse licensed to device vendors", "Neoverse 授权给设备厂商" ], [ "n/a", "n/a" ], [ "Licensee-specific", "由被授权方决定" ], [ "n/a", "n/a" ], [ "CPU control; packet engines separate", "CPU 控制；报文引擎单独设计" ], [ "n/a", "n/a" ] ], "sources": [ "E09", "P08" ] } ], "panels": [ [ 0, 1, 2, 3, 4, 5 ], [ 0, 6, 7, 8, 9 ], [ 0, 10, 11, 12, 13 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "accelerators": { "id": "accelerators", "title": [ "Complementary accelerator IP in the common schema", "统一字段中的互补加速器 IP" ], "headers": [ [ "Product", "产品" ], [ "Architecture", "架构" ], [ "GA / milestone", "商用／里程碑" ], [ "Status", "状态" ], [ "Process", "工艺" ], [ "Dies / packaging", "裸片／封装" ], [ "Compute units", "计算单元" ], [ "Dense BF16", "稠密 BF16" ], [ "Dense FP8", "稠密 FP8" ], [ "Dense FP6 / FP4", "稠密 FP6／FP4" ], [ "FP64 vector / matrix", "FP64 向量／矩阵" ], [ "Memory: type; stacks; GB; TB/s", "内存：类型；堆栈；GB；TB/s" ], [ "LLC / SRAM", "末级缓存／SRAM" ], [ "Scale-up: links; GB/s per direction; domain", "纵向扩展：链路；单向 GB/s；域" ], [ "Host link", "主机连接" ], [ "Power / cooling", "功耗／散热" ], [ "Form factor", "形态" ] ], "rows": [ { "id": "n78", "values": [ [ "Ethos-N78", "Ethos-N78" ], [ "Ethos-N", "Ethos-N" ], [ "2020 IP", "2020 IP" ], [ "Licensable IP", "可授权 IP" ], [ "n/a", "n/a" ], [ "Integrated IP", "集成 IP" ], [ "configurable", "configurable" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/a", "n/a" ], [ "HBM n/a; SoC memory", "HBM n/a；SoC 内存" ], [ "n/d", "n/d" ], [ "n/a", "n/a" ], [ "SoC interconnect", "SoC 互联" ], [ "n/a", "n/a" ], [ "IP", "IP" ] ], "sources": [ "E12" ] }, { "id": "u85", "values": [ [ "Ethos-U85", "Ethos-U85" ], [ "Ethos-U", "Ethos-U" ], [ "2024 IP", "2024 IP" ], [ "Licensable IP", "可授权 IP" ], [ "n/a", "n/a" ], [ "Integrated IP", "集成 IP" ], [ "128-2048 MACs", "128-2048 MACs" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/a", "n/a" ], [ "HBM n/a; system SRAM/DRAM", "HBM n/a；系统 SRAM／DRAM" ], [ "n/d", "n/d" ], [ "n/a", "n/a" ], [ "SoC interconnect", "SoC 互联" ], [ "n/a", "n/a" ], [ "IP", "IP" ] ], "sources": [ "P11", "E11" ] }, { "id": "mali", "values": [ [ "Mali G2-Ultra NX", "Mali G2-Ultra NX" ], [ "Mali", "Mali" ], [ "2026 IP", "2026 IP" ], [ "Announced; GA n/d", "已公布；GA n/d" ], [ "n/a", "n/a" ], [ "Mobile GPU IP", "移动 GPU IP" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "HBM n/a; shared SoC memory", "HBM n/a；共享 SoC 内存" ], [ "n/d", "n/d" ], [ "n/a", "n/a" ], [ "SoC interconnect", "SoC 互联" ], [ "n/a", "n/a" ], [ "IP", "IP" ] ], "sources": [ "E10" ] } ], "panels": [ [ 0, 1, 2, 3, 4, 5 ], [ 0, 6, 7, 8, 9, 10 ], [ 0, 11, 12, 13 ], [ 0, 14, 15, 16 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "software": { "id": "software", "title": [ "Software milestones", "软件里程碑" ], "headers": [ [ "Release / component", "版本／组件" ], [ "Date", "日期" ], [ "Hardware enabled", "启用硬件" ], [ "Key features", "主要功能" ] ], "rows": [ { "id": "aarch64", "values": [ [ "AArch64 Linux / GCC / LLVM", "AArch64 Linux / GCC / LLVM" ], [ "2015-2026", "2015-2026" ], [ "Cortex, Neoverse and custom cores", "Cortex、Neoverse 与定制核心" ], [ "Portable binaries; core-specific scheduling and ISA dispatch", "可移植二进制；针对核心的调度与 ISA 分派" ] ], "sources": [ "P08" ] }, { "id": "compute", "values": [ [ "Arm Compute Library", "Arm Compute Library" ], [ "ongoing", "ongoing" ], [ "Arm CPU / Mali", "Arm CPU／Mali" ], [ "Optimized AI operators; feature-dependent paths", "优化 AI 算子；依硬件特性选择路径" ] ], "sources": [ "P13" ] }, { "id": "rd", "values": [ [ "Neoverse reference software", "Neoverse reference software" ], [ "2024 release", "2024 release" ], [ "RD-V3 and related platforms", "RD-V3 及相关平台" ], [ "Firmware and fixed virtual platform integration", "固件与固定虚拟平台集成" ] ], "sources": [ "P14" ] } ], "panels": [ [ 0, 1, 2, 3 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "systems": { "id": "systems", "title": [ "Representative system boundaries", "代表性系统边界" ], "headers": [ [ "Platform", "平台" ], [ "Year / milestone", "年份／里程碑" ], [ "CPU / accelerator count", "CPU／加速器数量" ], [ "Scale-up domain", "纵向扩展域" ], [ "Scale-out per accelerator", "每加速器横向带宽" ], [ "Rack power", "机架功耗" ], [ "Cooling", "散热" ] ], "rows": [ { "id": "licensee", "values": [ [ "Licensee cloud server", "被授权方云服务器" ], [ "2019-2026", "2019-2026" ], [ "Graviton / Axion / Cobalt", "Graviton／Axion／Cobalt" ], [ "Provider-specific", "依云厂商" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ] ], "sources": [ "E08", "E16", "E17", "E18", "E19" ] }, { "id": "agi", "values": [ [ "AGI CPU 1OU dual-node reference", "AGI CPU 1OU 双节点参考平台" ], [ "2026", "2026" ], [ "2 x AGI CPU", "2 x AGI CPU" ], [ "Two independent nodes", "两个独立节点" ], [ "n/d", "n/d" ], [ "36 kW example; 8160 cores", "36 kW 示例；8160 核" ], [ "Air", "风冷" ] ], "sources": [ "P07", "E13" ] }, { "id": "agi2", "values": [ [ "AGI CPU 2U2P reference", "AGI CPU 2U2P 参考平台" ], [ "2026", "2026" ], [ "2 x AGI CPU", "2 x AGI CPU" ], [ "2-socket coherent server", "双插槽一致性服务器" ], [ "n/d", "n/d" ], [ "n/d", "n/d" ], [ "Air", "风冷" ] ], "sources": [ "P07", "E14" ] } ], "panels": [ [ 0, 1, 2, 3 ], [ 0, 4, 5, 6 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "ratios": { "id": "ratios", "title": [ "Derived bandwidth and cache ratios", "带宽与缓存推导比例" ], "headers": [ [ "Configuration", "配置" ], [ "DRAM peak GB/s", "DRAM 峰值 GB/s" ], [ "GB/s/core", "GB/s／核" ], [ "SLC MB/core", "SLC MB／核" ], [ "Meaning", "含义" ] ], "rows": [ { "id": "agi136", "values": [ [ "AGI 136C", "AGI 136C" ], [ "844.8", "844.8" ], [ "6.21", "6.21" ], [ "0.94", "0.94" ], [ "Equal-share ratio; not a reservation", "均分比例；非预留保证" ] ], "sources": [ "P07" ] }, { "id": "agi128", "values": [ [ "AGI 128C", "AGI 128C" ], [ "844.8", "844.8" ], [ "6.60", "6.60" ], [ "1.00", "1.00" ], [ "Same interface, fewer active cores", "相同接口，较少启用核心" ] ], "sources": [ "P07" ] }, { "id": "agi64", "values": [ [ "AGI 64C", "AGI 64C" ], [ "844.8", "844.8" ], [ "13.20", "13.20" ], [ "2.00", "2.00" ], [ "Memory and cache capacity per core increase", "每核内存与缓存资源增加" ] ], "sources": [ "P07" ] }, { "id": "graviton4", "values": [ [ "Graviton4 96C", "Graviton4 96C" ], [ "537.6", "537.6" ], [ "5.60", "5.60" ], [ "n/d", "n/d" ], [ "12 x DDR5-5600; AWS implementation", "12×DDR5-5600；AWS 实现" ] ], "sources": [ "E16" ] } ], "panels": [ [ 0, 1, 2, 3, 4 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "conference": { "id": "conference", "title": [ "Verified disclosure anchors", "已核验披露依据" ], "headers": [ [ "Venue", "会议／活动" ], [ "Year", "年份" ], [ "Paper / talk / disclosure", "论文／演讲／披露" ], [ "Presenter / authors", "报告人／作者" ], [ "Product", "产品" ], [ "Evidence type", "证据类型" ], [ "Source", "来源" ] ], "rows": [ { "id": "n1hc", "values": [ [ "Hot Chips", "Hot Chips" ], [ "2019", "2019" ], [ "Neoverse N1 Cloud-to-Edge Infrastructure SoCs", "Neoverse N1 Cloud-to-Edge Infrastructure SoCs" ], [ "Arm", "Arm" ], [ "N1", "N1" ], [ "Architecture", "架构" ], [ "P01", "P01" ] ], "sources": [ "P01" ] }, { "id": "n1isscc", "values": [ [ "ISSCC", "ISSCC" ], [ "2020", "2020" ], [ "A 3GHz Arm Neoverse N1 CPU in 7nm FinFET for Infrastructure Applications", "A 3GHz Arm Neoverse N1 CPU in 7nm FinFET for Infrastructure Applications" ], [ "R. Christy et al.", "R. Christy et al." ], [ "N1", "N1" ], [ "Circuit / implementation", "电路／实现" ], [ "C01", "C01" ] ], "sources": [ "C01" ] }, { "id": "n2hc", "values": [ [ "Hot Chips", "Hot Chips" ], [ "2021", "2021" ], [ "Arm Neoverse N2: 2nd generation infrastructure CPUs and system IPs", "Arm Neoverse N2: 2nd generation infrastructure CPUs and system IPs" ], [ "A. Pellegrini", "A. Pellegrini" ], [ "N2 / CMN-700", "N2 / CMN-700" ], [ "Architecture", "架构" ], [ "C04", "C04" ] ], "sources": [ "C04" ] }, { "id": "v2hc", "values": [ [ "Hot Chips", "Hot Chips" ], [ "2023", "2023" ], [ "Arm Neoverse V2 Platform", "Arm Neoverse V2 Platform" ], [ "Magnus Bruce", "Magnus Bruce" ], [ "V2", "V2" ], [ "Architecture", "架构" ], [ "C02", "C02" ] ], "sources": [ "C02" ] }, { "id": "csshc", "values": [ [ "Hot Chips", "Hot Chips" ], [ "2023", "2023" ], [ "Neoverse Compute Subsystems launch", "Neoverse Compute Subsystems launch" ], [ "Arm", "Arm" ], [ "CSS N2", "CSS N2" ], [ "Subsystem", "子系统" ], [ "E03", "E03" ] ], "sources": [ "E03" ] }, { "id": "agihc", "values": [ [ "Hot Chips", "Hot Chips" ], [ "2026", "2026" ], [ "Arm AGI CPU architecture disclosure", "Arm AGI CPU architecture disclosure" ], [ "Arm", "Arm" ], [ "AGI CPU", "AGI CPU" ], [ "Architecture / system", "架构／系统" ], [ "C03", "C03" ] ], "sources": [ "C03" ] }, { "id": "isca", "values": [ [ "ISCA", "ISCA" ], [ "2019 / 2024", "2019 / 2024" ], [ "MISB; Triangel", "MISB; Triangel" ], [ "Arm / academic researchers", "Arm / academic researchers" ], [ "Related memory research", "Related memory research" ], [ "Related research", "相关研究" ], [ "R06 R03", "R06 R03" ] ], "sources": [ "R06", "R03" ] }, { "id": "micro", "values": [ [ "MICRO", "MICRO" ], [ "2019", "2019" ], [ "Temporal Prefetching Without the Off-Chip Metadata", "Temporal Prefetching Without the Off-Chip Metadata" ], [ "Wu et al.", "Wu et al." ], [ "Related memory research", "Related memory research" ], [ "Related research", "相关研究" ], [ "R05", "R05" ] ], "sources": [ "R05" ] }, { "id": "hpca", "values": [ [ "HPCA", "HPCA" ], [ "2025", "2025" ], [ "Criticality-Aware Instruction-Centric Bandwidth Partitioning", "Criticality-Aware Instruction-Centric Bandwidth Partitioning" ], [ "Paper authors", "Paper authors" ], [ "Resource partitioning", "Resource partitioning" ], [ "Related research", "相关研究" ], [ "R04", "R04" ] ], "sources": [ "R04" ] }, { "id": "asplos", "values": [ [ "ASPLOS", "ASPLOS" ], [ "2025", "2025" ], [ "Hierarchical Prefetching", "Hierarchical Prefetching" ], [ "Zhang et al.", "Zhang et al." ], [ "Instruction supply", "Instruction supply" ], [ "Related research", "相关研究" ], [ "R07", "R07" ] ], "sources": [ "R07" ] }, { "id": "ignite", "values": [ [ "Microsoft Ignite / Build", "Microsoft Ignite / Build" ], [ "2025 / 2026", "2025 / 2026" ], [ "Cobalt 200 disclosure and preview", "Cobalt 200 disclosure and preview" ], [ "Microsoft", "Microsoft" ], [ "CSS V3 implementation", "CSS V3 implementation" ], [ "Partner deployment", "合作伙伴部署" ], [ "E07 E18 E20", "E07 E18 E20" ] ], "sources": [ "E07", "E18", "E20" ] }, { "id": "next", "values": [ [ "Google Cloud Next", "Google Cloud Next" ], [ "2024", "2024" ], [ "Google Axion introduction", "Google Axion introduction" ], [ "Google", "Google" ], [ "V2 implementation", "V2 implementation" ], [ "Partner deployment", "合作伙伴部署" ], [ "E17", "E17" ] ], "sources": [ "E17" ] }, { "id": "reinvent", "values": [ [ "AWS re:Invent / EC2 launches", "AWS re:Invent / EC2 launches" ], [ "2023-2026", "2023-2026" ], [ "Graviton4 / Graviton5", "Graviton4 / Graviton5" ], [ "AWS", "AWS" ], [ "V2 / V3 implementations", "V2 / V3 implementations" ], [ "Partner deployment", "合作伙伴部署" ], [ "E16 E19", "E16 E19" ] ], "sources": [ "E16", "E19" ] }, { "id": "everywhere", "values": [ [ "Arm Everywhere", "Arm Everywhere" ], [ "2026", "2026" ], [ "AGI CPU and CSS N4", "AGI CPU and CSS N4" ], [ "Arm", "Arm" ], [ "Merchant CPU / IP", "Merchant CPU / IP" ], [ "Product launch", "产品发布" ], [ "E05 E06", "E05 E06" ] ], "sources": [ "E05", "E06" ] } ], "panels": [ [ 0, 1, 2, 3 ], [ 0, 4, 5, 6 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "crosswalk": { "id": "crosswalk", "title": [ "Names that must not be conflated", "需要区分的名称" ], "headers": [ [ "Name", "名称" ], [ "Meaning", "含义" ], [ "Owner / boundary", "归属／边界" ] ], "rows": [ { "id": "ares", "values": [ [ "Ares / N1", "Ares / N1" ], [ "Core IP generation", "核心 IP 代际" ], [ "Arm", "Arm" ] ], "sources": [ "P01", "E01" ] }, { "id": "zeus", "values": [ [ "Zeus / V1", "Zeus / V1" ], [ "Vector-oriented core IP", "面向向量性能的核心 IP" ], [ "Arm", "Arm" ] ], "sources": [ "P02" ] }, { "id": "perseus", "values": [ [ "Perseus / N2", "Perseus / N2" ], [ "Density-oriented Armv9 core", "面向密度的 Armv9 核心" ], [ "Arm", "Arm" ] ], "sources": [ "P08" ] }, { "id": "demeter", "values": [ [ "Demeter / V2", "Demeter / V2" ], [ "Core used by Grace, Axion and Graviton4", "Grace、Axion、Graviton4 使用的核心" ], [ "Arm core; partner SoCs", "Arm 核心；合作伙伴 SoC" ] ], "sources": [ "C02", "E08" ] }, { "id": "css", "values": [ [ "CSS", "CSS" ], [ "Preintegrated compute subsystem", "预集成计算子系统" ], [ "Not a complete merchant chip", "不是完整商用芯片" ] ], "sources": [ "E03" ] }, { "id": "agi", "values": [ [ "AGI CPU", "AGI CPU" ], [ "Arm-designed server silicon", "Arm 自研服务器芯片" ], [ "V3-based; not CSS N4", "基于 V3；不是 CSS N4" ] ], "sources": [ "P07", "E06" ] }, { "id": "custom", "values": [ [ "Falkor / Oryon / AmpereOne / Vera", "Falkor／Oryon／AmpereOne／Vera" ], [ "Custom Arm-compatible cores or products", "定制 Arm 兼容核心或产品" ], [ "Licensee designs; not Neoverse aliases", "被授权方设计；不是 Neoverse 别名" ] ], "sources": [ "C03", "E08" ] } ], "panels": [ [ 0, 1, 2 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" }, "hierarchy": { "id": "hierarchy", "title": [ "Bandwidth hierarchy by era", "各时代带宽层次" ], "headers": [ [ "Era", "时代" ], [ "On-die / die-to-die", "片上／裸片间" ], [ "Memory", "内存" ], [ "Host attach", "主机连接" ], [ "Scale-up / scale-out", "纵向／横向扩展" ] ], "rows": [ { "id": "early", "values": [ [ "2015-2018", "2015-2018" ], [ "Licensee fabric", "被授权方互联" ], [ "Licensee DDR", "被授权方 DDR" ], [ "PCIe; n/d", "PCIe; n/d" ], [ "Licensee network; n/d", "被授权方网络；n/d" ] ], "sources": [ "E08" ] }, { "id": "n1", "values": [ [ "2019-2022", "2019-2022" ], [ "CMN-600/700; n/d", "CMN-600/700; n/d" ], [ "Partner-configured DDR; n/d", "合作伙伴配置 DDR；n/d" ], [ "PCIe / CCIX; n/d", "PCIe / CCIX; n/d" ], [ "No universal Arm link", "无通用 Arm 链路" ] ], "sources": [ "P01", "C04" ] }, { "id": "css", "values": [ [ "2023-2025", "2023-2025" ], [ "CMN / CHI C2C; n/d", "CMN / CHI C2C; n/d" ], [ "Graviton4: 537.6 GB/s peak", "Graviton4：537.6 GB/s 峰值" ], [ "Grace C2C is NVIDIA-owned", "Grace C2C 属于 NVIDIA" ], [ "Partner-specific", "依合作伙伴" ] ], "sources": [ "E16", "P15", "E09" ] }, { "id": "agi", "values": [ [ "2026", "2026" ], [ "CMN; D2D n/d", "CMN; D2D n/d" ], [ "AGI: 844.8 GB/s derived peak", "AGI：844.8 GB/s 推导峰值" ], [ "PCIe 6 x16 ~128 GB/s raw", "PCIe 6 x16 ~128 GB/s raw" ], [ "External XPU/NIC; n/d", "外部 XPU／NIC；n/d" ] ], "sources": [ "P07" ] } ], "panels": [ [ 0, 1, 2, 3, 4 ] ], "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled" } }, "figures": { "early": { "id": "early", "title": [ "2015-2018: ISA and partner integration", "2015—2018：ISA 与合作伙伴集成" ], "nodes": [ [ "n0", [ "Arm ISA / Cortex IP", "Arm ISA／Cortex IP" ], 0, 0 ], [ "n1", [ "Custom Arm cores", "定制 Arm 核心" ], 1, 0 ], [ "n2", [ "Partner server SoC", "合作伙伴服务器 SoC" ], 0, 1 ], [ "n3", [ "DDR / PCIe / NIC", "DDR／PCIe／NIC" ], 1, 1 ], [ "n4", [ "Linux / firmware", "Linux／固件" ], 0, 2 ], [ "n5", [ "Cloud / edge services", "云／边缘服务" ], 1, 2 ] ], "edges": [ [ "n0", "n2", [ "design", "设计" ] ], [ "n1", "n3", [ "integration", "集成" ] ], [ "n2", "n4", [ "enable", "启用" ] ], [ "n3", "n5", [ "compose", "组成" ] ], [ "n4", "n5", [ "software", "软件" ] ] ], "caption": [ "Conceptual ownership and integration map; partner GPU and network bandwidth is not attributed to Arm.", "概念性归属与集成图；合作伙伴 GPU 和网络带宽不归入 Arm。" ] }, "n1era": { "id": "n1era", "title": [ "2019-2022: Neoverse platforms", "2019—2022：Neoverse 平台" ], "nodes": [ [ "n0", [ "N1 / V1 / N2", "N1／V1／N2" ], 0, 0 ], [ "n1", [ "CMN + system IP", "CMN＋系统 IP" ], 1, 0 ], [ "n2", [ "Graviton / Altra / partners", "Graviton／Altra／合作伙伴" ], 0, 1 ], [ "n3", [ "DDR + external accelerators", "DDR＋外部加速器" ], 1, 1 ], [ "n4", [ "Linux / SVE libraries", "Linux／SVE 库" ], 0, 2 ], [ "n5", [ "Cloud / HPC / networking", "云／HPC／网络" ], 1, 2 ] ], "edges": [ [ "n0", "n2", [ "design", "设计" ] ], [ "n1", "n3", [ "integration", "集成" ] ], [ "n2", "n4", [ "enable", "启用" ] ], [ "n3", "n5", [ "compose", "组成" ] ], [ "n4", "n5", [ "software", "软件" ] ] ], "caption": [ "Conceptual ownership and integration map; partner GPU and network bandwidth is not attributed to Arm.", "概念性归属与集成图；合作伙伴 GPU 和网络带宽不归入 Arm。" ] }, "cssera": { "id": "cssera", "title": [ "2023-2025: CSS and heterogeneous hosts", "2023—2025：CSS 与异构主机" ], "nodes": [ [ "n0", [ "V2 / V3 / N3 + CSS", "V2／V3／N3＋CSS" ], 0, 0 ], [ "n1", [ "CMN / CHI C2C", "CMN／CHI C2C" ], 1, 0 ], [ "n2", [ "Grace / Axion / Cobalt", "Grace／Axion／Cobalt" ], 0, 1 ], [ "n3", [ "Partner GPUs / DPUs", "合作伙伴 GPU／DPU" ], 1, 1 ], [ "n4", [ "Firmware / optimized kernels", "固件／优化内核" ], 0, 2 ], [ "n5", [ "Cloud AI / coherent systems", "云 AI／一致性系统" ], 1, 2 ] ], "edges": [ [ "n0", "n2", [ "design", "设计" ] ], [ "n1", "n3", [ "integration", "集成" ] ], [ "n2", "n4", [ "enable", "启用" ] ], [ "n3", "n5", [ "compose", "组成" ] ], [ "n4", "n5", [ "software", "软件" ] ] ], "caption": [ "Conceptual ownership and integration map; partner GPU and network bandwidth is not attributed to Arm.", "概念性归属与集成图；合作伙伴 GPU 和网络带宽不归入 Arm。" ] }, "current": { "id": "current", "title": [ "2026: IP and merchant silicon coexist", "2026：IP 与商用芯片并行" ], "nodes": [ [ "n0", [ "CSS N4 licensable IP", "CSS N4 授权 IP" ], 0, 0 ], [ "n1", [ "AGI CPU, V3-based", "基于 V3 的 AGI CPU" ], 1, 0 ], [ "n2", [ "Custom partner silicon", "合作伙伴定制芯片" ], 0, 1 ], [ "n3", [ "DDR5 / PCIe 6 / CXL 3", "DDR5／PCIe 6／CXL 3" ], 1, 1 ], [ "n4", [ "OS / runtimes / management", "操作系统／运行时／管理" ], 0, 2 ], [ "n5", [ "OEM racks + partner XPUs", "OEM 机架＋合作伙伴 XPU" ], 1, 2 ] ], "edges": [ [ "n0", "n2", [ "design", "设计" ] ], [ "n1", "n3", [ "integration", "集成" ] ], [ "n2", "n4", [ "enable", "启用" ] ], [ "n3", "n5", [ "compose", "组成" ] ], [ "n4", "n5", [ "software", "软件" ] ] ], "caption": [ "Conceptual ownership and integration map; partner GPU and network bandwidth is not attributed to Arm.", "概念性归属与集成图；合作伙伴 GPU 和网络带宽不归入 Arm。" ] } }, "claims": { "cpu-ip.n1.0": { "value": "Neoverse N1 / Ares", "field": "Generation / reference SKU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "n1" }, "cpu-ip.n1.1": { "value": "Ares", "field": "Codename", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "n1" }, "cpu-ip.n1.2": { "value": "2019 IP disclosure", "field": "GA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "n1" }, "cpu-ip.n1.3": { "value": "Licensable IP", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "n1" }, "cpu-ip.n1.4": { "value": "N1", "field": "Core µarch", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "n1" }, "cpu-ip.n1.5": { "value": "Configurable; E1 SMT2; N4 threads n/d; others single-threaded", "field": "Cores / threads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "n1" }, "cpu-ip.n1.6": { "value": "Licensee-defined; N4 targets 3 nm", "field": "Process per die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "n1" }, "cpu-ip.n1.7": { "value": "IP, not a packaged SKU", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "n1" }, "cpu-ip.n1.8": { "value": "512 KB / 1 MB", "field": "L2 per core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "n1" }, "cpu-ip.n1.9": { "value": "System configuration", "field": "L3 / domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "n1" }, "cpu-ip.n1.10": { "value": "Implementation-defined", "field": "Memory: channels; rate; GB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "n1" }, "cpu-ip.n1.11": { "value": "n/a", "field": "Sockets / links", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "n1" }, "cpu-ip.n1.12": { "value": "System integration", "field": "PCIe / CXL", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "n1" }, "cpu-ip.n1.13": { "value": "n/a", "field": "TDP", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "n1" }, "cpu-ip.n1.14": { "value": "Armv8.2-A; NEON 128-bit", "field": "Vector / matrix ISA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "n1" }, "cpu-ip.e1.0": { "value": "Neoverse E1", "field": "Generation / reference SKU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "e1" }, "cpu-ip.e1.1": { "value": "n/d", "field": "Codename", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "e1" }, "cpu-ip.e1.2": { "value": "2019 IP disclosure", "field": "GA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "e1" }, "cpu-ip.e1.3": { "value": "Licensable IP", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "e1" }, "cpu-ip.e1.4": { "value": "E1", "field": "Core µarch", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "e1" }, "cpu-ip.e1.5": { "value": "Configurable; E1 SMT2; N4 threads n/d; others single-threaded", "field": "Cores / threads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "e1" }, "cpu-ip.e1.6": { "value": "Licensee-defined; N4 targets 3 nm", "field": "Process per die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "e1" }, "cpu-ip.e1.7": { "value": "IP, not a packaged SKU", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "e1" }, "cpu-ip.e1.8": { "value": "n/d", "field": "L2 per core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "e1" }, "cpu-ip.e1.9": { "value": "System configuration", "field": "L3 / domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "e1" }, "cpu-ip.e1.10": { "value": "Implementation-defined", "field": "Memory: channels; rate; GB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "e1" }, "cpu-ip.e1.11": { "value": "n/a", "field": "Sockets / links", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "e1" }, "cpu-ip.e1.12": { "value": "System integration", "field": "PCIe / CXL", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "e1" }, "cpu-ip.e1.13": { "value": "n/a", "field": "TDP", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "e1" }, "cpu-ip.e1.14": { "value": "Armv8.2-A; NEON; SMT2", "field": "Vector / matrix ISA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "e1" }, "cpu-ip.v1.0": { "value": "Neoverse V1 / Zeus", "field": "Generation / reference SKU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P02", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "v1" }, "cpu-ip.v1.1": { "value": "Zeus", "field": "Codename", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P02", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "v1" }, "cpu-ip.v1.2": { "value": "2020-2021 IP disclosure", "field": "GA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P02", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "v1" }, "cpu-ip.v1.3": { "value": "Licensable IP", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P02", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "v1" }, "cpu-ip.v1.4": { "value": "V1", "field": "Core µarch", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P02", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "v1" }, "cpu-ip.v1.5": { "value": "Configurable; E1 SMT2; N4 threads n/d; others single-threaded", "field": "Cores / threads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P02", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "v1" }, "cpu-ip.v1.6": { "value": "Licensee-defined; N4 targets 3 nm", "field": "Process per die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P02", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "v1" }, "cpu-ip.v1.7": { "value": "IP, not a packaged SKU", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P02", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "v1" }, "cpu-ip.v1.8": { "value": "512 KB / 1 MB", "field": "L2 per core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P02", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "v1" }, "cpu-ip.v1.9": { "value": "System configuration", "field": "L3 / domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P02", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "v1" }, "cpu-ip.v1.10": { "value": "Implementation-defined", "field": "Memory: channels; rate; GB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P02", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "v1" }, "cpu-ip.v1.11": { "value": "n/a", "field": "Sockets / links", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P02", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "v1" }, "cpu-ip.v1.12": { "value": "System integration", "field": "PCIe / CXL", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P02", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "v1" }, "cpu-ip.v1.13": { "value": "n/a", "field": "TDP", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P02", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "v1" }, "cpu-ip.v1.14": { "value": "SVE: 2 x 256-bit; BF16; INT8", "field": "Vector / matrix ISA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P02", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "v1" }, "cpu-ip.n2.0": { "value": "Neoverse N2 / Perseus", "field": "Generation / reference SKU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P03", "P08", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "n2" }, "cpu-ip.n2.1": { "value": "Perseus", "field": "Codename", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P03", "P08", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "n2" }, "cpu-ip.n2.2": { "value": "2020-2021 IP disclosure", "field": "GA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P03", "P08", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "n2" }, "cpu-ip.n2.3": { "value": "Licensable IP", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P03", "P08", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "n2" }, "cpu-ip.n2.4": { "value": "N2", "field": "Core µarch", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P03", "P08", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "n2" }, "cpu-ip.n2.5": { "value": "Configurable; E1 SMT2; N4 threads n/d; others single-threaded", "field": "Cores / threads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P03", "P08", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "n2" }, "cpu-ip.n2.6": { "value": "Licensee-defined; N4 targets 3 nm", "field": "Process per die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P03", "P08", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "n2" }, "cpu-ip.n2.7": { "value": "IP, not a packaged SKU", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P03", "P08", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "n2" }, "cpu-ip.n2.8": { "value": "512 KB / 1 MB", "field": "L2 per core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P03", "P08", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "n2" }, "cpu-ip.n2.9": { "value": "System configuration", "field": "L3 / domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P03", "P08", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "n2" }, "cpu-ip.n2.10": { "value": "Implementation-defined", "field": "Memory: channels; rate; GB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P03", "P08", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "n2" }, "cpu-ip.n2.11": { "value": "n/a", "field": "Sockets / links", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P03", "P08", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "n2" }, "cpu-ip.n2.12": { "value": "System integration", "field": "PCIe / CXL", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P03", "P08", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "n2" }, "cpu-ip.n2.13": { "value": "n/a", "field": "TDP", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P03", "P08", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "n2" }, "cpu-ip.n2.14": { "value": "Armv9; SVE2 128-bit; BF16", "field": "Vector / matrix ISA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P03", "P08", "E02" ], "disclosure_date": "2020-2021", "status": "licensable IP", "scope": "n2" }, "cpu-ip.v2.0": { "value": "Neoverse V2 / Demeter", "field": "Generation / reference SKU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2022-2023", "status": "licensable IP", "scope": "v2" }, "cpu-ip.v2.1": { "value": "Demeter", "field": "Codename", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2022-2023", "status": "licensable IP", "scope": "v2" }, "cpu-ip.v2.2": { "value": "2022-2023 IP disclosure", "field": "GA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2022-2023", "status": "licensable IP", "scope": "v2" }, "cpu-ip.v2.3": { "value": "Licensable IP", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2022-2023", "status": "licensable IP", "scope": "v2" }, "cpu-ip.v2.4": { "value": "V2", "field": "Core µarch", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2022-2023", "status": "licensable IP", "scope": "v2" }, "cpu-ip.v2.5": { "value": "Configurable; E1 SMT2; N4 threads n/d; others single-threaded", "field": "Cores / threads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2022-2023", "status": "licensable IP", "scope": "v2" }, "cpu-ip.v2.6": { "value": "Licensee-defined; N4 targets 3 nm", "field": "Process per die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2022-2023", "status": "licensable IP", "scope": "v2" }, "cpu-ip.v2.7": { "value": "IP, not a packaged SKU", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2022-2023", "status": "licensable IP", "scope": "v2" }, "cpu-ip.v2.8": { "value": "1 / 2 MB", "field": "L2 per core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2022-2023", "status": "licensable IP", "scope": "v2" }, "cpu-ip.v2.9": { "value": "System configuration", "field": "L3 / domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2022-2023", "status": "licensable IP", "scope": "v2" }, "cpu-ip.v2.10": { "value": "Implementation-defined", "field": "Memory: channels; rate; GB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2022-2023", "status": "licensable IP", "scope": "v2" }, "cpu-ip.v2.11": { "value": "n/a", "field": "Sockets / links", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2022-2023", "status": "licensable IP", "scope": "v2" }, "cpu-ip.v2.12": { "value": "System integration", "field": "PCIe / CXL", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2022-2023", "status": "licensable IP", "scope": "v2" }, "cpu-ip.v2.13": { "value": "n/a", "field": "TDP", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2022-2023", "status": "licensable IP", "scope": "v2" }, "cpu-ip.v2.14": { "value": "Armv9; SVE2 128-bit; 4 vector pipes", "field": "Vector / matrix ISA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "P08" ], "disclosure_date": "2022-2023", "status": "licensable IP", "scope": "v2" }, "cpu-ip.v3.0": { "value": "Neoverse V3", "field": "Generation / reference SKU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "v3" }, "cpu-ip.v3.1": { "value": "n/d", "field": "Codename", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "v3" }, "cpu-ip.v3.2": { "value": "2024 IP disclosure", "field": "GA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "v3" }, "cpu-ip.v3.3": { "value": "Licensable IP", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "v3" }, "cpu-ip.v3.4": { "value": "V3", "field": "Core µarch", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "v3" }, "cpu-ip.v3.5": { "value": "Configurable; E1 SMT2; N4 threads n/d; others single-threaded", "field": "Cores / threads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "v3" }, "cpu-ip.v3.6": { "value": "Licensee-defined; N4 targets 3 nm", "field": "Process per die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "v3" }, "cpu-ip.v3.7": { "value": "IP, not a packaged SKU", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "v3" }, "cpu-ip.v3.8": { "value": "2 / 3 MB", "field": "L2 per core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "v3" }, "cpu-ip.v3.9": { "value": "System configuration", "field": "L3 / domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "v3" }, "cpu-ip.v3.10": { "value": "Implementation-defined", "field": "Memory: channels; rate; GB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "v3" }, "cpu-ip.v3.11": { "value": "n/a", "field": "Sockets / links", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "v3" }, "cpu-ip.v3.12": { "value": "System integration", "field": "PCIe / CXL", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "v3" }, "cpu-ip.v3.13": { "value": "n/a", "field": "TDP", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "v3" }, "cpu-ip.v3.14": { "value": "Armv9.2-A; SVE2; CCA", "field": "Vector / matrix ISA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P04", "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "v3" }, "cpu-ip.n3.0": { "value": "Neoverse N3", "field": "Generation / reference SKU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "n3" }, "cpu-ip.n3.1": { "value": "n/d", "field": "Codename", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "n3" }, "cpu-ip.n3.2": { "value": "2024 IP disclosure", "field": "GA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "n3" }, "cpu-ip.n3.3": { "value": "Licensable IP", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "n3" }, "cpu-ip.n3.4": { "value": "N3", "field": "Core µarch", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "n3" }, "cpu-ip.n3.5": { "value": "Configurable; E1 SMT2; N4 threads n/d; others single-threaded", "field": "Cores / threads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "n3" }, "cpu-ip.n3.6": { "value": "Licensee-defined; N4 targets 3 nm", "field": "Process per die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "n3" }, "cpu-ip.n3.7": { "value": "IP, not a packaged SKU", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "n3" }, "cpu-ip.n3.8": { "value": "128 KB - 2 MB", "field": "L2 per core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "n3" }, "cpu-ip.n3.9": { "value": "System configuration", "field": "L3 / domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "n3" }, "cpu-ip.n3.10": { "value": "Implementation-defined", "field": "Memory: channels; rate; GB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "n3" }, "cpu-ip.n3.11": { "value": "n/a", "field": "Sockets / links", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "n3" }, "cpu-ip.n3.12": { "value": "System integration", "field": "PCIe / CXL", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "n3" }, "cpu-ip.n3.13": { "value": "n/a", "field": "TDP", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "n3" }, "cpu-ip.n3.14": { "value": "Armv9.2-A; SVE2", "field": "Vector / matrix ISA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "n3" }, "cpu-ip.n4.0": { "value": "CSS N4", "field": "Generation / reference SKU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P10", "E06" ], "disclosure_date": "2026-09", "status": "licensable IP", "scope": "n4" }, "cpu-ip.n4.1": { "value": "n/d", "field": "Codename", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P10", "E06" ], "disclosure_date": "2026-09", "status": "licensable IP", "scope": "n4" }, "cpu-ip.n4.2": { "value": "2026-09 IP disclosure", "field": "GA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P10", "E06" ], "disclosure_date": "2026-09", "status": "licensable IP", "scope": "n4" }, "cpu-ip.n4.3": { "value": "Licensable IP", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P10", "E06" ], "disclosure_date": "2026-09", "status": "licensable IP", "scope": "n4" }, "cpu-ip.n4.4": { "value": "N4", "field": "Core µarch", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P10", "E06" ], "disclosure_date": "2026-09", "status": "licensable IP", "scope": "n4" }, "cpu-ip.n4.5": { "value": "Configurable; E1 SMT2; N4 threads n/d; others single-threaded", "field": "Cores / threads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P10", "E06" ], "disclosure_date": "2026-09", "status": "licensable IP", "scope": "n4" }, "cpu-ip.n4.6": { "value": "Licensee-defined; N4 targets 3 nm", "field": "Process per die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P10", "E06" ], "disclosure_date": "2026-09", "status": "licensable IP", "scope": "n4" }, "cpu-ip.n4.7": { "value": "IP, not a packaged SKU", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P10", "E06" ], "disclosure_date": "2026-09", "status": "licensable IP", "scope": "n4" }, "cpu-ip.n4.8": { "value": "up to 2 MB", "field": "L2 per core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P10", "E06" ], "disclosure_date": "2026-09", "status": "licensable IP", "scope": "n4" }, "cpu-ip.n4.9": { "value": "System configuration", "field": "L3 / domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P10", "E06" ], "disclosure_date": "2026-09", "status": "licensable IP", "scope": "n4" }, "cpu-ip.n4.10": { "value": "Implementation-defined", "field": "Memory: channels; rate; GB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P10", "E06" ], "disclosure_date": "2026-09", "status": "licensable IP", "scope": "n4" }, "cpu-ip.n4.11": { "value": "n/a", "field": "Sockets / links", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P10", "E06" ], "disclosure_date": "2026-09", "status": "licensable IP", "scope": "n4" }, "cpu-ip.n4.12": { "value": "System integration", "field": "PCIe / CXL", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P10", "E06" ], "disclosure_date": "2026-09", "status": "licensable IP", "scope": "n4" }, "cpu-ip.n4.13": { "value": "n/a", "field": "TDP", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P10", "E06" ], "disclosure_date": "2026-09", "status": "licensable IP", "scope": "n4" }, "cpu-ip.n4.14": { "value": "Armv9; details n/d", "field": "Vector / matrix ISA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P10", "E06" ], "disclosure_date": "2026-09", "status": "licensable IP", "scope": "n4" }, "css.cssn2.0": { "value": "CSS N2", "field": "Subsystem", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2023", "status": "licensable IP", "scope": "cssn2" }, "css.cssn2.1": { "value": "2023", "field": "Disclosure", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2023", "status": "licensable IP", "scope": "cssn2" }, "css.cssn2.2": { "value": "Up to 64 N2", "field": "Core envelope", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2023", "status": "licensable IP", "scope": "cssn2" }, "css.cssn2.3": { "value": "DDR5/LPDDR5; PCIe 5 / CXL", "field": "Memory / I/O", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2023", "status": "licensable IP", "scope": "cssn2" }, "css.cssn2.4": { "value": "Prevalidated CPU and system design", "field": "Integration meaning", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2023", "status": "licensable IP", "scope": "cssn2" }, "css.cssv3.0": { "value": "CSS V3", "field": "Subsystem", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "cssv3" }, "css.cssv3.1": { "value": "2024", "field": "Disclosure", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "cssv3" }, "css.cssv3.2": { "value": "Up to 64 V3 per subsystem", "field": "Core envelope", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "cssv3" }, "css.cssv3.3": { "value": "up to 12 memory channels; 64 PCIe 5/CXL lanes", "field": "Memory / I/O", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "cssv3" }, "css.cssv3.4": { "value": "Chiplet-ready; CCA support", "field": "Integration meaning", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09", "E04" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "cssv3" }, "css.cssn3.0": { "value": "CSS N3", "field": "Subsystem", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E04", "E09", "P08" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "cssn3" }, "css.cssn3.1": { "value": "2024", "field": "Disclosure", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E04", "E09", "P08" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "cssn3" }, "css.cssn3.2": { "value": "Configurable N3 subsystem", "field": "Core envelope", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E04", "E09", "P08" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "cssn3" }, "css.cssn3.3": { "value": "CMN S3; CHI C2C", "field": "Memory / I/O", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E04", "E09", "P08" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "cssn3" }, "css.cssn3.4": { "value": "Cloud, networking, DPU and edge customization", "field": "Integration meaning", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E04", "E09", "P08" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "cssn3" }, "css.cssn4.0": { "value": "CSS N4", "field": "Subsystem", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P10", "E06" ], "disclosure_date": "2026-09", "status": "announced IP", "scope": "cssn4" }, "css.cssn4.1": { "value": "2026-09", "field": "Disclosure", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P10", "E06" ], "disclosure_date": "2026-09", "status": "announced IP", "scope": "cssn4" }, "css.cssn4.2": { "value": "Up to 128 N4 per die", "field": "Core envelope", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P10", "E06" ], "disclosure_date": "2026-09", "status": "announced IP", "scope": "cssn4" }, "css.cssn4.3": { "value": "DDR5 / LPDDR6; PCIe 7 / CXL 4.0", "field": "Memory / I/O", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P10", "E06" ], "disclosure_date": "2026-09", "status": "announced IP", "scope": "cssn4" }, "css.cssn4.4": { "value": "3 nm target; configurable compute foundation", "field": "Integration meaning", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P06", "P10", "E06" ], "disclosure_date": "2026-09", "status": "announced IP", "scope": "cssn4" }, "cpu-silicon.agi136.0": { "value": "AGI CPU 136C", "field": "Generation / reference SKU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi136" }, "cpu-silicon.agi136.1": { "value": "SP113012", "field": "Codename", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi136" }, "cpu-silicon.agi136.2": { "value": "2026", "field": "GA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi136" }, "cpu-silicon.agi136.3": { "value": "Shipping / available", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi136" }, "cpu-silicon.agi136.4": { "value": "Neoverse V3", "field": "Core µarch", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi136" }, "cpu-silicon.agi136.5": { "value": "136 / 136", "field": "Cores / threads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi136" }, "cpu-silicon.agi136.6": { "value": "3 nm", "field": "Process per die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi136" }, "cpu-silicon.agi136.7": { "value": "Arm-designed server SoC", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi136" }, "cpu-silicon.agi136.8": { "value": "2 MB", "field": "L2 per core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi136" }, "cpu-silicon.agi136.9": { "value": "128 MB SLC", "field": "L3 / domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi136" }, "cpu-silicon.agi136.10": { "value": "DDR5; 12; 8800 MT/s; 844.8 GB/s", "field": "Memory: channels; rate; GB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi136" }, "cpu-silicon.agi136.11": { "value": "2S; link rate n/d", "field": "Sockets / links", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi136" }, "cpu-silicon.agi136.12": { "value": "96 PCIe 6; CXL 3.0 Type 3", "field": "PCIe / CXL", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi136" }, "cpu-silicon.agi136.13": { "value": "300 W", "field": "TDP", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi136" }, "cpu-silicon.agi136.14": { "value": "2 x 128-bit SVE2; BF16; INT8 MMLA", "field": "Vector / matrix ISA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi136" }, "cpu-silicon.agi128.0": { "value": "AGI CPU 128C", "field": "Generation / reference SKU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi128" }, "cpu-silicon.agi128.1": { "value": "SP113012S", "field": "Codename", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi128" }, "cpu-silicon.agi128.2": { "value": "2026", "field": "GA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi128" }, "cpu-silicon.agi128.3": { "value": "Shipping / available", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi128" }, "cpu-silicon.agi128.4": { "value": "Neoverse V3", "field": "Core µarch", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi128" }, "cpu-silicon.agi128.5": { "value": "128 / 128", "field": "Cores / threads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi128" }, "cpu-silicon.agi128.6": { "value": "3 nm", "field": "Process per die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi128" }, "cpu-silicon.agi128.7": { "value": "Arm-designed server SoC", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi128" }, "cpu-silicon.agi128.8": { "value": "2 MB", "field": "L2 per core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi128" }, "cpu-silicon.agi128.9": { "value": "128 MB SLC", "field": "L3 / domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi128" }, "cpu-silicon.agi128.10": { "value": "DDR5; 12; 8800 MT/s; 844.8 GB/s", "field": "Memory: channels; rate; GB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi128" }, "cpu-silicon.agi128.11": { "value": "2S; link rate n/d", "field": "Sockets / links", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi128" }, "cpu-silicon.agi128.12": { "value": "96 PCIe 6; CXL 3.0 Type 3", "field": "PCIe / CXL", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi128" }, "cpu-silicon.agi128.13": { "value": "300 W", "field": "TDP", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi128" }, "cpu-silicon.agi128.14": { "value": "2 x 128-bit SVE2; BF16; INT8 MMLA", "field": "Vector / matrix ISA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi128" }, "cpu-silicon.agi64.0": { "value": "AGI CPU 64C", "field": "Generation / reference SKU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi64" }, "cpu-silicon.agi64.1": { "value": "SP113012A", "field": "Codename", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi64" }, "cpu-silicon.agi64.2": { "value": "2026", "field": "GA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi64" }, "cpu-silicon.agi64.3": { "value": "Shipping / available", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi64" }, "cpu-silicon.agi64.4": { "value": "Neoverse V3", "field": "Core µarch", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi64" }, "cpu-silicon.agi64.5": { "value": "64 / 64", "field": "Cores / threads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi64" }, "cpu-silicon.agi64.6": { "value": "3 nm", "field": "Process per die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi64" }, "cpu-silicon.agi64.7": { "value": "Arm-designed server SoC", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi64" }, "cpu-silicon.agi64.8": { "value": "2 MB", "field": "L2 per core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi64" }, "cpu-silicon.agi64.9": { "value": "128 MB SLC", "field": "L3 / domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi64" }, "cpu-silicon.agi64.10": { "value": "DDR5; 12; 8800 MT/s; 844.8 GB/s", "field": "Memory: channels; rate; GB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi64" }, "cpu-silicon.agi64.11": { "value": "2S; link rate n/d", "field": "Sockets / links", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi64" }, "cpu-silicon.agi64.12": { "value": "96 PCIe 6; CXL 3.0 Type 3", "field": "PCIe / CXL", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi64" }, "cpu-silicon.agi64.13": { "value": "300 W", "field": "TDP", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi64" }, "cpu-silicon.agi64.14": { "value": "2 x 128-bit SVE2; BF16; INT8 MMLA", "field": "Vector / matrix ISA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14", "E15" ], "disclosure_date": "2026", "status": "available to order", "scope": "agi64" }, "interconnect.cmn600.0": { "value": "CMN-600 / CHI", "field": "Interconnect", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "cmn600" }, "interconnect.cmn600.1": { "value": "N1", "field": "Year / generation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "cmn600" }, "interconnect.cmn600.2": { "value": "n/a", "field": "Lane rate", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "cmn600" }, "interconnect.cmn600.3": { "value": "n/a", "field": "Lanes / link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "cmn600" }, "interconnect.cmn600.4": { "value": "n/d", "field": "GB/s per link per direction", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "cmn600" }, "interconnect.cmn600.5": { "value": "n/d", "field": "Links / device", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "cmn600" }, "interconnect.cmn600.6": { "value": "Coherent on-die mesh", "field": "Topology", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "cmn600" }, "interconnect.cmn600.7": { "value": "Implementation-defined", "field": "Domain limit", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "cmn600" }, "interconnect.cmn600.8": { "value": "Cache coherence; system cache", "field": "Coherence / semantics", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2019", "status": "licensable IP", "scope": "cmn600" }, "interconnect.cmn700.0": { "value": "CMN-700", "field": "Interconnect", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2021-2023", "status": "licensable IP", "scope": "cmn700" }, "interconnect.cmn700.1": { "value": "N2 / V2", "field": "Year / generation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2021-2023", "status": "licensable IP", "scope": "cmn700" }, "interconnect.cmn700.2": { "value": "n/a", "field": "Lane rate", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2021-2023", "status": "licensable IP", "scope": "cmn700" }, "interconnect.cmn700.3": { "value": "n/a", "field": "Lanes / link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2021-2023", "status": "licensable IP", "scope": "cmn700" }, "interconnect.cmn700.4": { "value": "n/d", "field": "GB/s per link per direction", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2021-2023", "status": "licensable IP", "scope": "cmn700" }, "interconnect.cmn700.5": { "value": "n/d", "field": "Links / device", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2021-2023", "status": "licensable IP", "scope": "cmn700" }, "interconnect.cmn700.6": { "value": "Coherent mesh; multi-chip integration", "field": "Topology", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2021-2023", "status": "licensable IP", "scope": "cmn700" }, "interconnect.cmn700.7": { "value": "n/d", "field": "Domain limit", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2021-2023", "status": "licensable IP", "scope": "cmn700" }, "interconnect.cmn700.8": { "value": "CHI", "field": "Coherence / semantics", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "C04" ], "disclosure_date": "2021-2023", "status": "licensable IP", "scope": "cmn700" }, "interconnect.cmns3.0": { "value": "CMN S3 / CHI C2C", "field": "Interconnect", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09", "P14", "E09" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "cmns3" }, "interconnect.cmns3.1": { "value": "V3 / N3", "field": "Year / generation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09", "P14", "E09" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "cmns3" }, "interconnect.cmns3.2": { "value": "n/d", "field": "Lane rate", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09", "P14", "E09" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "cmns3" }, "interconnect.cmns3.3": { "value": "n/d", "field": "Lanes / link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09", "P14", "E09" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "cmns3" }, "interconnect.cmns3.4": { "value": "n/d", "field": "GB/s per link per direction", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09", "P14", "E09" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "cmns3" }, "interconnect.cmns3.5": { "value": "n/d", "field": "Links / device", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09", "P14", "E09" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "cmns3" }, "interconnect.cmns3.6": { "value": "Mesh and chiplet links", "field": "Topology", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09", "P14", "E09" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "cmns3" }, "interconnect.cmns3.7": { "value": "n/d", "field": "Domain limit", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09", "P14", "E09" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "cmns3" }, "interconnect.cmns3.8": { "value": "Coherent subsystem integration", "field": "Coherence / semantics", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P09", "P14", "E09" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "cmns3" }, "interconnect.pcie6.0": { "value": "AGI CPU PCIe 6 / CXL 3", "field": "Interconnect", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "shipping", "scope": "pcie6" }, "interconnect.pcie6.1": { "value": "2026", "field": "Year / generation", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "shipping", "scope": "pcie6" }, "interconnect.pcie6.2": { "value": "64 GT/s", "field": "Lane rate", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "shipping", "scope": "pcie6" }, "interconnect.pcie6.3": { "value": "up to x16", "field": "Lanes / link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "shipping", "scope": "pcie6" }, "interconnect.pcie6.4": { "value": "~128 raw x16", "field": "GB/s per link per direction", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "shipping", "scope": "pcie6" }, "interconnect.pcie6.5": { "value": "96 lanes total", "field": "Links / device", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "shipping", "scope": "pcie6" }, "interconnect.pcie6.6": { "value": "Host I/O fabric", "field": "Topology", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "shipping", "scope": "pcie6" }, "interconnect.pcie6.7": { "value": "n/d", "field": "Domain limit", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "shipping", "scope": "pcie6" }, "interconnect.pcie6.8": { "value": "PCIe I/O; CXL Type 3 memory", "field": "Coherence / semantics", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "shipping", "scope": "pcie6" }, "network.none.0": { "value": "No Arm-branded AI NIC established", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E09", "P08" ], "disclosure_date": "2026", "status": "portfolio boundary", "scope": "none" }, "network.none.1": { "value": "n/a", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E09", "P08" ], "disclosure_date": "2026", "status": "portfolio boundary", "scope": "none" }, "network.none.2": { "value": "n/a", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E09", "P08" ], "disclosure_date": "2026", "status": "portfolio boundary", "scope": "none" }, "network.none.3": { "value": "IP supplier / CPU supplier", "field": "Class", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E09", "P08" ], "disclosure_date": "2026", "status": "portfolio boundary", "scope": "none" }, "network.none.4": { "value": "n/a", "field": "Ports × speed", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E09", "P08" ], "disclosure_date": "2026", "status": "portfolio boundary", "scope": "none" }, "network.none.5": { "value": "n/a", "field": "SerDes", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E09", "P08" ], "disclosure_date": "2026", "status": "portfolio boundary", "scope": "none" }, "network.none.6": { "value": "n/a", "field": "Host interface", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E09", "P08" ], "disclosure_date": "2026", "status": "portfolio boundary", "scope": "none" }, "network.none.7": { "value": "n/a", "field": "Programmable engine", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E09", "P08" ], "disclosure_date": "2026", "status": "portfolio boundary", "scope": "none" }, "network.none.8": { "value": "Neoverse licensed to device vendors", "field": "Embedded CPU", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E09", "P08" ], "disclosure_date": "2026", "status": "portfolio boundary", "scope": "none" }, "network.none.9": { "value": "n/a", "field": "On-card memory", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E09", "P08" ], "disclosure_date": "2026", "status": "portfolio boundary", "scope": "none" }, "network.none.10": { "value": "Licensee-specific", "field": "Transport / RDMA", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E09", "P08" ], "disclosure_date": "2026", "status": "portfolio boundary", "scope": "none" }, "network.none.11": { "value": "n/a", "field": "Congestion control", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E09", "P08" ], "disclosure_date": "2026", "status": "portfolio boundary", "scope": "none" }, "network.none.12": { "value": "CPU control; packet engines separate", "field": "Key offloads", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E09", "P08" ], "disclosure_date": "2026", "status": "portfolio boundary", "scope": "none" }, "network.none.13": { "value": "n/a", "field": "Power", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E09", "P08" ], "disclosure_date": "2026", "status": "portfolio boundary", "scope": "none" }, "accelerators.n78.0": { "value": "Ethos-N78", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E12" ], "disclosure_date": "2020", "status": "licensable IP", "scope": "n78" }, "accelerators.n78.1": { "value": "Ethos-N", "field": "Architecture", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E12" ], "disclosure_date": "2020", "status": "licensable IP", "scope": "n78" }, "accelerators.n78.2": { "value": "2020 IP", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E12" ], "disclosure_date": "2020", "status": "licensable IP", "scope": "n78" }, "accelerators.n78.3": { "value": "Licensable IP", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E12" ], "disclosure_date": "2020", "status": "licensable IP", "scope": "n78" }, "accelerators.n78.4": { "value": "n/a", "field": "Process", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E12" ], "disclosure_date": "2020", "status": "licensable IP", "scope": "n78" }, "accelerators.n78.5": { "value": "Integrated IP", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E12" ], "disclosure_date": "2020", "status": "licensable IP", "scope": "n78" }, "accelerators.n78.6": { "value": "configurable", "field": "Compute units", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E12" ], "disclosure_date": "2020", "status": "licensable IP", "scope": "n78" }, "accelerators.n78.7": { "value": "n/d", "field": "Dense BF16", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E12" ], "disclosure_date": "2020", "status": "licensable IP", "scope": "n78" }, "accelerators.n78.8": { "value": "n/d", "field": "Dense FP8", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E12" ], "disclosure_date": "2020", "status": "licensable IP", "scope": "n78" }, "accelerators.n78.9": { "value": "n/d", "field": "Dense FP6 / FP4", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E12" ], "disclosure_date": "2020", "status": "licensable IP", "scope": "n78" }, "accelerators.n78.10": { "value": "n/a", "field": "FP64 vector / matrix", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E12" ], "disclosure_date": "2020", "status": "licensable IP", "scope": "n78" }, "accelerators.n78.11": { "value": "HBM n/a; SoC memory", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E12" ], "disclosure_date": "2020", "status": "licensable IP", "scope": "n78" }, "accelerators.n78.12": { "value": "n/d", "field": "LLC / SRAM", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E12" ], "disclosure_date": "2020", "status": "licensable IP", "scope": "n78" }, "accelerators.n78.13": { "value": "n/a", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E12" ], "disclosure_date": "2020", "status": "licensable IP", "scope": "n78" }, "accelerators.n78.14": { "value": "SoC interconnect", "field": "Host link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E12" ], "disclosure_date": "2020", "status": "licensable IP", "scope": "n78" }, "accelerators.n78.15": { "value": "n/a", "field": "Power / cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E12" ], "disclosure_date": "2020", "status": "licensable IP", "scope": "n78" }, "accelerators.n78.16": { "value": "IP", "field": "Form factor", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E12" ], "disclosure_date": "2020", "status": "licensable IP", "scope": "n78" }, "accelerators.u85.0": { "value": "Ethos-U85", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "u85" }, "accelerators.u85.1": { "value": "Ethos-U", "field": "Architecture", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "u85" }, "accelerators.u85.2": { "value": "2024 IP", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "u85" }, "accelerators.u85.3": { "value": "Licensable IP", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "u85" }, "accelerators.u85.4": { "value": "n/a", "field": "Process", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "u85" }, "accelerators.u85.5": { "value": "Integrated IP", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "u85" }, "accelerators.u85.6": { "value": "128-2048 MACs", "field": "Compute units", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "u85" }, "accelerators.u85.7": { "value": "n/d", "field": "Dense BF16", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "u85" }, "accelerators.u85.8": { "value": "n/d", "field": "Dense FP8", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "u85" }, "accelerators.u85.9": { "value": "n/d", "field": "Dense FP6 / FP4", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "u85" }, "accelerators.u85.10": { "value": "n/a", "field": "FP64 vector / matrix", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "u85" }, "accelerators.u85.11": { "value": "HBM n/a; system SRAM/DRAM", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "u85" }, "accelerators.u85.12": { "value": "n/d", "field": "LLC / SRAM", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "u85" }, "accelerators.u85.13": { "value": "n/a", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "u85" }, "accelerators.u85.14": { "value": "SoC interconnect", "field": "Host link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "u85" }, "accelerators.u85.15": { "value": "n/a", "field": "Power / cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "u85" }, "accelerators.u85.16": { "value": "IP", "field": "Form factor", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P11", "E11" ], "disclosure_date": "2024", "status": "licensable IP", "scope": "u85" }, "accelerators.mali.0": { "value": "Mali G2-Ultra NX", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E10" ], "disclosure_date": "2026", "status": "announced IP", "scope": "mali" }, "accelerators.mali.1": { "value": "Mali", "field": "Architecture", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E10" ], "disclosure_date": "2026", "status": "announced IP", "scope": "mali" }, "accelerators.mali.2": { "value": "2026 IP", "field": "GA / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E10" ], "disclosure_date": "2026", "status": "announced IP", "scope": "mali" }, "accelerators.mali.3": { "value": "Announced; GA n/d", "field": "Status", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E10" ], "disclosure_date": "2026", "status": "announced IP", "scope": "mali" }, "accelerators.mali.4": { "value": "n/a", "field": "Process", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E10" ], "disclosure_date": "2026", "status": "announced IP", "scope": "mali" }, "accelerators.mali.5": { "value": "Mobile GPU IP", "field": "Dies / packaging", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E10" ], "disclosure_date": "2026", "status": "announced IP", "scope": "mali" }, "accelerators.mali.6": { "value": "n/d", "field": "Compute units", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E10" ], "disclosure_date": "2026", "status": "announced IP", "scope": "mali" }, "accelerators.mali.7": { "value": "n/d", "field": "Dense BF16", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E10" ], "disclosure_date": "2026", "status": "announced IP", "scope": "mali" }, "accelerators.mali.8": { "value": "n/d", "field": "Dense FP8", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E10" ], "disclosure_date": "2026", "status": "announced IP", "scope": "mali" }, "accelerators.mali.9": { "value": "n/d", "field": "Dense FP6 / FP4", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E10" ], "disclosure_date": "2026", "status": "announced IP", "scope": "mali" }, "accelerators.mali.10": { "value": "n/d", "field": "FP64 vector / matrix", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E10" ], "disclosure_date": "2026", "status": "announced IP", "scope": "mali" }, "accelerators.mali.11": { "value": "HBM n/a; shared SoC memory", "field": "Memory: type; stacks; GB; TB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E10" ], "disclosure_date": "2026", "status": "announced IP", "scope": "mali" }, "accelerators.mali.12": { "value": "n/d", "field": "LLC / SRAM", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E10" ], "disclosure_date": "2026", "status": "announced IP", "scope": "mali" }, "accelerators.mali.13": { "value": "n/a", "field": "Scale-up: links; GB/s per direction; domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E10" ], "disclosure_date": "2026", "status": "announced IP", "scope": "mali" }, "accelerators.mali.14": { "value": "SoC interconnect", "field": "Host link", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E10" ], "disclosure_date": "2026", "status": "announced IP", "scope": "mali" }, "accelerators.mali.15": { "value": "n/a", "field": "Power / cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E10" ], "disclosure_date": "2026", "status": "announced IP", "scope": "mali" }, "accelerators.mali.16": { "value": "IP", "field": "Form factor", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E10" ], "disclosure_date": "2026", "status": "announced IP", "scope": "mali" }, "software.aarch64.0": { "value": "AArch64 Linux / GCC / LLVM", "field": "Release / component", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2015-2026", "status": "available", "scope": "aarch64" }, "software.aarch64.1": { "value": "2015-2026", "field": "Date", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2015-2026", "status": "available", "scope": "aarch64" }, "software.aarch64.2": { "value": "Cortex, Neoverse and custom cores", "field": "Hardware enabled", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2015-2026", "status": "available", "scope": "aarch64" }, "software.aarch64.3": { "value": "Portable binaries; core-specific scheduling and ISA dispatch", "field": "Key features", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P08" ], "disclosure_date": "2015-2026", "status": "available", "scope": "aarch64" }, "software.compute.0": { "value": "Arm Compute Library", "field": "Release / component", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P13" ], "disclosure_date": "2026", "status": "available", "scope": "compute" }, "software.compute.1": { "value": "ongoing", "field": "Date", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P13" ], "disclosure_date": "2026", "status": "available", "scope": "compute" }, "software.compute.2": { "value": "Arm CPU / Mali", "field": "Hardware enabled", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P13" ], "disclosure_date": "2026", "status": "available", "scope": "compute" }, "software.compute.3": { "value": "Optimized AI operators; feature-dependent paths", "field": "Key features", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P13" ], "disclosure_date": "2026", "status": "available", "scope": "compute" }, "software.rd.0": { "value": "Neoverse reference software", "field": "Release / component", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P14" ], "disclosure_date": "2024", "status": "available", "scope": "rd" }, "software.rd.1": { "value": "2024 release", "field": "Date", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P14" ], "disclosure_date": "2024", "status": "available", "scope": "rd" }, "software.rd.2": { "value": "RD-V3 and related platforms", "field": "Hardware enabled", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P14" ], "disclosure_date": "2024", "status": "available", "scope": "rd" }, "software.rd.3": { "value": "Firmware and fixed virtual platform integration", "field": "Key features", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P14" ], "disclosure_date": "2024", "status": "available", "scope": "rd" }, "systems.licensee.0": { "value": "Licensee cloud server", "field": "Platform", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E08", "E16", "E17", "E18", "E19" ], "disclosure_date": "2026", "status": "mixed", "scope": "licensee" }, "systems.licensee.1": { "value": "2019-2026", "field": "Year / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E08", "E16", "E17", "E18", "E19" ], "disclosure_date": "2026", "status": "mixed", "scope": "licensee" }, "systems.licensee.2": { "value": "Graviton / Axion / Cobalt", "field": "CPU / accelerator count", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E08", "E16", "E17", "E18", "E19" ], "disclosure_date": "2026", "status": "mixed", "scope": "licensee" }, "systems.licensee.3": { "value": "Provider-specific", "field": "Scale-up domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E08", "E16", "E17", "E18", "E19" ], "disclosure_date": "2026", "status": "mixed", "scope": "licensee" }, "systems.licensee.4": { "value": "n/d", "field": "Scale-out per accelerator", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E08", "E16", "E17", "E18", "E19" ], "disclosure_date": "2026", "status": "mixed", "scope": "licensee" }, "systems.licensee.5": { "value": "n/d", "field": "Rack power", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E08", "E16", "E17", "E18", "E19" ], "disclosure_date": "2026", "status": "mixed", "scope": "licensee" }, "systems.licensee.6": { "value": "n/d", "field": "Cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E08", "E16", "E17", "E18", "E19" ], "disclosure_date": "2026", "status": "mixed", "scope": "licensee" }, "systems.agi.0": { "value": "AGI CPU 1OU dual-node reference", "field": "Platform", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E13" ], "disclosure_date": "2026", "status": "available reference", "scope": "agi" }, "systems.agi.1": { "value": "2026", "field": "Year / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E13" ], "disclosure_date": "2026", "status": "available reference", "scope": "agi" }, "systems.agi.2": { "value": "2 x AGI CPU", "field": "CPU / accelerator count", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E13" ], "disclosure_date": "2026", "status": "available reference", "scope": "agi" }, "systems.agi.3": { "value": "Two independent nodes", "field": "Scale-up domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E13" ], "disclosure_date": "2026", "status": "available reference", "scope": "agi" }, "systems.agi.4": { "value": "n/d", "field": "Scale-out per accelerator", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E13" ], "disclosure_date": "2026", "status": "available reference", "scope": "agi" }, "systems.agi.5": { "value": "36 kW example; 8160 cores", "field": "Rack power", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E13" ], "disclosure_date": "2026", "status": "available reference", "scope": "agi" }, "systems.agi.6": { "value": "Air", "field": "Cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E13" ], "disclosure_date": "2026", "status": "available reference", "scope": "agi" }, "systems.agi2.0": { "value": "AGI CPU 2U2P reference", "field": "Platform", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14" ], "disclosure_date": "2026", "status": "available reference", "scope": "agi2" }, "systems.agi2.1": { "value": "2026", "field": "Year / milestone", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14" ], "disclosure_date": "2026", "status": "available reference", "scope": "agi2" }, "systems.agi2.2": { "value": "2 x AGI CPU", "field": "CPU / accelerator count", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14" ], "disclosure_date": "2026", "status": "available reference", "scope": "agi2" }, "systems.agi2.3": { "value": "2-socket coherent server", "field": "Scale-up domain", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14" ], "disclosure_date": "2026", "status": "available reference", "scope": "agi2" }, "systems.agi2.4": { "value": "n/d", "field": "Scale-out per accelerator", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14" ], "disclosure_date": "2026", "status": "available reference", "scope": "agi2" }, "systems.agi2.5": { "value": "n/d", "field": "Rack power", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14" ], "disclosure_date": "2026", "status": "available reference", "scope": "agi2" }, "systems.agi2.6": { "value": "Air", "field": "Cooling", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E14" ], "disclosure_date": "2026", "status": "available reference", "scope": "agi2" }, "ratios.agi136.0": { "value": "AGI 136C", "field": "Configuration", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "derived", "scope": "agi136" }, "ratios.agi136.1": { "value": "844.8", "field": "DRAM peak GB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "derived", "scope": "agi136" }, "ratios.agi136.2": { "value": "6.21", "field": "GB/s/core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "derived", "scope": "agi136" }, "ratios.agi136.3": { "value": "0.94", "field": "SLC MB/core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "derived", "scope": "agi136" }, "ratios.agi136.4": { "value": "Equal-share ratio; not a reservation", "field": "Meaning", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "derived", "scope": "agi136" }, "ratios.agi128.0": { "value": "AGI 128C", "field": "Configuration", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "derived", "scope": "agi128" }, "ratios.agi128.1": { "value": "844.8", "field": "DRAM peak GB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "derived", "scope": "agi128" }, "ratios.agi128.2": { "value": "6.60", "field": "GB/s/core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "derived", "scope": "agi128" }, "ratios.agi128.3": { "value": "1.00", "field": "SLC MB/core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "derived", "scope": "agi128" }, "ratios.agi128.4": { "value": "Same interface, fewer active cores", "field": "Meaning", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "derived", "scope": "agi128" }, "ratios.agi64.0": { "value": "AGI 64C", "field": "Configuration", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "derived", "scope": "agi64" }, "ratios.agi64.1": { "value": "844.8", "field": "DRAM peak GB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "derived", "scope": "agi64" }, "ratios.agi64.2": { "value": "13.20", "field": "GB/s/core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "derived", "scope": "agi64" }, "ratios.agi64.3": { "value": "2.00", "field": "SLC MB/core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "derived", "scope": "agi64" }, "ratios.agi64.4": { "value": "Memory and cache capacity per core increase", "field": "Meaning", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "derived", "scope": "agi64" }, "ratios.graviton4.0": { "value": "Graviton4 96C", "field": "Configuration", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E16" ], "disclosure_date": "2024", "status": "derived", "scope": "graviton4" }, "ratios.graviton4.1": { "value": "537.6", "field": "DRAM peak GB/s", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E16" ], "disclosure_date": "2024", "status": "derived", "scope": "graviton4" }, "ratios.graviton4.2": { "value": "5.60", "field": "GB/s/core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E16" ], "disclosure_date": "2024", "status": "derived", "scope": "graviton4" }, "ratios.graviton4.3": { "value": "n/d", "field": "SLC MB/core", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E16" ], "disclosure_date": "2024", "status": "derived", "scope": "graviton4" }, "ratios.graviton4.4": { "value": "12 x DDR5-5600; AWS implementation", "field": "Meaning", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E16" ], "disclosure_date": "2024", "status": "derived", "scope": "graviton4" }, "conference.n1hc.0": { "value": "Hot Chips", "field": "Venue", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2019", "status": "disclosed", "scope": "n1hc" }, "conference.n1hc.1": { "value": "2019", "field": "Year", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2019", "status": "disclosed", "scope": "n1hc" }, "conference.n1hc.2": { "value": "Neoverse N1 Cloud-to-Edge Infrastructure SoCs", "field": "Paper / talk / disclosure", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2019", "status": "disclosed", "scope": "n1hc" }, "conference.n1hc.3": { "value": "Arm", "field": "Presenter / authors", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2019", "status": "disclosed", "scope": "n1hc" }, "conference.n1hc.4": { "value": "N1", "field": "Product", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2019", "status": "disclosed", "scope": "n1hc" }, "conference.n1hc.5": { "value": "Architecture", "field": "Evidence type", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2019", "status": "disclosed", "scope": "n1hc" }, "conference.n1hc.6": { "value": "P01", "field": "Source", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01" ], "disclosure_date": "2019", "status": "disclosed", "scope": "n1hc" }, "conference.n1isscc.0": { "value": "ISSCC", "field": "Venue", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01" ], "disclosure_date": "2020", "status": "disclosed", "scope": "n1isscc" }, "conference.n1isscc.1": { "value": "2020", "field": "Year", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01" ], "disclosure_date": "2020", "status": "disclosed", "scope": "n1isscc" }, "conference.n1isscc.2": { "value": "A 3GHz Arm Neoverse N1 CPU in 7nm FinFET for Infrastructure Applications", "field": "Paper / talk / disclosure", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C01" ], "disclosure_date": "2020", "status": "disclosed", "scope": "n1isscc" }, "conference.n1isscc.3": { "value": "R. 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"scope": "demeter" }, "crosswalk.demeter.1": { "value": "Core used by Grace, Axion and Graviton4", "field": "Meaning", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "E08" ], "disclosure_date": "2023", "status": "IP", "scope": "demeter" }, "crosswalk.demeter.2": { "value": "Arm core; partner SoCs", "field": "Owner / boundary", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C02", "E08" ], "disclosure_date": "2023", "status": "IP", "scope": "demeter" }, "crosswalk.css.0": { "value": "CSS", "field": "Name", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2023", "status": "IP", "scope": "css" }, "crosswalk.css.1": { "value": "Preintegrated compute subsystem", "field": "Meaning", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2023", "status": "IP", "scope": "css" }, "crosswalk.css.2": { "value": "Not a complete merchant chip", "field": "Owner / boundary", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E03" ], "disclosure_date": "2023", "status": "IP", "scope": "css" }, "crosswalk.agi.0": { "value": "AGI CPU", "field": "Name", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E06" ], "disclosure_date": "2026", "status": "shipping", "scope": "agi" }, "crosswalk.agi.1": { "value": "Arm-designed server silicon", "field": "Meaning", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E06" ], "disclosure_date": "2026", "status": "shipping", "scope": "agi" }, "crosswalk.agi.2": { "value": "V3-based; not CSS N4", "field": "Owner / boundary", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07", "E06" ], "disclosure_date": "2026", "status": "shipping", "scope": "agi" }, "crosswalk.custom.0": { "value": "Falkor / Oryon / AmpereOne / Vera", "field": "Name", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03", "E08" ], "disclosure_date": "2026", "status": "ownership boundary", "scope": "custom" }, "crosswalk.custom.1": { "value": "Custom Arm-compatible cores or products", "field": "Meaning", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03", "E08" ], "disclosure_date": "2026", "status": "ownership boundary", "scope": "custom" }, "crosswalk.custom.2": { "value": "Licensee designs; not Neoverse aliases", "field": "Owner / boundary", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "C03", "E08" ], "disclosure_date": "2026", "status": "ownership boundary", "scope": "custom" }, "hierarchy.early.0": { "value": "2015-2018", "field": "Era", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E08" ], "disclosure_date": "2015-2018", "status": "mixed", "scope": "early" }, "hierarchy.early.1": { "value": "Licensee fabric", "field": "On-die / die-to-die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E08" ], "disclosure_date": "2015-2018", "status": "mixed", "scope": "early" }, "hierarchy.early.2": { "value": "Licensee DDR", "field": "Memory", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E08" ], "disclosure_date": "2015-2018", "status": "mixed", "scope": "early" }, "hierarchy.early.3": { "value": "PCIe; n/d", "field": "Host attach", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E08" ], "disclosure_date": "2015-2018", "status": "mixed", "scope": "early" }, "hierarchy.early.4": { "value": "Licensee network; n/d", "field": "Scale-up / scale-out", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E08" ], "disclosure_date": "2015-2018", "status": "mixed", "scope": "early" }, "hierarchy.n1.0": { "value": "2019-2022", "field": "Era", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "C04" ], "disclosure_date": "2019-2022", "status": "mixed", "scope": "n1" }, "hierarchy.n1.1": { "value": "CMN-600/700; n/d", "field": "On-die / die-to-die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "C04" ], "disclosure_date": "2019-2022", "status": "mixed", "scope": "n1" }, "hierarchy.n1.2": { "value": "Partner-configured DDR; n/d", "field": "Memory", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "C04" ], "disclosure_date": "2019-2022", "status": "mixed", "scope": "n1" }, "hierarchy.n1.3": { "value": "PCIe / CCIX; n/d", "field": "Host attach", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "C04" ], "disclosure_date": "2019-2022", "status": "mixed", "scope": "n1" }, "hierarchy.n1.4": { "value": "No universal Arm link", "field": "Scale-up / scale-out", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P01", "C04" ], "disclosure_date": "2019-2022", "status": "mixed", "scope": "n1" }, "hierarchy.css.0": { "value": "2023-2025", "field": "Era", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E16", "P15", "E09" ], "disclosure_date": "2023-2025", "status": "mixed", "scope": "css" }, "hierarchy.css.1": { "value": "CMN / CHI C2C; n/d", "field": "On-die / die-to-die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E16", "P15", "E09" ], "disclosure_date": "2023-2025", "status": "mixed", "scope": "css" }, "hierarchy.css.2": { "value": "Graviton4: 537.6 GB/s peak", "field": "Memory", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E16", "P15", "E09" ], "disclosure_date": "2023-2025", "status": "mixed", "scope": "css" }, "hierarchy.css.3": { "value": "Grace C2C is NVIDIA-owned", "field": "Host attach", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E16", "P15", "E09" ], "disclosure_date": "2023-2025", "status": "mixed", "scope": "css" }, "hierarchy.css.4": { "value": "Partner-specific", "field": "Scale-up / scale-out", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "E16", "P15", "E09" ], "disclosure_date": "2023-2025", "status": "mixed", "scope": "css" }, "hierarchy.agi.0": { "value": "2026", "field": "Era", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "shipping", "scope": "agi" }, "hierarchy.agi.1": { "value": "CMN; D2D n/d", "field": "On-die / die-to-die", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "shipping", "scope": "agi" }, "hierarchy.agi.2": { "value": "AGI: 844.8 GB/s derived peak", "field": "Memory", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "shipping", "scope": "agi" }, "hierarchy.agi.3": { "value": "PCIe 6 x16 ~128 GB/s raw", "field": "Host attach", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "shipping", "scope": "agi" }, "hierarchy.agi.4": { "value": "External XPU/NIC; n/d", "field": "Scale-up / scale-out", "basis": "Per reference product; theoretical peak; decimal bandwidth; direction and format as labelled", "source": [ "P07" ], "disclosure_date": "2026", "status": "shipping", "scope": "agi" } }, "numeric_facts": { "agi136.cores": { "value": 136, "unit": "cores", "scope": "CPU package", "source": [ "P07" ], "status": "shipping", "basis": "theoretical peak", "direction": "n/a", "format": "n/a", "date": "2026-09-28" }, "agi136.dram": { "value": 844.8, "unit": "GB/s", "scope": "CPU package", "source": [ "P07" ], "status": "shipping", "basis": "12 x 8800 MT/s x 8 B; theoretical payload", "direction": "n/a", "format": "n/a", "date": "2026-09-28" }, "agi136.dram_per_core": { "value": 6.21, "unit": "GB/s/core", "scope": "CPU package", "source": [ "P07" ], "status": "derived", "basis": "equal share; not guaranteed", "direction": "n/a", "format": "n/a", "date": "2026-09-28" }, "agi136.slc_per_core": { "value": 0.94, "unit": "MB/core", "scope": "CPU package", "source": [ "P07" ], "status": "derived", "basis": "theoretical peak", "direction": "n/a", "format": "n/a", "date": "2026-09-28" }, "agi128.cores": { "value": 128, "unit": "cores", "scope": "CPU package", "source": [ "P07" ], "status": "shipping", "basis": "theoretical peak", "direction": "n/a", "format": "n/a", "date": "2026-09-28" }, "agi128.dram": { "value": 844.8, "unit": "GB/s", "scope": "CPU package", "source": [ "P07" ], "status": "shipping", "basis": "12 x 8800 MT/s x 8 B; theoretical payload", "direction": "n/a", "format": "n/a", "date": "2026-09-28" }, "agi128.dram_per_core": { "value": 6.6, "unit": "GB/s/core", "scope": "CPU package", "source": [ "P07" ], "status": "derived", "basis": "equal share; not guaranteed", "direction": "n/a", "format": "n/a", "date": "2026-09-28" }, "agi128.slc_per_core": { "value": 1.0, "unit": "MB/core", "scope": "CPU package", "source": [ "P07" ], "status": "derived", "basis": "theoretical peak", "direction": "n/a", "format": "n/a", "date": "2026-09-28" }, "agi64.cores": { "value": 64, "unit": "cores", "scope": "CPU package", "source": [ "P07" ], "status": "shipping", "basis": "theoretical peak", "direction": "n/a", "format": "n/a", "date": "2026-09-28" }, "agi64.dram": { "value": 844.8, "unit": "GB/s", "scope": "CPU package", "source": [ "P07" ], "status": "shipping", "basis": "12 x 8800 MT/s x 8 B; theoretical payload", "direction": "n/a", "format": "n/a", "date": "2026-09-28" }, "agi64.dram_per_core": { "value": 13.2, "unit": "GB/s/core", "scope": "CPU package", "source": [ "P07" ], "status": "derived", "basis": "equal share; not guaranteed", "direction": "n/a", "format": "n/a", "date": "2026-09-28" }, "agi64.slc_per_core": { "value": 2.0, "unit": "MB/core", "scope": "CPU package", "source": [ "P07" ], "status": "derived", "basis": "theoretical peak", "direction": "n/a", "format": "n/a", "date": "2026-09-28" }, "cssn4.cores": { "value": 128, "unit": "cores", "scope": "subsystem die maximum", "source": [ "P06" ], "status": "announced IP", "basis": "theoretical peak", "direction": "n/a", "format": "n/a", "date": "2026-09-28" }, "u85.int8": { "value": 4.096, "unit": "TOPS", "scope": "2048 MAC configuration at 1 GHz", "source": [ "P11" ], "status": "derived", "basis": "MAC=2; not BF16", "direction": "n/a", "format": "INT8", "date": "2026-09-28" } }, "sources": { "P01": { "id": "P01", "title": "The Arm Neoverse N1 Platform: Building Blocks for the Next-Gen Cloud-to-Edge Infrastructure SoC", "url": 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"id": "E12", "title": "Ethos-N78 and Mali-G78, 2020", "url": "https://newsroom.arm.com/news/new-arm-ip-delivers-true-digital-immersion-for-the-5g-era", "retrieved": "2026-09-28", "access": "Full accessible document text" }, "E13": { "id": "E13", "title": "Arm AGI CPU 1OU dual-node reference server", "url": "https://developer.arm.com/community/arm-community-blogs/b/servers-and-cloud-computing-blog/posts/introducing-the-arm-agi-cpu-1ou-dual-node-reference-server", "retrieved": "2026-09-28", "access": "Full accessible document text" }, "E14": { "id": "E14", "title": "Supermicro Arm AGI CPU systems datasheet", "url": "https://www.supermicro.com/datasheet/datasheet_Supermicro_Arm_AGI.pdf", "retrieved": "2026-09-28", "access": "Full accessible document text" }, "R01": { "id": "R01", "title": "Verified Security for the Morello Capability-enhanced Prototype Arm Architecture", "url": "https://link.springer.com/chapter/10.1007/978-3-030-99336-8_7", "retrieved": "2026-09-28", "access": "Full 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